1//===- ARCRegisterInfo.td - ARC Register defs --------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Declarations that describe the ARC register file 11//===----------------------------------------------------------------------===// 12 13class ARCReg<string n, list<string> altNames> : Register<n, altNames> { 14 field bits<6> HwEncoding; 15 let Namespace = "ARC"; 16} 17 18// Registers are identified with 6-bit ID numbers. 19// Core - 32-bit core registers 20class Core<int num, string n, list<string>altNames=[]> : ARCReg<n, altNames> { 21 let HWEncoding = num; 22} 23 24class Status<string n> : ARCReg<n, []> { 25} 26 27// Integer registers 28def R0 : Core< 0, "%r0">, DwarfRegNum<[0]>; 29def R1 : Core< 1, "%r1">, DwarfRegNum<[1]>; 30def R2 : Core< 2, "%r2">, DwarfRegNum<[2]>; 31def R3 : Core< 3, "%r3">, DwarfRegNum<[3]>; 32let CostPerUse=[1] in { 33def R4 : Core< 4, "%r4">, DwarfRegNum<[4]>; 34def R5 : Core< 5, "%r5">, DwarfRegNum<[5]>; 35def R6 : Core< 6, "%r6">, DwarfRegNum<[6]>; 36def R7 : Core< 7, "%r7">, DwarfRegNum<[7]>; 37def R8 : Core< 8, "%r8">, DwarfRegNum<[8]>; 38def R9 : Core< 9, "%r9">, DwarfRegNum<[9]>; 39def R10 : Core<10, "%r10">, DwarfRegNum<[10]>; 40def R11 : Core<11, "%r11">, DwarfRegNum<[11]>; 41} 42def R12 : Core<12, "%r12">, DwarfRegNum<[12]>; 43def R13 : Core<13, "%r13">, DwarfRegNum<[13]>; 44def R14 : Core<14, "%r14">, DwarfRegNum<[14]>; 45def R15 : Core<15, "%r15">, DwarfRegNum<[15]>; 46 47let CostPerUse=[1] in { 48def R16 : Core<16, "%r16">, DwarfRegNum<[16]>; 49def R17 : Core<17, "%r17">, DwarfRegNum<[17]>; 50def R18 : Core<18, "%r18">, DwarfRegNum<[18]>; 51def R19 : Core<19, "%r19">, DwarfRegNum<[19]>; 52def R20 : Core<20, "%r20">, DwarfRegNum<[20]>; 53def R21 : Core<21, "%r21">, DwarfRegNum<[21]>; 54def R22 : Core<22, "%r22">, DwarfRegNum<[22]>; 55def R23 : Core<23, "%r23">, DwarfRegNum<[23]>; 56def R24 : Core<24, "%r24">, DwarfRegNum<[24]>; 57def R25 : Core<25, "%r25">, DwarfRegNum<[25]>; 58def GP : Core<26, "%gp",["%r26"]>, DwarfRegNum<[26]>; 59def FP : Core<27, "%fp", ["%r27"]>, DwarfRegNum<[27]>; 60def SP : Core<28, "%sp", ["%r28"]>, DwarfRegNum<[28]>; 61def ILINK : Core<29, "%ilink">, DwarfRegNum<[29]>; 62def R30 : Core<30, "%r30">, DwarfRegNum<[30]>; 63def BLINK: Core<31, "%blink">, DwarfRegNum<[31]>; 64 65def STATUS32 : Status<"status32">, DwarfRegNum<[32]>; 66} 67 68// Register classes. 69// 70def GPR32: RegisterClass<"ARC", [i32], 32, 71 (add R0, R1, R2, R3, 72 R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, 73 R20, R21, R22, R23, R24, R25, GP, FP, SP, ILINK, R30, BLINK)>; 74 75def SREG : RegisterClass<"ARC", [i32], 1, (add STATUS32)>; 76 77def GPR_S : RegisterClass<"ARC", [i32], 8, 78 (add R0, R1, R2, R3, R12, R13, R14, R15)>; 79 80