1 //===-- ARM.h - Top-level interface for ARM representation ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the entry points for global functions defined in the LLVM
10 // ARM back-end.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_ARM_ARM_H
15 #define LLVM_LIB_TARGET_ARM_ARM_H
16 
17 #include "llvm/IR/LegacyPassManager.h"
18 #include "llvm/Support/CodeGen.h"
19 #include <functional>
20 #include <vector>
21 
22 namespace llvm {
23 
24 class ARMAsmPrinter;
25 class ARMBaseTargetMachine;
26 class ARMRegisterBankInfo;
27 class ARMSubtarget;
28 class Function;
29 class FunctionPass;
30 class InstructionSelector;
31 class MachineInstr;
32 class MCInst;
33 class PassRegistry;
34 
35 Pass *createMVETailPredicationPass();
36 FunctionPass *createARMLowOverheadLoopsPass();
37 FunctionPass *createARMBlockPlacementPass();
38 Pass *createARMParallelDSPPass();
39 FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM,
40                                CodeGenOpt::Level OptLevel);
41 FunctionPass *createA15SDOptimizerPass();
42 FunctionPass *createARMLoadStoreOptimizationPass(bool PreAlloc = false);
43 FunctionPass *createARMExpandPseudoPass();
44 FunctionPass *createARMBranchTargetsPass();
45 FunctionPass *createARMConstantIslandPass();
46 FunctionPass *createMLxExpansionPass();
47 FunctionPass *createThumb2ITBlockPass();
48 FunctionPass *createMVEVPTBlockPass();
49 FunctionPass *createMVETPAndVPTOptimisationsPass();
50 FunctionPass *createARMOptimizeBarriersPass();
51 FunctionPass *createThumb2SizeReductionPass(
52     std::function<bool(const Function &)> Ftor = nullptr);
53 InstructionSelector *
54 createARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI,
55                              const ARMRegisterBankInfo &RBI);
56 Pass *createMVEGatherScatterLoweringPass();
57 FunctionPass *createARMSLSHardeningPass();
58 FunctionPass *createARMIndirectThunks();
59 Pass *createMVELaneInterleavingPass();
60 
61 void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
62                                   ARMAsmPrinter &AP);
63 
64 void initializeARMParallelDSPPass(PassRegistry &);
65 void initializeARMLoadStoreOptPass(PassRegistry &);
66 void initializeARMPreAllocLoadStoreOptPass(PassRegistry &);
67 void initializeARMBranchTargetsPass(PassRegistry &);
68 void initializeARMConstantIslandsPass(PassRegistry &);
69 void initializeARMExpandPseudoPass(PassRegistry &);
70 void initializeThumb2SizeReducePass(PassRegistry &);
71 void initializeThumb2ITBlockPass(PassRegistry &);
72 void initializeMVEVPTBlockPass(PassRegistry &);
73 void initializeMVETPAndVPTOptimisationsPass(PassRegistry &);
74 void initializeARMLowOverheadLoopsPass(PassRegistry &);
75 void initializeARMBlockPlacementPass(PassRegistry &);
76 void initializeMVETailPredicationPass(PassRegistry &);
77 void initializeMVEGatherScatterLoweringPass(PassRegistry &);
78 void initializeARMSLSHardeningPass(PassRegistry &);
79 void initializeMVELaneInterleavingPass(PassRegistry &);
80 
81 } // end namespace llvm
82 
83 #endif // LLVM_LIB_TARGET_ARM_ARM_H
84