1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the Base ARM implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H 14 #define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H 15 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/ADT/DenseMap.h" 18 #include "llvm/ADT/SmallSet.h" 19 #include "llvm/CodeGen/MachineBasicBlock.h" 20 #include "llvm/CodeGen/MachineInstr.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineOperand.h" 23 #include "llvm/CodeGen/TargetInstrInfo.h" 24 #include "llvm/IR/IntrinsicInst.h" 25 #include "llvm/IR/IntrinsicsARM.h" 26 #include <array> 27 #include <cstdint> 28 29 #define GET_INSTRINFO_HEADER 30 #include "ARMGenInstrInfo.inc" 31 32 namespace llvm { 33 34 class ARMBaseRegisterInfo; 35 class ARMSubtarget; 36 37 class ARMBaseInstrInfo : public ARMGenInstrInfo { 38 const ARMSubtarget &Subtarget; 39 40 protected: 41 // Can be only subclassed. 42 explicit ARMBaseInstrInfo(const ARMSubtarget &STI); 43 44 void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, 45 unsigned LoadImmOpc, unsigned LoadOpc) const; 46 47 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI 48 /// and \p DefIdx. 49 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of 50 /// the list is modeled as <Reg:SubReg, SubIdx>. 51 /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce 52 /// two elements: 53 /// - %1:sub1, sub0 54 /// - %2<:0>, sub1 55 /// 56 /// \returns true if it is possible to build such an input sequence 57 /// with the pair \p MI, \p DefIdx. False otherwise. 58 /// 59 /// \pre MI.isRegSequenceLike(). 60 bool getRegSequenceLikeInputs( 61 const MachineInstr &MI, unsigned DefIdx, 62 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override; 63 64 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI 65 /// and \p DefIdx. 66 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG. 67 /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce: 68 /// - %1:sub1, sub0 69 /// 70 /// \returns true if it is possible to build such an input sequence 71 /// with the pair \p MI, \p DefIdx. False otherwise. 72 /// 73 /// \pre MI.isExtractSubregLike(). 74 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, 75 RegSubRegPairAndIdx &InputReg) const override; 76 77 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI 78 /// and \p DefIdx. 79 /// \p [out] BaseReg and \p [out] InsertedReg contain 80 /// the equivalent inputs of INSERT_SUBREG. 81 /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce: 82 /// - BaseReg: %0:sub0 83 /// - InsertedReg: %1:sub1, sub3 84 /// 85 /// \returns true if it is possible to build such an input sequence 86 /// with the pair \p MI, \p DefIdx. False otherwise. 87 /// 88 /// \pre MI.isInsertSubregLike(). 89 bool 90 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, 91 RegSubRegPair &BaseReg, 92 RegSubRegPairAndIdx &InsertedReg) const override; 93 94 /// Commutes the operands in the given instruction. 95 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2. 96 /// 97 /// Do not call this method for a non-commutable instruction or for 98 /// non-commutable pair of operand indices OpIdx1 and OpIdx2. 99 /// Even though the instruction is commutable, the method may still 100 /// fail to commute the operands, null pointer is returned in such cases. 101 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 102 unsigned OpIdx1, 103 unsigned OpIdx2) const override; 104 /// If the specific machine instruction is an instruction that moves/copies 105 /// value from one register to another register return destination and source 106 /// registers as machine operands. 107 Optional<DestSourcePair> 108 isCopyInstrImpl(const MachineInstr &MI) const override; 109 110 /// Specialization of \ref TargetInstrInfo::describeLoadedValue, used to 111 /// enhance debug entry value descriptions for ARM targets. 112 Optional<ParamLoadedValue> describeLoadedValue(const MachineInstr &MI, 113 Register Reg) const override; 114 115 public: 116 // Return whether the target has an explicit NOP encoding. 117 bool hasNOP() const; 118 119 // Return the non-pre/post incrementing version of 'Opc'. Return 0 120 // if there is not such an opcode. 121 virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0; 122 123 MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, 124 LiveIntervals *LIS) const override; 125 126 virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0; 127 const ARMSubtarget &getSubtarget() const { return Subtarget; } 128 129 ScheduleHazardRecognizer * 130 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, 131 const ScheduleDAG *DAG) const override; 132 133 ScheduleHazardRecognizer * 134 CreateTargetMIHazardRecognizer(const InstrItineraryData *II, 135 const ScheduleDAGMI *DAG) const override; 136 137 ScheduleHazardRecognizer * 138 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 139 const ScheduleDAG *DAG) const override; 140 141 // Branch analysis. 142 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 143 MachineBasicBlock *&FBB, 144 SmallVectorImpl<MachineOperand> &Cond, 145 bool AllowModify = false) const override; 146 unsigned removeBranch(MachineBasicBlock &MBB, 147 int *BytesRemoved = nullptr) const override; 148 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 149 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 150 const DebugLoc &DL, 151 int *BytesAdded = nullptr) const override; 152 153 bool 154 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 155 156 // Predication support. 157 bool isPredicated(const MachineInstr &MI) const override; 158 159 // MIR printer helper function to annotate Operands with a comment. 160 std::string 161 createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, 162 unsigned OpIdx, 163 const TargetRegisterInfo *TRI) const override; 164 165 ARMCC::CondCodes getPredicate(const MachineInstr &MI) const { 166 int PIdx = MI.findFirstPredOperandIdx(); 167 return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm() 168 : ARMCC::AL; 169 } 170 171 bool PredicateInstruction(MachineInstr &MI, 172 ArrayRef<MachineOperand> Pred) const override; 173 174 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1, 175 ArrayRef<MachineOperand> Pred2) const override; 176 177 bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred, 178 bool SkipDead) const override; 179 180 bool isPredicable(const MachineInstr &MI) const override; 181 182 // CPSR defined in instruction 183 static bool isCPSRDefined(const MachineInstr &MI); 184 185 /// GetInstSize - Returns the size of the specified MachineInstr. 186 /// 187 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 188 189 unsigned isLoadFromStackSlot(const MachineInstr &MI, 190 int &FrameIndex) const override; 191 unsigned isStoreToStackSlot(const MachineInstr &MI, 192 int &FrameIndex) const override; 193 unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, 194 int &FrameIndex) const override; 195 unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, 196 int &FrameIndex) const override; 197 198 void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 199 unsigned SrcReg, bool KillSrc, 200 const ARMSubtarget &Subtarget) const; 201 void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 202 unsigned DestReg, bool KillSrc, 203 const ARMSubtarget &Subtarget) const; 204 205 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 206 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 207 bool KillSrc) const override; 208 209 void storeRegToStackSlot(MachineBasicBlock &MBB, 210 MachineBasicBlock::iterator MBBI, 211 Register SrcReg, bool isKill, int FrameIndex, 212 const TargetRegisterClass *RC, 213 const TargetRegisterInfo *TRI) const override; 214 215 void loadRegFromStackSlot(MachineBasicBlock &MBB, 216 MachineBasicBlock::iterator MBBI, 217 Register DestReg, int FrameIndex, 218 const TargetRegisterClass *RC, 219 const TargetRegisterInfo *TRI) const override; 220 221 bool expandPostRAPseudo(MachineInstr &MI) const override; 222 223 bool shouldSink(const MachineInstr &MI) const override; 224 225 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 226 Register DestReg, unsigned SubIdx, 227 const MachineInstr &Orig, 228 const TargetRegisterInfo &TRI) const override; 229 230 MachineInstr & 231 duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, 232 const MachineInstr &Orig) const override; 233 234 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg, 235 unsigned SubIdx, unsigned State, 236 const TargetRegisterInfo *TRI) const; 237 238 bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, 239 const MachineRegisterInfo *MRI) const override; 240 241 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 242 /// determine if two loads are loading from the same base address. It should 243 /// only return true if the base pointers are the same and the only 244 /// differences between the two addresses is the offset. It also returns the 245 /// offsets by reference. 246 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, 247 int64_t &Offset2) const override; 248 249 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 250 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads 251 /// should be scheduled togther. On some targets if two loads are loading from 252 /// addresses in the same cache line, it's better if they are scheduled 253 /// together. This function takes two integers that represent the load offsets 254 /// from the common base address. It returns true if it decides it's desirable 255 /// to schedule the two loads together. "NumLoads" is the number of loads that 256 /// have already been scheduled after Load1. 257 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 258 int64_t Offset1, int64_t Offset2, 259 unsigned NumLoads) const override; 260 261 bool isSchedulingBoundary(const MachineInstr &MI, 262 const MachineBasicBlock *MBB, 263 const MachineFunction &MF) const override; 264 265 bool isProfitableToIfCvt(MachineBasicBlock &MBB, 266 unsigned NumCycles, unsigned ExtraPredCycles, 267 BranchProbability Probability) const override; 268 269 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT, 270 unsigned ExtraT, MachineBasicBlock &FMBB, 271 unsigned NumF, unsigned ExtraF, 272 BranchProbability Probability) const override; 273 274 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 275 BranchProbability Probability) const override { 276 return NumCycles == 1; 277 } 278 279 unsigned extraSizeToPredicateInstructions(const MachineFunction &MF, 280 unsigned NumInsts) const override; 281 unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const override; 282 283 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 284 MachineBasicBlock &FMBB) const override; 285 286 /// analyzeCompare - For a comparison instruction, return the source registers 287 /// in SrcReg and SrcReg2 if having two register operands, and the value it 288 /// compares against in CmpValue. Return true if the comparison instruction 289 /// can be analyzed. 290 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, 291 Register &SrcReg2, int64_t &CmpMask, 292 int64_t &CmpValue) const override; 293 294 /// optimizeCompareInstr - Convert the instruction to set the zero flag so 295 /// that we can remove a "comparison with zero"; Remove a redundant CMP 296 /// instruction if the flags can be updated in the same way by an earlier 297 /// instruction such as SUB. 298 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, 299 Register SrcReg2, int64_t CmpMask, int64_t CmpValue, 300 const MachineRegisterInfo *MRI) const override; 301 302 bool analyzeSelect(const MachineInstr &MI, 303 SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp, 304 unsigned &FalseOp, bool &Optimizable) const override; 305 306 MachineInstr *optimizeSelect(MachineInstr &MI, 307 SmallPtrSetImpl<MachineInstr *> &SeenMIs, 308 bool) const override; 309 310 /// FoldImmediate - 'Reg' is known to be defined by a move immediate 311 /// instruction, try to fold the immediate into the use instruction. 312 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, 313 MachineRegisterInfo *MRI) const override; 314 315 unsigned getNumMicroOps(const InstrItineraryData *ItinData, 316 const MachineInstr &MI) const override; 317 318 int getOperandLatency(const InstrItineraryData *ItinData, 319 const MachineInstr &DefMI, unsigned DefIdx, 320 const MachineInstr &UseMI, 321 unsigned UseIdx) const override; 322 int getOperandLatency(const InstrItineraryData *ItinData, 323 SDNode *DefNode, unsigned DefIdx, 324 SDNode *UseNode, unsigned UseIdx) const override; 325 326 /// VFP/NEON execution domains. 327 std::pair<uint16_t, uint16_t> 328 getExecutionDomain(const MachineInstr &MI) const override; 329 void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override; 330 331 unsigned 332 getPartialRegUpdateClearance(const MachineInstr &, unsigned, 333 const TargetRegisterInfo *) const override; 334 void breakPartialRegDependency(MachineInstr &, unsigned, 335 const TargetRegisterInfo *TRI) const override; 336 337 /// Get the number of addresses by LDM or VLDM or zero for unknown. 338 unsigned getNumLDMAddresses(const MachineInstr &MI) const; 339 340 std::pair<unsigned, unsigned> 341 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 342 ArrayRef<std::pair<unsigned, const char *>> 343 getSerializableDirectMachineOperandTargetFlags() const override; 344 ArrayRef<std::pair<unsigned, const char *>> 345 getSerializableBitmaskMachineOperandTargetFlags() const override; 346 347 /// ARM supports the MachineOutliner. 348 bool isFunctionSafeToOutlineFrom(MachineFunction &MF, 349 bool OutlineFromLinkOnceODRs) const override; 350 outliner::OutlinedFunction getOutliningCandidateInfo( 351 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override; 352 void mergeOutliningCandidateAttributes( 353 Function &F, std::vector<outliner::Candidate> &Candidates) const override; 354 outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MIT, 355 unsigned Flags) const override; 356 bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, 357 unsigned &Flags) const override; 358 void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, 359 const outliner::OutlinedFunction &OF) const override; 360 MachineBasicBlock::iterator 361 insertOutlinedCall(Module &M, MachineBasicBlock &MBB, 362 MachineBasicBlock::iterator &It, MachineFunction &MF, 363 const outliner::Candidate &C) const override; 364 365 /// Enable outlining by default at -Oz. 366 bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override; 367 368 bool isUnspillableTerminatorImpl(const MachineInstr *MI) const override { 369 return MI->getOpcode() == ARM::t2LoopEndDec || 370 MI->getOpcode() == ARM::t2DoLoopStartTP || 371 MI->getOpcode() == ARM::t2WhileLoopStartLR || 372 MI->getOpcode() == ARM::t2WhileLoopStartTP; 373 } 374 375 private: 376 /// Returns an unused general-purpose register which can be used for 377 /// constructing an outlined call if one exists. Returns 0 otherwise. 378 unsigned findRegisterToSaveLRTo(const outliner::Candidate &C) const; 379 380 /// Adds an instruction which saves the link register on top of the stack into 381 /// the MachineBasicBlock \p MBB at position \p It. If \p Auth is true, 382 /// compute and store an authentication code alongiside the link register. 383 /// If \p CFI is true, emit CFI instructions. 384 void saveLROnStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator It, 385 bool CFI, bool Auth) const; 386 387 /// Adds an instruction which restores the link register from the top the 388 /// stack into the MachineBasicBlock \p MBB at position \p It. If \p Auth is 389 /// true, restore an authentication code and authenticate LR. 390 /// If \p CFI is true, emit CFI instructions. 391 void restoreLRFromStack(MachineBasicBlock &MBB, 392 MachineBasicBlock::iterator It, bool CFI, 393 bool Auth) const; 394 395 /// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It, 396 /// for the case when the LR is saved in the register \p Reg. 397 void emitCFIForLRSaveToReg(MachineBasicBlock &MBB, 398 MachineBasicBlock::iterator It, 399 Register Reg) const; 400 401 /// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It, 402 /// after the LR is was restored from a register. 403 void emitCFIForLRRestoreFromReg(MachineBasicBlock &MBB, 404 MachineBasicBlock::iterator It) const; 405 /// \brief Sets the offsets on outlined instructions in \p MBB which use SP 406 /// so that they will be valid post-outlining. 407 /// 408 /// \param MBB A \p MachineBasicBlock in an outlined function. 409 void fixupPostOutline(MachineBasicBlock &MBB) const; 410 411 /// Returns true if the machine instruction offset can handle the stack fixup 412 /// and updates it if requested. 413 bool checkAndUpdateStackOffset(MachineInstr *MI, int64_t Fixup, 414 bool Updt) const; 415 416 unsigned getInstBundleLength(const MachineInstr &MI) const; 417 418 int getVLDMDefCycle(const InstrItineraryData *ItinData, 419 const MCInstrDesc &DefMCID, 420 unsigned DefClass, 421 unsigned DefIdx, unsigned DefAlign) const; 422 int getLDMDefCycle(const InstrItineraryData *ItinData, 423 const MCInstrDesc &DefMCID, 424 unsigned DefClass, 425 unsigned DefIdx, unsigned DefAlign) const; 426 int getVSTMUseCycle(const InstrItineraryData *ItinData, 427 const MCInstrDesc &UseMCID, 428 unsigned UseClass, 429 unsigned UseIdx, unsigned UseAlign) const; 430 int getSTMUseCycle(const InstrItineraryData *ItinData, 431 const MCInstrDesc &UseMCID, 432 unsigned UseClass, 433 unsigned UseIdx, unsigned UseAlign) const; 434 int getOperandLatency(const InstrItineraryData *ItinData, 435 const MCInstrDesc &DefMCID, 436 unsigned DefIdx, unsigned DefAlign, 437 const MCInstrDesc &UseMCID, 438 unsigned UseIdx, unsigned UseAlign) const; 439 440 int getOperandLatencyImpl(const InstrItineraryData *ItinData, 441 const MachineInstr &DefMI, unsigned DefIdx, 442 const MCInstrDesc &DefMCID, unsigned DefAdj, 443 const MachineOperand &DefMO, unsigned Reg, 444 const MachineInstr &UseMI, unsigned UseIdx, 445 const MCInstrDesc &UseMCID, unsigned UseAdj) const; 446 447 unsigned getPredicationCost(const MachineInstr &MI) const override; 448 449 unsigned getInstrLatency(const InstrItineraryData *ItinData, 450 const MachineInstr &MI, 451 unsigned *PredCost = nullptr) const override; 452 453 int getInstrLatency(const InstrItineraryData *ItinData, 454 SDNode *Node) const override; 455 456 bool hasHighOperandLatency(const TargetSchedModel &SchedModel, 457 const MachineRegisterInfo *MRI, 458 const MachineInstr &DefMI, unsigned DefIdx, 459 const MachineInstr &UseMI, 460 unsigned UseIdx) const override; 461 bool hasLowDefLatency(const TargetSchedModel &SchedModel, 462 const MachineInstr &DefMI, 463 unsigned DefIdx) const override; 464 465 /// verifyInstruction - Perform target specific instruction verification. 466 bool verifyInstruction(const MachineInstr &MI, 467 StringRef &ErrInfo) const override; 468 469 virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI) const = 0; 470 471 void expandMEMCPY(MachineBasicBlock::iterator) const; 472 473 /// Identify instructions that can be folded into a MOVCC instruction, and 474 /// return the defining instruction. 475 MachineInstr *canFoldIntoMOVCC(Register Reg, const MachineRegisterInfo &MRI, 476 const TargetInstrInfo *TII) const; 477 478 bool isReallyTriviallyReMaterializable(const MachineInstr &MI, 479 AAResults *AA) const override; 480 481 private: 482 /// Modeling special VFP / NEON fp MLA / MLS hazards. 483 484 /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal 485 /// MLx table. 486 DenseMap<unsigned, unsigned> MLxEntryMap; 487 488 /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause 489 /// stalls when scheduled together with fp MLA / MLS opcodes. 490 SmallSet<unsigned, 16> MLxHazardOpcodes; 491 492 public: 493 /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS 494 /// instruction. 495 bool isFpMLxInstruction(unsigned Opcode) const { 496 return MLxEntryMap.count(Opcode); 497 } 498 499 /// isFpMLxInstruction - This version also returns the multiply opcode and the 500 /// addition / subtraction opcode to expand to. Return true for 'HasLane' for 501 /// the MLX instructions with an extra lane operand. 502 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, 503 unsigned &AddSubOpc, bool &NegAcc, 504 bool &HasLane) const; 505 506 /// canCauseFpMLxStall - Return true if an instruction of the specified opcode 507 /// will cause stalls when scheduled after (within 4-cycle window) a fp 508 /// MLA / MLS instruction. 509 bool canCauseFpMLxStall(unsigned Opcode) const { 510 return MLxHazardOpcodes.count(Opcode); 511 } 512 513 /// Returns true if the instruction has a shift by immediate that can be 514 /// executed in one cycle less. 515 bool isSwiftFastImmShift(const MachineInstr *MI) const; 516 517 /// Returns predicate register associated with the given frame instruction. 518 unsigned getFramePred(const MachineInstr &MI) const { 519 assert(isFrameInstr(MI)); 520 // Operands of ADJCALLSTACKDOWN/ADJCALLSTACKUP: 521 // - argument declared in the pattern: 522 // 0 - frame size 523 // 1 - arg of CALLSEQ_START/CALLSEQ_END 524 // 2 - predicate code (like ARMCC::AL) 525 // - added by predOps: 526 // 3 - predicate reg 527 return MI.getOperand(3).getReg(); 528 } 529 530 Optional<RegImmPair> isAddImmediate(const MachineInstr &MI, 531 Register Reg) const override; 532 }; 533 534 /// Get the operands corresponding to the given \p Pred value. By default, the 535 /// predicate register is assumed to be 0 (no register), but you can pass in a 536 /// \p PredReg if that is not the case. 537 static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred, 538 unsigned PredReg = 0) { 539 return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)), 540 MachineOperand::CreateReg(PredReg, false)}}; 541 } 542 543 /// Get the operand corresponding to the conditional code result. By default, 544 /// this is 0 (no register). 545 static inline MachineOperand condCodeOp(unsigned CCReg = 0) { 546 return MachineOperand::CreateReg(CCReg, false); 547 } 548 549 /// Get the operand corresponding to the conditional code result for Thumb1. 550 /// This operand will always refer to CPSR and it will have the Define flag set. 551 /// You can optionally set the Dead flag by means of \p isDead. 552 static inline MachineOperand t1CondCodeOp(bool isDead = false) { 553 return MachineOperand::CreateReg(ARM::CPSR, 554 /*Define*/ true, /*Implicit*/ false, 555 /*Kill*/ false, isDead); 556 } 557 558 static inline 559 bool isUncondBranchOpcode(int Opc) { 560 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; 561 } 562 563 // This table shows the VPT instruction variants, i.e. the different 564 // mask field encodings, see also B5.6. Predication/conditional execution in 565 // the ArmARM. 566 static inline bool isVPTOpcode(int Opc) { 567 return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 || 568 Opc == ARM::MVE_VPTv16s8 || Opc == ARM::MVE_VPTv8i16 || 569 Opc == ARM::MVE_VPTv8u16 || Opc == ARM::MVE_VPTv8s16 || 570 Opc == ARM::MVE_VPTv4i32 || Opc == ARM::MVE_VPTv4u32 || 571 Opc == ARM::MVE_VPTv4s32 || Opc == ARM::MVE_VPTv4f32 || 572 Opc == ARM::MVE_VPTv8f16 || Opc == ARM::MVE_VPTv16i8r || 573 Opc == ARM::MVE_VPTv16u8r || Opc == ARM::MVE_VPTv16s8r || 574 Opc == ARM::MVE_VPTv8i16r || Opc == ARM::MVE_VPTv8u16r || 575 Opc == ARM::MVE_VPTv8s16r || Opc == ARM::MVE_VPTv4i32r || 576 Opc == ARM::MVE_VPTv4u32r || Opc == ARM::MVE_VPTv4s32r || 577 Opc == ARM::MVE_VPTv4f32r || Opc == ARM::MVE_VPTv8f16r || 578 Opc == ARM::MVE_VPST; 579 } 580 581 static inline 582 unsigned VCMPOpcodeToVPT(unsigned Opcode) { 583 switch (Opcode) { 584 default: 585 return 0; 586 case ARM::MVE_VCMPf32: 587 return ARM::MVE_VPTv4f32; 588 case ARM::MVE_VCMPf16: 589 return ARM::MVE_VPTv8f16; 590 case ARM::MVE_VCMPi8: 591 return ARM::MVE_VPTv16i8; 592 case ARM::MVE_VCMPi16: 593 return ARM::MVE_VPTv8i16; 594 case ARM::MVE_VCMPi32: 595 return ARM::MVE_VPTv4i32; 596 case ARM::MVE_VCMPu8: 597 return ARM::MVE_VPTv16u8; 598 case ARM::MVE_VCMPu16: 599 return ARM::MVE_VPTv8u16; 600 case ARM::MVE_VCMPu32: 601 return ARM::MVE_VPTv4u32; 602 case ARM::MVE_VCMPs8: 603 return ARM::MVE_VPTv16s8; 604 case ARM::MVE_VCMPs16: 605 return ARM::MVE_VPTv8s16; 606 case ARM::MVE_VCMPs32: 607 return ARM::MVE_VPTv4s32; 608 609 case ARM::MVE_VCMPf32r: 610 return ARM::MVE_VPTv4f32r; 611 case ARM::MVE_VCMPf16r: 612 return ARM::MVE_VPTv8f16r; 613 case ARM::MVE_VCMPi8r: 614 return ARM::MVE_VPTv16i8r; 615 case ARM::MVE_VCMPi16r: 616 return ARM::MVE_VPTv8i16r; 617 case ARM::MVE_VCMPi32r: 618 return ARM::MVE_VPTv4i32r; 619 case ARM::MVE_VCMPu8r: 620 return ARM::MVE_VPTv16u8r; 621 case ARM::MVE_VCMPu16r: 622 return ARM::MVE_VPTv8u16r; 623 case ARM::MVE_VCMPu32r: 624 return ARM::MVE_VPTv4u32r; 625 case ARM::MVE_VCMPs8r: 626 return ARM::MVE_VPTv16s8r; 627 case ARM::MVE_VCMPs16r: 628 return ARM::MVE_VPTv8s16r; 629 case ARM::MVE_VCMPs32r: 630 return ARM::MVE_VPTv4s32r; 631 } 632 } 633 634 static inline 635 bool isCondBranchOpcode(int Opc) { 636 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc; 637 } 638 639 static inline bool isJumpTableBranchOpcode(int Opc) { 640 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm_i12 || 641 Opc == ARM::BR_JTm_rs || Opc == ARM::BR_JTadd || Opc == ARM::tBR_JTr || 642 Opc == ARM::t2BR_JT; 643 } 644 645 static inline 646 bool isIndirectBranchOpcode(int Opc) { 647 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND; 648 } 649 650 static inline bool isIndirectCall(const MachineInstr &MI) { 651 int Opc = MI.getOpcode(); 652 switch (Opc) { 653 // indirect calls: 654 case ARM::BLX: 655 case ARM::BLX_noip: 656 case ARM::BLX_pred: 657 case ARM::BLX_pred_noip: 658 case ARM::BX_CALL: 659 case ARM::BMOVPCRX_CALL: 660 case ARM::TCRETURNri: 661 case ARM::TAILJMPr: 662 case ARM::TAILJMPr4: 663 case ARM::tBLXr: 664 case ARM::tBLXr_noip: 665 case ARM::tBLXNSr: 666 case ARM::tBLXNS_CALL: 667 case ARM::tBX_CALL: 668 case ARM::tTAILJMPr: 669 assert(MI.isCall(MachineInstr::IgnoreBundle)); 670 return true; 671 // direct calls: 672 case ARM::BL: 673 case ARM::BL_pred: 674 case ARM::BMOVPCB_CALL: 675 case ARM::BL_PUSHLR: 676 case ARM::BLXi: 677 case ARM::TCRETURNdi: 678 case ARM::TAILJMPd: 679 case ARM::SVC: 680 case ARM::HVC: 681 case ARM::TPsoft: 682 case ARM::tTAILJMPd: 683 case ARM::t2SMC: 684 case ARM::t2HVC: 685 case ARM::tBL: 686 case ARM::tBLXi: 687 case ARM::tBL_PUSHLR: 688 case ARM::tTAILJMPdND: 689 case ARM::tSVC: 690 case ARM::tTPsoft: 691 assert(MI.isCall(MachineInstr::IgnoreBundle)); 692 return false; 693 } 694 assert(!MI.isCall(MachineInstr::IgnoreBundle)); 695 return false; 696 } 697 698 static inline bool isIndirectControlFlowNotComingBack(const MachineInstr &MI) { 699 int opc = MI.getOpcode(); 700 return MI.isReturn() || isIndirectBranchOpcode(MI.getOpcode()) || 701 isJumpTableBranchOpcode(opc); 702 } 703 704 static inline bool isSpeculationBarrierEndBBOpcode(int Opc) { 705 return Opc == ARM::SpeculationBarrierISBDSBEndBB || 706 Opc == ARM::SpeculationBarrierSBEndBB || 707 Opc == ARM::t2SpeculationBarrierISBDSBEndBB || 708 Opc == ARM::t2SpeculationBarrierSBEndBB; 709 } 710 711 static inline bool isPopOpcode(int Opc) { 712 return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET || 713 Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD || 714 Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD; 715 } 716 717 static inline bool isPushOpcode(int Opc) { 718 return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD || 719 Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD; 720 } 721 722 static inline bool isSubImmOpcode(int Opc) { 723 return Opc == ARM::SUBri || 724 Opc == ARM::tSUBi3 || Opc == ARM::tSUBi8 || 725 Opc == ARM::tSUBSi3 || Opc == ARM::tSUBSi8 || 726 Opc == ARM::t2SUBri || Opc == ARM::t2SUBri12 || Opc == ARM::t2SUBSri; 727 } 728 729 static inline bool isMovRegOpcode(int Opc) { 730 return Opc == ARM::MOVr || Opc == ARM::tMOVr || Opc == ARM::t2MOVr; 731 } 732 /// isValidCoprocessorNumber - decide whether an explicit coprocessor 733 /// number is legal in generic instructions like CDP. The answer can 734 /// vary with the subtarget. 735 static inline bool isValidCoprocessorNumber(unsigned Num, 736 const FeatureBitset& featureBits) { 737 // In Armv7 and Armv8-M CP10 and CP11 clash with VFP/NEON, however, the 738 // coprocessor is still valid for CDP/MCR/MRC and friends. Allowing it is 739 // useful for code which is shared with older architectures which do not know 740 // the new VFP/NEON mnemonics. 741 742 // Armv8-A disallows everything *other* than 111x (CP14 and CP15). 743 if (featureBits[ARM::HasV8Ops] && (Num & 0xE) != 0xE) 744 return false; 745 746 // Armv8.1-M disallows 100x (CP8,CP9) and 111x (CP14,CP15) 747 // which clash with MVE. 748 if (featureBits[ARM::HasV8_1MMainlineOps] && 749 ((Num & 0xE) == 0x8 || (Num & 0xE) == 0xE)) 750 return false; 751 752 return true; 753 } 754 755 /// getInstrPredicate - If instruction is predicated, returns its predicate 756 /// condition, otherwise returns AL. It also returns the condition code 757 /// register by reference. 758 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg); 759 760 unsigned getMatchingCondBranchOpcode(unsigned Opc); 761 762 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether 763 /// the instruction is encoded with an 'S' bit is determined by the optional 764 /// CPSR def operand. 765 unsigned convertAddSubFlagsOpcode(unsigned OldOpc); 766 767 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of 768 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2 769 /// code. 770 void emitARMRegPlusImmediate(MachineBasicBlock &MBB, 771 MachineBasicBlock::iterator &MBBI, 772 const DebugLoc &dl, Register DestReg, 773 Register BaseReg, int NumBytes, 774 ARMCC::CondCodes Pred, Register PredReg, 775 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0); 776 777 void emitT2RegPlusImmediate(MachineBasicBlock &MBB, 778 MachineBasicBlock::iterator &MBBI, 779 const DebugLoc &dl, Register DestReg, 780 Register BaseReg, int NumBytes, 781 ARMCC::CondCodes Pred, Register PredReg, 782 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0); 783 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, 784 MachineBasicBlock::iterator &MBBI, 785 const DebugLoc &dl, Register DestReg, 786 Register BaseReg, int NumBytes, 787 const TargetInstrInfo &TII, 788 const ARMBaseRegisterInfo &MRI, 789 unsigned MIFlags = 0); 790 791 /// Tries to add registers to the reglist of a given base-updating 792 /// push/pop instruction to adjust the stack by an additional 793 /// NumBytes. This can save a few bytes per function in code-size, but 794 /// obviously generates more memory traffic. As such, it only takes 795 /// effect in functions being optimised for size. 796 bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, 797 MachineFunction &MF, MachineInstr *MI, 798 unsigned NumBytes); 799 800 /// rewriteARMFrameIndex / rewriteT2FrameIndex - 801 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the 802 /// offset could not be handled directly in MI, and return the left-over 803 /// portion by reference. 804 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 805 Register FrameReg, int &Offset, 806 const ARMBaseInstrInfo &TII); 807 808 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 809 Register FrameReg, int &Offset, 810 const ARMBaseInstrInfo &TII, 811 const TargetRegisterInfo *TRI); 812 813 /// Return true if Reg is defd between From and To 814 bool registerDefinedBetween(unsigned Reg, MachineBasicBlock::iterator From, 815 MachineBasicBlock::iterator To, 816 const TargetRegisterInfo *TRI); 817 818 /// Search backwards from a tBcc to find a tCMPi8 against 0, meaning 819 /// we can convert them to a tCBZ or tCBNZ. Return nullptr if not found. 820 MachineInstr *findCMPToFoldIntoCBZ(MachineInstr *Br, 821 const TargetRegisterInfo *TRI); 822 823 void addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB); 824 void addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, Register DestReg); 825 826 void addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond); 827 void addPredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned Cond, 828 unsigned Inactive); 829 830 /// Returns the number of instructions required to materialize the given 831 /// constant in a register, or 3 if a literal pool load is needed. 832 /// If ForCodesize is specified, an approximate cost in bytes is returned. 833 unsigned ConstantMaterializationCost(unsigned Val, 834 const ARMSubtarget *Subtarget, 835 bool ForCodesize = false); 836 837 /// Returns true if Val1 has a lower Constant Materialization Cost than Val2. 838 /// Uses the cost from ConstantMaterializationCost, first with ForCodesize as 839 /// specified. If the scores are equal, return the comparison for !ForCodesize. 840 bool HasLowerConstantMaterializationCost(unsigned Val1, unsigned Val2, 841 const ARMSubtarget *Subtarget, 842 bool ForCodesize = false); 843 844 // Return the immediate if this is ADDri or SUBri, scaled as appropriate. 845 // Returns 0 for unknown instructions. 846 inline int getAddSubImmediate(MachineInstr &MI) { 847 int Scale = 1; 848 unsigned ImmOp; 849 switch (MI.getOpcode()) { 850 case ARM::t2ADDri: 851 ImmOp = 2; 852 break; 853 case ARM::t2SUBri: 854 case ARM::t2SUBri12: 855 ImmOp = 2; 856 Scale = -1; 857 break; 858 case ARM::tSUBi3: 859 case ARM::tSUBi8: 860 ImmOp = 3; 861 Scale = -1; 862 break; 863 default: 864 return 0; 865 } 866 return Scale * MI.getOperand(ImmOp).getImm(); 867 } 868 869 // Given a memory access Opcode, check that the give Imm would be a valid Offset 870 // for this instruction using its addressing mode. 871 inline bool isLegalAddressImm(unsigned Opcode, int Imm, 872 const TargetInstrInfo *TII) { 873 const MCInstrDesc &Desc = TII->get(Opcode); 874 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 875 switch (AddrMode) { 876 case ARMII::AddrModeT2_i7: 877 return std::abs(Imm) < ((1 << 7) * 1); 878 case ARMII::AddrModeT2_i7s2: 879 return std::abs(Imm) < ((1 << 7) * 2) && Imm % 2 == 0; 880 case ARMII::AddrModeT2_i7s4: 881 return std::abs(Imm) < ((1 << 7) * 4) && Imm % 4 == 0; 882 case ARMII::AddrModeT2_i8: 883 return std::abs(Imm) < ((1 << 8) * 1); 884 case ARMII::AddrModeT2_i8pos: 885 return Imm >= 0 && Imm < ((1 << 8) * 1); 886 case ARMII::AddrModeT2_i8neg: 887 return Imm < 0 && -Imm < ((1 << 8) * 1); 888 case ARMII::AddrModeT2_i8s4: 889 return std::abs(Imm) < ((1 << 8) * 4) && Imm % 4 == 0; 890 case ARMII::AddrModeT2_i12: 891 return Imm >= 0 && Imm < ((1 << 12) * 1); 892 case ARMII::AddrMode2: 893 return std::abs(Imm) < ((1 << 12) * 1); 894 default: 895 llvm_unreachable("Unhandled Addressing mode"); 896 } 897 } 898 899 // Return true if the given intrinsic is a gather 900 inline bool isGather(IntrinsicInst *IntInst) { 901 if (IntInst == nullptr) 902 return false; 903 unsigned IntrinsicID = IntInst->getIntrinsicID(); 904 return (IntrinsicID == Intrinsic::masked_gather || 905 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base || 906 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_predicated || 907 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb || 908 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb_predicated || 909 IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset || 910 IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset_predicated); 911 } 912 913 // Return true if the given intrinsic is a scatter 914 inline bool isScatter(IntrinsicInst *IntInst) { 915 if (IntInst == nullptr) 916 return false; 917 unsigned IntrinsicID = IntInst->getIntrinsicID(); 918 return (IntrinsicID == Intrinsic::masked_scatter || 919 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base || 920 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_predicated || 921 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb || 922 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb_predicated || 923 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset || 924 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset_predicated); 925 } 926 927 // Return true if the given intrinsic is a gather or scatter 928 inline bool isGatherScatter(IntrinsicInst *IntInst) { 929 if (IntInst == nullptr) 930 return false; 931 return isGather(IntInst) || isScatter(IntInst); 932 } 933 934 unsigned getBLXOpcode(const MachineFunction &MF); 935 unsigned gettBLXrOpcode(const MachineFunction &MF); 936 unsigned getBLXpredOpcode(const MachineFunction &MF); 937 938 } // end namespace llvm 939 940 #endif // LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H 941