1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains a pass that expands pseudo instructions into target 10 // instructions to allow proper scheduling, if-conversion, and other late 11 // optimizations. This pass should be run after register allocation but before 12 // the post-regalloc scheduling pass. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "ARM.h" 17 #include "ARMBaseInstrInfo.h" 18 #include "ARMBaseRegisterInfo.h" 19 #include "ARMConstantPoolValue.h" 20 #include "ARMMachineFunctionInfo.h" 21 #include "ARMSubtarget.h" 22 #include "MCTargetDesc/ARMAddressingModes.h" 23 #include "llvm/CodeGen/LivePhysRegs.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineFunctionPass.h" 26 #include "llvm/MC/MCAsmInfo.h" 27 #include "llvm/Support/Debug.h" 28 29 using namespace llvm; 30 31 #define DEBUG_TYPE "arm-pseudo" 32 33 static cl::opt<bool> 34 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden, 35 cl::desc("Verify machine code after expanding ARM pseudos")); 36 37 #define ARM_EXPAND_PSEUDO_NAME "ARM pseudo instruction expansion pass" 38 39 namespace { 40 class ARMExpandPseudo : public MachineFunctionPass { 41 public: 42 static char ID; 43 ARMExpandPseudo() : MachineFunctionPass(ID) {} 44 45 const ARMBaseInstrInfo *TII; 46 const TargetRegisterInfo *TRI; 47 const ARMSubtarget *STI; 48 ARMFunctionInfo *AFI; 49 50 bool runOnMachineFunction(MachineFunction &Fn) override; 51 52 MachineFunctionProperties getRequiredProperties() const override { 53 return MachineFunctionProperties().set( 54 MachineFunctionProperties::Property::NoVRegs); 55 } 56 57 StringRef getPassName() const override { 58 return ARM_EXPAND_PSEUDO_NAME; 59 } 60 61 private: 62 void TransferImpOps(MachineInstr &OldMI, 63 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI); 64 bool ExpandMI(MachineBasicBlock &MBB, 65 MachineBasicBlock::iterator MBBI, 66 MachineBasicBlock::iterator &NextMBBI); 67 bool ExpandMBB(MachineBasicBlock &MBB); 68 void ExpandVLD(MachineBasicBlock::iterator &MBBI); 69 void ExpandVST(MachineBasicBlock::iterator &MBBI); 70 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI); 71 void ExpandVTBL(MachineBasicBlock::iterator &MBBI, 72 unsigned Opc, bool IsExt); 73 void ExpandMQQPRLoadStore(MachineBasicBlock::iterator &MBBI); 74 void ExpandMOV32BitImm(MachineBasicBlock &MBB, 75 MachineBasicBlock::iterator &MBBI); 76 void CMSEClearGPRegs(MachineBasicBlock &MBB, 77 MachineBasicBlock::iterator MBBI, const DebugLoc &DL, 78 const SmallVectorImpl<unsigned> &ClearRegs, 79 unsigned ClobberReg); 80 MachineBasicBlock &CMSEClearFPRegs(MachineBasicBlock &MBB, 81 MachineBasicBlock::iterator MBBI); 82 MachineBasicBlock &CMSEClearFPRegsV8(MachineBasicBlock &MBB, 83 MachineBasicBlock::iterator MBBI, 84 const BitVector &ClearRegs); 85 MachineBasicBlock &CMSEClearFPRegsV81(MachineBasicBlock &MBB, 86 MachineBasicBlock::iterator MBBI, 87 const BitVector &ClearRegs); 88 void CMSESaveClearFPRegs(MachineBasicBlock &MBB, 89 MachineBasicBlock::iterator MBBI, DebugLoc &DL, 90 const LivePhysRegs &LiveRegs, 91 SmallVectorImpl<unsigned> &AvailableRegs); 92 void CMSESaveClearFPRegsV8(MachineBasicBlock &MBB, 93 MachineBasicBlock::iterator MBBI, DebugLoc &DL, 94 const LivePhysRegs &LiveRegs, 95 SmallVectorImpl<unsigned> &ScratchRegs); 96 void CMSESaveClearFPRegsV81(MachineBasicBlock &MBB, 97 MachineBasicBlock::iterator MBBI, DebugLoc &DL, 98 const LivePhysRegs &LiveRegs); 99 void CMSERestoreFPRegs(MachineBasicBlock &MBB, 100 MachineBasicBlock::iterator MBBI, DebugLoc &DL, 101 SmallVectorImpl<unsigned> &AvailableRegs); 102 void CMSERestoreFPRegsV8(MachineBasicBlock &MBB, 103 MachineBasicBlock::iterator MBBI, DebugLoc &DL, 104 SmallVectorImpl<unsigned> &AvailableRegs); 105 void CMSERestoreFPRegsV81(MachineBasicBlock &MBB, 106 MachineBasicBlock::iterator MBBI, DebugLoc &DL, 107 SmallVectorImpl<unsigned> &AvailableRegs); 108 bool ExpandCMP_SWAP(MachineBasicBlock &MBB, 109 MachineBasicBlock::iterator MBBI, unsigned LdrexOp, 110 unsigned StrexOp, unsigned UxtOp, 111 MachineBasicBlock::iterator &NextMBBI); 112 113 bool ExpandCMP_SWAP_64(MachineBasicBlock &MBB, 114 MachineBasicBlock::iterator MBBI, 115 MachineBasicBlock::iterator &NextMBBI); 116 }; 117 char ARMExpandPseudo::ID = 0; 118 } 119 120 INITIALIZE_PASS(ARMExpandPseudo, DEBUG_TYPE, ARM_EXPAND_PSEUDO_NAME, false, 121 false) 122 123 /// TransferImpOps - Transfer implicit operands on the pseudo instruction to 124 /// the instructions created from the expansion. 125 void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI, 126 MachineInstrBuilder &UseMI, 127 MachineInstrBuilder &DefMI) { 128 const MCInstrDesc &Desc = OldMI.getDesc(); 129 for (const MachineOperand &MO : 130 llvm::drop_begin(OldMI.operands(), Desc.getNumOperands())) { 131 assert(MO.isReg() && MO.getReg()); 132 if (MO.isUse()) 133 UseMI.add(MO); 134 else 135 DefMI.add(MO); 136 } 137 } 138 139 namespace { 140 // Constants for register spacing in NEON load/store instructions. 141 // For quad-register load-lane and store-lane pseudo instructors, the 142 // spacing is initially assumed to be EvenDblSpc, and that is changed to 143 // OddDblSpc depending on the lane number operand. 144 enum NEONRegSpacing { 145 SingleSpc, 146 SingleLowSpc , // Single spacing, low registers, three and four vectors. 147 SingleHighQSpc, // Single spacing, high registers, four vectors. 148 SingleHighTSpc, // Single spacing, high registers, three vectors. 149 EvenDblSpc, 150 OddDblSpc 151 }; 152 153 // Entries for NEON load/store information table. The table is sorted by 154 // PseudoOpc for fast binary-search lookups. 155 struct NEONLdStTableEntry { 156 uint16_t PseudoOpc; 157 uint16_t RealOpc; 158 bool IsLoad; 159 bool isUpdating; 160 bool hasWritebackOperand; 161 uint8_t RegSpacing; // One of type NEONRegSpacing 162 uint8_t NumRegs; // D registers loaded or stored 163 uint8_t RegElts; // elements per D register; used for lane ops 164 // FIXME: Temporary flag to denote whether the real instruction takes 165 // a single register (like the encoding) or all of the registers in 166 // the list (like the asm syntax and the isel DAG). When all definitions 167 // are converted to take only the single encoded register, this will 168 // go away. 169 bool copyAllListRegs; 170 171 // Comparison methods for binary search of the table. 172 bool operator<(const NEONLdStTableEntry &TE) const { 173 return PseudoOpc < TE.PseudoOpc; 174 } 175 friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) { 176 return TE.PseudoOpc < PseudoOpc; 177 } 178 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc, 179 const NEONLdStTableEntry &TE) { 180 return PseudoOpc < TE.PseudoOpc; 181 } 182 }; 183 } 184 185 static const NEONLdStTableEntry NEONLdStTable[] = { 186 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true}, 187 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true}, 188 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true}, 189 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true}, 190 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true}, 191 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true}, 192 193 { ARM::VLD1d16QPseudo, ARM::VLD1d16Q, true, false, false, SingleSpc, 4, 4 ,false}, 194 { ARM::VLD1d16QPseudoWB_fixed, ARM::VLD1d16Qwb_fixed, true, true, false, SingleSpc, 4, 4 ,false}, 195 { ARM::VLD1d16QPseudoWB_register, ARM::VLD1d16Qwb_register, true, true, true, SingleSpc, 4, 4 ,false}, 196 { ARM::VLD1d16TPseudo, ARM::VLD1d16T, true, false, false, SingleSpc, 3, 4 ,false}, 197 { ARM::VLD1d16TPseudoWB_fixed, ARM::VLD1d16Twb_fixed, true, true, false, SingleSpc, 3, 4 ,false}, 198 { ARM::VLD1d16TPseudoWB_register, ARM::VLD1d16Twb_register, true, true, true, SingleSpc, 3, 4 ,false}, 199 200 { ARM::VLD1d32QPseudo, ARM::VLD1d32Q, true, false, false, SingleSpc, 4, 2 ,false}, 201 { ARM::VLD1d32QPseudoWB_fixed, ARM::VLD1d32Qwb_fixed, true, true, false, SingleSpc, 4, 2 ,false}, 202 { ARM::VLD1d32QPseudoWB_register, ARM::VLD1d32Qwb_register, true, true, true, SingleSpc, 4, 2 ,false}, 203 { ARM::VLD1d32TPseudo, ARM::VLD1d32T, true, false, false, SingleSpc, 3, 2 ,false}, 204 { ARM::VLD1d32TPseudoWB_fixed, ARM::VLD1d32Twb_fixed, true, true, false, SingleSpc, 3, 2 ,false}, 205 { ARM::VLD1d32TPseudoWB_register, ARM::VLD1d32Twb_register, true, true, true, SingleSpc, 3, 2 ,false}, 206 207 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false}, 208 { ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,false}, 209 { ARM::VLD1d64QPseudoWB_register, ARM::VLD1d64Qwb_register, true, true, true, SingleSpc, 4, 1 ,false}, 210 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false}, 211 { ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,false}, 212 { ARM::VLD1d64TPseudoWB_register, ARM::VLD1d64Twb_register, true, true, true, SingleSpc, 3, 1 ,false}, 213 214 { ARM::VLD1d8QPseudo, ARM::VLD1d8Q, true, false, false, SingleSpc, 4, 8 ,false}, 215 { ARM::VLD1d8QPseudoWB_fixed, ARM::VLD1d8Qwb_fixed, true, true, false, SingleSpc, 4, 8 ,false}, 216 { ARM::VLD1d8QPseudoWB_register, ARM::VLD1d8Qwb_register, true, true, true, SingleSpc, 4, 8 ,false}, 217 { ARM::VLD1d8TPseudo, ARM::VLD1d8T, true, false, false, SingleSpc, 3, 8 ,false}, 218 { ARM::VLD1d8TPseudoWB_fixed, ARM::VLD1d8Twb_fixed, true, true, false, SingleSpc, 3, 8 ,false}, 219 { ARM::VLD1d8TPseudoWB_register, ARM::VLD1d8Twb_register, true, true, true, SingleSpc, 3, 8 ,false}, 220 221 { ARM::VLD1q16HighQPseudo, ARM::VLD1d16Q, true, false, false, SingleHighQSpc, 4, 4 ,false}, 222 { ARM::VLD1q16HighQPseudo_UPD, ARM::VLD1d16Qwb_fixed, true, true, true, SingleHighQSpc, 4, 4 ,false}, 223 { ARM::VLD1q16HighTPseudo, ARM::VLD1d16T, true, false, false, SingleHighTSpc, 3, 4 ,false}, 224 { ARM::VLD1q16HighTPseudo_UPD, ARM::VLD1d16Twb_fixed, true, true, true, SingleHighTSpc, 3, 4 ,false}, 225 { ARM::VLD1q16LowQPseudo_UPD, ARM::VLD1d16Qwb_fixed, true, true, true, SingleLowSpc, 4, 4 ,false}, 226 { ARM::VLD1q16LowTPseudo_UPD, ARM::VLD1d16Twb_fixed, true, true, true, SingleLowSpc, 3, 4 ,false}, 227 228 { ARM::VLD1q32HighQPseudo, ARM::VLD1d32Q, true, false, false, SingleHighQSpc, 4, 2 ,false}, 229 { ARM::VLD1q32HighQPseudo_UPD, ARM::VLD1d32Qwb_fixed, true, true, true, SingleHighQSpc, 4, 2 ,false}, 230 { ARM::VLD1q32HighTPseudo, ARM::VLD1d32T, true, false, false, SingleHighTSpc, 3, 2 ,false}, 231 { ARM::VLD1q32HighTPseudo_UPD, ARM::VLD1d32Twb_fixed, true, true, true, SingleHighTSpc, 3, 2 ,false}, 232 { ARM::VLD1q32LowQPseudo_UPD, ARM::VLD1d32Qwb_fixed, true, true, true, SingleLowSpc, 4, 2 ,false}, 233 { ARM::VLD1q32LowTPseudo_UPD, ARM::VLD1d32Twb_fixed, true, true, true, SingleLowSpc, 3, 2 ,false}, 234 235 { ARM::VLD1q64HighQPseudo, ARM::VLD1d64Q, true, false, false, SingleHighQSpc, 4, 1 ,false}, 236 { ARM::VLD1q64HighQPseudo_UPD, ARM::VLD1d64Qwb_fixed, true, true, true, SingleHighQSpc, 4, 1 ,false}, 237 { ARM::VLD1q64HighTPseudo, ARM::VLD1d64T, true, false, false, SingleHighTSpc, 3, 1 ,false}, 238 { ARM::VLD1q64HighTPseudo_UPD, ARM::VLD1d64Twb_fixed, true, true, true, SingleHighTSpc, 3, 1 ,false}, 239 { ARM::VLD1q64LowQPseudo_UPD, ARM::VLD1d64Qwb_fixed, true, true, true, SingleLowSpc, 4, 1 ,false}, 240 { ARM::VLD1q64LowTPseudo_UPD, ARM::VLD1d64Twb_fixed, true, true, true, SingleLowSpc, 3, 1 ,false}, 241 242 { ARM::VLD1q8HighQPseudo, ARM::VLD1d8Q, true, false, false, SingleHighQSpc, 4, 8 ,false}, 243 { ARM::VLD1q8HighQPseudo_UPD, ARM::VLD1d8Qwb_fixed, true, true, true, SingleHighQSpc, 4, 8 ,false}, 244 { ARM::VLD1q8HighTPseudo, ARM::VLD1d8T, true, false, false, SingleHighTSpc, 3, 8 ,false}, 245 { ARM::VLD1q8HighTPseudo_UPD, ARM::VLD1d8Twb_fixed, true, true, true, SingleHighTSpc, 3, 8 ,false}, 246 { ARM::VLD1q8LowQPseudo_UPD, ARM::VLD1d8Qwb_fixed, true, true, true, SingleLowSpc, 4, 8 ,false}, 247 { ARM::VLD1q8LowTPseudo_UPD, ARM::VLD1d8Twb_fixed, true, true, true, SingleLowSpc, 3, 8 ,false}, 248 249 { ARM::VLD2DUPq16EvenPseudo, ARM::VLD2DUPd16x2, true, false, false, EvenDblSpc, 2, 4 ,false}, 250 { ARM::VLD2DUPq16OddPseudo, ARM::VLD2DUPd16x2, true, false, false, OddDblSpc, 2, 4 ,false}, 251 { ARM::VLD2DUPq16OddPseudoWB_fixed, ARM::VLD2DUPd16x2wb_fixed, true, true, false, OddDblSpc, 2, 4 ,false}, 252 { ARM::VLD2DUPq16OddPseudoWB_register, ARM::VLD2DUPd16x2wb_register, true, true, true, OddDblSpc, 2, 4 ,false}, 253 { ARM::VLD2DUPq32EvenPseudo, ARM::VLD2DUPd32x2, true, false, false, EvenDblSpc, 2, 2 ,false}, 254 { ARM::VLD2DUPq32OddPseudo, ARM::VLD2DUPd32x2, true, false, false, OddDblSpc, 2, 2 ,false}, 255 { ARM::VLD2DUPq32OddPseudoWB_fixed, ARM::VLD2DUPd32x2wb_fixed, true, true, false, OddDblSpc, 2, 2 ,false}, 256 { ARM::VLD2DUPq32OddPseudoWB_register, ARM::VLD2DUPd32x2wb_register, true, true, true, OddDblSpc, 2, 2 ,false}, 257 { ARM::VLD2DUPq8EvenPseudo, ARM::VLD2DUPd8x2, true, false, false, EvenDblSpc, 2, 8 ,false}, 258 { ARM::VLD2DUPq8OddPseudo, ARM::VLD2DUPd8x2, true, false, false, OddDblSpc, 2, 8 ,false}, 259 { ARM::VLD2DUPq8OddPseudoWB_fixed, ARM::VLD2DUPd8x2wb_fixed, true, true, false, OddDblSpc, 2, 8 ,false}, 260 { ARM::VLD2DUPq8OddPseudoWB_register, ARM::VLD2DUPd8x2wb_register, true, true, true, OddDblSpc, 2, 8 ,false}, 261 262 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true}, 263 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true}, 264 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true}, 265 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true}, 266 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true}, 267 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true}, 268 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true}, 269 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true}, 270 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true}, 271 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true}, 272 273 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false}, 274 { ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false}, 275 { ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,false}, 276 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false}, 277 { ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false}, 278 { ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,false}, 279 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false}, 280 { ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false}, 281 { ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,false}, 282 283 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true}, 284 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true}, 285 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true}, 286 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true}, 287 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true}, 288 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true}, 289 { ARM::VLD3DUPq16EvenPseudo, ARM::VLD3DUPq16, true, false, false, EvenDblSpc, 3, 4 ,true}, 290 { ARM::VLD3DUPq16OddPseudo, ARM::VLD3DUPq16, true, false, false, OddDblSpc, 3, 4 ,true}, 291 { ARM::VLD3DUPq16OddPseudo_UPD, ARM::VLD3DUPq16_UPD, true, true, true, OddDblSpc, 3, 4 ,true}, 292 { ARM::VLD3DUPq32EvenPseudo, ARM::VLD3DUPq32, true, false, false, EvenDblSpc, 3, 2 ,true}, 293 { ARM::VLD3DUPq32OddPseudo, ARM::VLD3DUPq32, true, false, false, OddDblSpc, 3, 2 ,true}, 294 { ARM::VLD3DUPq32OddPseudo_UPD, ARM::VLD3DUPq32_UPD, true, true, true, OddDblSpc, 3, 2 ,true}, 295 { ARM::VLD3DUPq8EvenPseudo, ARM::VLD3DUPq8, true, false, false, EvenDblSpc, 3, 8 ,true}, 296 { ARM::VLD3DUPq8OddPseudo, ARM::VLD3DUPq8, true, false, false, OddDblSpc, 3, 8 ,true}, 297 { ARM::VLD3DUPq8OddPseudo_UPD, ARM::VLD3DUPq8_UPD, true, true, true, OddDblSpc, 3, 8 ,true}, 298 299 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true}, 300 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true}, 301 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true}, 302 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true}, 303 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true}, 304 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true}, 305 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true}, 306 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true}, 307 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true}, 308 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true}, 309 310 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true}, 311 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true}, 312 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true}, 313 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true}, 314 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true}, 315 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true}, 316 317 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true}, 318 { ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true}, 319 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true}, 320 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true}, 321 { ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true}, 322 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true}, 323 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true}, 324 { ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true}, 325 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true}, 326 327 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true}, 328 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true}, 329 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true}, 330 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true}, 331 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true}, 332 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true}, 333 { ARM::VLD4DUPq16EvenPseudo, ARM::VLD4DUPq16, true, false, false, EvenDblSpc, 4, 4 ,true}, 334 { ARM::VLD4DUPq16OddPseudo, ARM::VLD4DUPq16, true, false, false, OddDblSpc, 4, 4 ,true}, 335 { ARM::VLD4DUPq16OddPseudo_UPD, ARM::VLD4DUPq16_UPD, true, true, true, OddDblSpc, 4, 4 ,true}, 336 { ARM::VLD4DUPq32EvenPseudo, ARM::VLD4DUPq32, true, false, false, EvenDblSpc, 4, 2 ,true}, 337 { ARM::VLD4DUPq32OddPseudo, ARM::VLD4DUPq32, true, false, false, OddDblSpc, 4, 2 ,true}, 338 { ARM::VLD4DUPq32OddPseudo_UPD, ARM::VLD4DUPq32_UPD, true, true, true, OddDblSpc, 4, 2 ,true}, 339 { ARM::VLD4DUPq8EvenPseudo, ARM::VLD4DUPq8, true, false, false, EvenDblSpc, 4, 8 ,true}, 340 { ARM::VLD4DUPq8OddPseudo, ARM::VLD4DUPq8, true, false, false, OddDblSpc, 4, 8 ,true}, 341 { ARM::VLD4DUPq8OddPseudo_UPD, ARM::VLD4DUPq8_UPD, true, true, true, OddDblSpc, 4, 8 ,true}, 342 343 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true}, 344 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true}, 345 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true}, 346 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true}, 347 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true}, 348 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true}, 349 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true}, 350 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true}, 351 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true}, 352 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true}, 353 354 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true}, 355 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true}, 356 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true}, 357 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true}, 358 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true}, 359 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true}, 360 361 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true}, 362 { ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true}, 363 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true}, 364 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true}, 365 { ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true}, 366 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true}, 367 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true}, 368 { ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true}, 369 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true}, 370 371 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true}, 372 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true}, 373 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true}, 374 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true}, 375 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true}, 376 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true}, 377 378 { ARM::VST1d16QPseudo, ARM::VST1d16Q, false, false, false, SingleSpc, 4, 4 ,false}, 379 { ARM::VST1d16QPseudoWB_fixed, ARM::VST1d16Qwb_fixed, false, true, false, SingleSpc, 4, 4 ,false}, 380 { ARM::VST1d16QPseudoWB_register, ARM::VST1d16Qwb_register, false, true, true, SingleSpc, 4, 4 ,false}, 381 { ARM::VST1d16TPseudo, ARM::VST1d16T, false, false, false, SingleSpc, 3, 4 ,false}, 382 { ARM::VST1d16TPseudoWB_fixed, ARM::VST1d16Twb_fixed, false, true, false, SingleSpc, 3, 4 ,false}, 383 { ARM::VST1d16TPseudoWB_register, ARM::VST1d16Twb_register, false, true, true, SingleSpc, 3, 4 ,false}, 384 385 { ARM::VST1d32QPseudo, ARM::VST1d32Q, false, false, false, SingleSpc, 4, 2 ,false}, 386 { ARM::VST1d32QPseudoWB_fixed, ARM::VST1d32Qwb_fixed, false, true, false, SingleSpc, 4, 2 ,false}, 387 { ARM::VST1d32QPseudoWB_register, ARM::VST1d32Qwb_register, false, true, true, SingleSpc, 4, 2 ,false}, 388 { ARM::VST1d32TPseudo, ARM::VST1d32T, false, false, false, SingleSpc, 3, 2 ,false}, 389 { ARM::VST1d32TPseudoWB_fixed, ARM::VST1d32Twb_fixed, false, true, false, SingleSpc, 3, 2 ,false}, 390 { ARM::VST1d32TPseudoWB_register, ARM::VST1d32Twb_register, false, true, true, SingleSpc, 3, 2 ,false}, 391 392 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false}, 393 { ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false}, 394 { ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,false}, 395 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false}, 396 { ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false}, 397 { ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,false}, 398 399 { ARM::VST1d8QPseudo, ARM::VST1d8Q, false, false, false, SingleSpc, 4, 8 ,false}, 400 { ARM::VST1d8QPseudoWB_fixed, ARM::VST1d8Qwb_fixed, false, true, false, SingleSpc, 4, 8 ,false}, 401 { ARM::VST1d8QPseudoWB_register, ARM::VST1d8Qwb_register, false, true, true, SingleSpc, 4, 8 ,false}, 402 { ARM::VST1d8TPseudo, ARM::VST1d8T, false, false, false, SingleSpc, 3, 8 ,false}, 403 { ARM::VST1d8TPseudoWB_fixed, ARM::VST1d8Twb_fixed, false, true, false, SingleSpc, 3, 8 ,false}, 404 { ARM::VST1d8TPseudoWB_register, ARM::VST1d8Twb_register, false, true, true, SingleSpc, 3, 8 ,false}, 405 406 { ARM::VST1q16HighQPseudo, ARM::VST1d16Q, false, false, false, SingleHighQSpc, 4, 4 ,false}, 407 { ARM::VST1q16HighQPseudo_UPD, ARM::VST1d16Qwb_fixed, false, true, true, SingleHighQSpc, 4, 8 ,false}, 408 { ARM::VST1q16HighTPseudo, ARM::VST1d16T, false, false, false, SingleHighTSpc, 3, 4 ,false}, 409 { ARM::VST1q16HighTPseudo_UPD, ARM::VST1d16Twb_fixed, false, true, true, SingleHighTSpc, 3, 4 ,false}, 410 { ARM::VST1q16LowQPseudo_UPD, ARM::VST1d16Qwb_fixed, false, true, true, SingleLowSpc, 4, 4 ,false}, 411 { ARM::VST1q16LowTPseudo_UPD, ARM::VST1d16Twb_fixed, false, true, true, SingleLowSpc, 3, 4 ,false}, 412 413 { ARM::VST1q32HighQPseudo, ARM::VST1d32Q, false, false, false, SingleHighQSpc, 4, 2 ,false}, 414 { ARM::VST1q32HighQPseudo_UPD, ARM::VST1d32Qwb_fixed, false, true, true, SingleHighQSpc, 4, 8 ,false}, 415 { ARM::VST1q32HighTPseudo, ARM::VST1d32T, false, false, false, SingleHighTSpc, 3, 2 ,false}, 416 { ARM::VST1q32HighTPseudo_UPD, ARM::VST1d32Twb_fixed, false, true, true, SingleHighTSpc, 3, 2 ,false}, 417 { ARM::VST1q32LowQPseudo_UPD, ARM::VST1d32Qwb_fixed, false, true, true, SingleLowSpc, 4, 2 ,false}, 418 { ARM::VST1q32LowTPseudo_UPD, ARM::VST1d32Twb_fixed, false, true, true, SingleLowSpc, 3, 2 ,false}, 419 420 { ARM::VST1q64HighQPseudo, ARM::VST1d64Q, false, false, false, SingleHighQSpc, 4, 1 ,false}, 421 { ARM::VST1q64HighQPseudo_UPD, ARM::VST1d64Qwb_fixed, false, true, true, SingleHighQSpc, 4, 8 ,false}, 422 { ARM::VST1q64HighTPseudo, ARM::VST1d64T, false, false, false, SingleHighTSpc, 3, 1 ,false}, 423 { ARM::VST1q64HighTPseudo_UPD, ARM::VST1d64Twb_fixed, false, true, true, SingleHighTSpc, 3, 1 ,false}, 424 { ARM::VST1q64LowQPseudo_UPD, ARM::VST1d64Qwb_fixed, false, true, true, SingleLowSpc, 4, 1 ,false}, 425 { ARM::VST1q64LowTPseudo_UPD, ARM::VST1d64Twb_fixed, false, true, true, SingleLowSpc, 3, 1 ,false}, 426 427 { ARM::VST1q8HighQPseudo, ARM::VST1d8Q, false, false, false, SingleHighQSpc, 4, 8 ,false}, 428 { ARM::VST1q8HighQPseudo_UPD, ARM::VST1d8Qwb_fixed, false, true, true, SingleHighQSpc, 4, 8 ,false}, 429 { ARM::VST1q8HighTPseudo, ARM::VST1d8T, false, false, false, SingleHighTSpc, 3, 8 ,false}, 430 { ARM::VST1q8HighTPseudo_UPD, ARM::VST1d8Twb_fixed, false, true, true, SingleHighTSpc, 3, 8 ,false}, 431 { ARM::VST1q8LowQPseudo_UPD, ARM::VST1d8Qwb_fixed, false, true, true, SingleLowSpc, 4, 8 ,false}, 432 { ARM::VST1q8LowTPseudo_UPD, ARM::VST1d8Twb_fixed, false, true, true, SingleLowSpc, 3, 8 ,false}, 433 434 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true}, 435 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true}, 436 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true}, 437 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true}, 438 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true}, 439 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true}, 440 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true}, 441 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true}, 442 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true}, 443 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true}, 444 445 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false}, 446 { ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false}, 447 { ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,false}, 448 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false}, 449 { ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false}, 450 { ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,false}, 451 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false}, 452 { ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false}, 453 { ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,false}, 454 455 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true}, 456 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true}, 457 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true}, 458 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true}, 459 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true}, 460 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true}, 461 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true}, 462 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true}, 463 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true}, 464 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true}, 465 466 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true}, 467 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true}, 468 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true}, 469 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true}, 470 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true}, 471 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true}, 472 473 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true}, 474 { ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true}, 475 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true}, 476 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true}, 477 { ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true}, 478 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true}, 479 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true}, 480 { ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true}, 481 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true}, 482 483 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true}, 484 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true}, 485 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true}, 486 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true}, 487 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true}, 488 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true}, 489 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true}, 490 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true}, 491 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true}, 492 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true}, 493 494 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true}, 495 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true}, 496 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true}, 497 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true}, 498 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true}, 499 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true}, 500 501 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true}, 502 { ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true}, 503 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true}, 504 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true}, 505 { ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true}, 506 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true}, 507 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true}, 508 { ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true}, 509 { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true} 510 }; 511 512 /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON 513 /// load or store pseudo instruction. 514 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) { 515 #ifndef NDEBUG 516 // Make sure the table is sorted. 517 static std::atomic<bool> TableChecked(false); 518 if (!TableChecked.load(std::memory_order_relaxed)) { 519 assert(llvm::is_sorted(NEONLdStTable) && "NEONLdStTable is not sorted!"); 520 TableChecked.store(true, std::memory_order_relaxed); 521 } 522 #endif 523 524 auto I = llvm::lower_bound(NEONLdStTable, Opcode); 525 if (I != std::end(NEONLdStTable) && I->PseudoOpc == Opcode) 526 return I; 527 return nullptr; 528 } 529 530 /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register, 531 /// corresponding to the specified register spacing. Not all of the results 532 /// are necessarily valid, e.g., a Q register only has 2 D subregisters. 533 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, 534 const TargetRegisterInfo *TRI, unsigned &D0, 535 unsigned &D1, unsigned &D2, unsigned &D3) { 536 if (RegSpc == SingleSpc || RegSpc == SingleLowSpc) { 537 D0 = TRI->getSubReg(Reg, ARM::dsub_0); 538 D1 = TRI->getSubReg(Reg, ARM::dsub_1); 539 D2 = TRI->getSubReg(Reg, ARM::dsub_2); 540 D3 = TRI->getSubReg(Reg, ARM::dsub_3); 541 } else if (RegSpc == SingleHighQSpc) { 542 D0 = TRI->getSubReg(Reg, ARM::dsub_4); 543 D1 = TRI->getSubReg(Reg, ARM::dsub_5); 544 D2 = TRI->getSubReg(Reg, ARM::dsub_6); 545 D3 = TRI->getSubReg(Reg, ARM::dsub_7); 546 } else if (RegSpc == SingleHighTSpc) { 547 D0 = TRI->getSubReg(Reg, ARM::dsub_3); 548 D1 = TRI->getSubReg(Reg, ARM::dsub_4); 549 D2 = TRI->getSubReg(Reg, ARM::dsub_5); 550 D3 = TRI->getSubReg(Reg, ARM::dsub_6); 551 } else if (RegSpc == EvenDblSpc) { 552 D0 = TRI->getSubReg(Reg, ARM::dsub_0); 553 D1 = TRI->getSubReg(Reg, ARM::dsub_2); 554 D2 = TRI->getSubReg(Reg, ARM::dsub_4); 555 D3 = TRI->getSubReg(Reg, ARM::dsub_6); 556 } else { 557 assert(RegSpc == OddDblSpc && "unknown register spacing"); 558 D0 = TRI->getSubReg(Reg, ARM::dsub_1); 559 D1 = TRI->getSubReg(Reg, ARM::dsub_3); 560 D2 = TRI->getSubReg(Reg, ARM::dsub_5); 561 D3 = TRI->getSubReg(Reg, ARM::dsub_7); 562 } 563 } 564 565 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register 566 /// operands to real VLD instructions with D register operands. 567 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) { 568 MachineInstr &MI = *MBBI; 569 MachineBasicBlock &MBB = *MI.getParent(); 570 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump()); 571 572 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 573 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed"); 574 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; 575 unsigned NumRegs = TableEntry->NumRegs; 576 577 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 578 TII->get(TableEntry->RealOpc)); 579 unsigned OpIdx = 0; 580 581 bool DstIsDead = MI.getOperand(OpIdx).isDead(); 582 Register DstReg = MI.getOperand(OpIdx++).getReg(); 583 584 bool IsVLD2DUP = TableEntry->RealOpc == ARM::VLD2DUPd8x2 || 585 TableEntry->RealOpc == ARM::VLD2DUPd16x2 || 586 TableEntry->RealOpc == ARM::VLD2DUPd32x2 || 587 TableEntry->RealOpc == ARM::VLD2DUPd8x2wb_fixed || 588 TableEntry->RealOpc == ARM::VLD2DUPd16x2wb_fixed || 589 TableEntry->RealOpc == ARM::VLD2DUPd32x2wb_fixed || 590 TableEntry->RealOpc == ARM::VLD2DUPd8x2wb_register || 591 TableEntry->RealOpc == ARM::VLD2DUPd16x2wb_register || 592 TableEntry->RealOpc == ARM::VLD2DUPd32x2wb_register; 593 594 if (IsVLD2DUP) { 595 unsigned SubRegIndex; 596 if (RegSpc == EvenDblSpc) { 597 SubRegIndex = ARM::dsub_0; 598 } else { 599 assert(RegSpc == OddDblSpc && "Unexpected spacing!"); 600 SubRegIndex = ARM::dsub_1; 601 } 602 Register SubReg = TRI->getSubReg(DstReg, SubRegIndex); 603 unsigned DstRegPair = TRI->getMatchingSuperReg(SubReg, ARM::dsub_0, 604 &ARM::DPairSpcRegClass); 605 MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead)); 606 } else { 607 unsigned D0, D1, D2, D3; 608 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 609 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 610 if (NumRegs > 1 && TableEntry->copyAllListRegs) 611 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 612 if (NumRegs > 2 && TableEntry->copyAllListRegs) 613 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 614 if (NumRegs > 3 && TableEntry->copyAllListRegs) 615 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 616 } 617 618 if (TableEntry->isUpdating) 619 MIB.add(MI.getOperand(OpIdx++)); 620 621 // Copy the addrmode6 operands. 622 MIB.add(MI.getOperand(OpIdx++)); 623 MIB.add(MI.getOperand(OpIdx++)); 624 625 // Copy the am6offset operand. 626 if (TableEntry->hasWritebackOperand) { 627 // TODO: The writing-back pseudo instructions we translate here are all 628 // defined to take am6offset nodes that are capable to represent both fixed 629 // and register forms. Some real instructions, however, do not rely on 630 // am6offset and have separate definitions for such forms. When this is the 631 // case, fixed forms do not take any offset nodes, so here we skip them for 632 // such instructions. Once all real and pseudo writing-back instructions are 633 // rewritten without use of am6offset nodes, this code will go away. 634 const MachineOperand &AM6Offset = MI.getOperand(OpIdx++); 635 if (TableEntry->RealOpc == ARM::VLD1d8Qwb_fixed || 636 TableEntry->RealOpc == ARM::VLD1d16Qwb_fixed || 637 TableEntry->RealOpc == ARM::VLD1d32Qwb_fixed || 638 TableEntry->RealOpc == ARM::VLD1d64Qwb_fixed || 639 TableEntry->RealOpc == ARM::VLD1d8Twb_fixed || 640 TableEntry->RealOpc == ARM::VLD1d16Twb_fixed || 641 TableEntry->RealOpc == ARM::VLD1d32Twb_fixed || 642 TableEntry->RealOpc == ARM::VLD1d64Twb_fixed || 643 TableEntry->RealOpc == ARM::VLD2DUPd8x2wb_fixed || 644 TableEntry->RealOpc == ARM::VLD2DUPd16x2wb_fixed || 645 TableEntry->RealOpc == ARM::VLD2DUPd32x2wb_fixed) { 646 assert(AM6Offset.getReg() == 0 && 647 "A fixed writing-back pseudo instruction provides an offset " 648 "register!"); 649 } else { 650 MIB.add(AM6Offset); 651 } 652 } 653 654 // For an instruction writing double-spaced subregs, the pseudo instruction 655 // has an extra operand that is a use of the super-register. Record the 656 // operand index and skip over it. 657 unsigned SrcOpIdx = 0; 658 if (!IsVLD2DUP) { 659 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc || 660 RegSpc == SingleLowSpc || RegSpc == SingleHighQSpc || 661 RegSpc == SingleHighTSpc) 662 SrcOpIdx = OpIdx++; 663 } 664 665 // Copy the predicate operands. 666 MIB.add(MI.getOperand(OpIdx++)); 667 MIB.add(MI.getOperand(OpIdx++)); 668 669 // Copy the super-register source operand used for double-spaced subregs over 670 // to the new instruction as an implicit operand. 671 if (SrcOpIdx != 0) { 672 MachineOperand MO = MI.getOperand(SrcOpIdx); 673 MO.setImplicit(true); 674 MIB.add(MO); 675 } 676 // Add an implicit def for the super-register. 677 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 678 TransferImpOps(MI, MIB, MIB); 679 680 // Transfer memoperands. 681 MIB.cloneMemRefs(MI); 682 MI.eraseFromParent(); 683 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump();); 684 } 685 686 /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register 687 /// operands to real VST instructions with D register operands. 688 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) { 689 MachineInstr &MI = *MBBI; 690 MachineBasicBlock &MBB = *MI.getParent(); 691 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump()); 692 693 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 694 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed"); 695 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; 696 unsigned NumRegs = TableEntry->NumRegs; 697 698 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 699 TII->get(TableEntry->RealOpc)); 700 unsigned OpIdx = 0; 701 if (TableEntry->isUpdating) 702 MIB.add(MI.getOperand(OpIdx++)); 703 704 // Copy the addrmode6 operands. 705 MIB.add(MI.getOperand(OpIdx++)); 706 MIB.add(MI.getOperand(OpIdx++)); 707 708 if (TableEntry->hasWritebackOperand) { 709 // TODO: The writing-back pseudo instructions we translate here are all 710 // defined to take am6offset nodes that are capable to represent both fixed 711 // and register forms. Some real instructions, however, do not rely on 712 // am6offset and have separate definitions for such forms. When this is the 713 // case, fixed forms do not take any offset nodes, so here we skip them for 714 // such instructions. Once all real and pseudo writing-back instructions are 715 // rewritten without use of am6offset nodes, this code will go away. 716 const MachineOperand &AM6Offset = MI.getOperand(OpIdx++); 717 if (TableEntry->RealOpc == ARM::VST1d8Qwb_fixed || 718 TableEntry->RealOpc == ARM::VST1d16Qwb_fixed || 719 TableEntry->RealOpc == ARM::VST1d32Qwb_fixed || 720 TableEntry->RealOpc == ARM::VST1d64Qwb_fixed || 721 TableEntry->RealOpc == ARM::VST1d8Twb_fixed || 722 TableEntry->RealOpc == ARM::VST1d16Twb_fixed || 723 TableEntry->RealOpc == ARM::VST1d32Twb_fixed || 724 TableEntry->RealOpc == ARM::VST1d64Twb_fixed) { 725 assert(AM6Offset.getReg() == 0 && 726 "A fixed writing-back pseudo instruction provides an offset " 727 "register!"); 728 } else { 729 MIB.add(AM6Offset); 730 } 731 } 732 733 bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 734 bool SrcIsUndef = MI.getOperand(OpIdx).isUndef(); 735 Register SrcReg = MI.getOperand(OpIdx++).getReg(); 736 unsigned D0, D1, D2, D3; 737 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3); 738 MIB.addReg(D0, getUndefRegState(SrcIsUndef)); 739 if (NumRegs > 1 && TableEntry->copyAllListRegs) 740 MIB.addReg(D1, getUndefRegState(SrcIsUndef)); 741 if (NumRegs > 2 && TableEntry->copyAllListRegs) 742 MIB.addReg(D2, getUndefRegState(SrcIsUndef)); 743 if (NumRegs > 3 && TableEntry->copyAllListRegs) 744 MIB.addReg(D3, getUndefRegState(SrcIsUndef)); 745 746 // Copy the predicate operands. 747 MIB.add(MI.getOperand(OpIdx++)); 748 MIB.add(MI.getOperand(OpIdx++)); 749 750 if (SrcIsKill && !SrcIsUndef) // Add an implicit kill for the super-reg. 751 MIB->addRegisterKilled(SrcReg, TRI, true); 752 else if (!SrcIsUndef) 753 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg. 754 TransferImpOps(MI, MIB, MIB); 755 756 // Transfer memoperands. 757 MIB.cloneMemRefs(MI); 758 MI.eraseFromParent(); 759 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump();); 760 } 761 762 /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ 763 /// register operands to real instructions with D register operands. 764 void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) { 765 MachineInstr &MI = *MBBI; 766 MachineBasicBlock &MBB = *MI.getParent(); 767 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump()); 768 769 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 770 assert(TableEntry && "NEONLdStTable lookup failed"); 771 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; 772 unsigned NumRegs = TableEntry->NumRegs; 773 unsigned RegElts = TableEntry->RegElts; 774 775 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 776 TII->get(TableEntry->RealOpc)); 777 unsigned OpIdx = 0; 778 // The lane operand is always the 3rd from last operand, before the 2 779 // predicate operands. 780 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm(); 781 782 // Adjust the lane and spacing as needed for Q registers. 783 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane"); 784 if (RegSpc == EvenDblSpc && Lane >= RegElts) { 785 RegSpc = OddDblSpc; 786 Lane -= RegElts; 787 } 788 assert(Lane < RegElts && "out of range lane for VLD/VST-lane"); 789 790 unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0; 791 unsigned DstReg = 0; 792 bool DstIsDead = false; 793 if (TableEntry->IsLoad) { 794 DstIsDead = MI.getOperand(OpIdx).isDead(); 795 DstReg = MI.getOperand(OpIdx++).getReg(); 796 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 797 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 798 if (NumRegs > 1) 799 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 800 if (NumRegs > 2) 801 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 802 if (NumRegs > 3) 803 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 804 } 805 806 if (TableEntry->isUpdating) 807 MIB.add(MI.getOperand(OpIdx++)); 808 809 // Copy the addrmode6 operands. 810 MIB.add(MI.getOperand(OpIdx++)); 811 MIB.add(MI.getOperand(OpIdx++)); 812 // Copy the am6offset operand. 813 if (TableEntry->hasWritebackOperand) 814 MIB.add(MI.getOperand(OpIdx++)); 815 816 // Grab the super-register source. 817 MachineOperand MO = MI.getOperand(OpIdx++); 818 if (!TableEntry->IsLoad) 819 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3); 820 821 // Add the subregs as sources of the new instruction. 822 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) | 823 getKillRegState(MO.isKill())); 824 MIB.addReg(D0, SrcFlags); 825 if (NumRegs > 1) 826 MIB.addReg(D1, SrcFlags); 827 if (NumRegs > 2) 828 MIB.addReg(D2, SrcFlags); 829 if (NumRegs > 3) 830 MIB.addReg(D3, SrcFlags); 831 832 // Add the lane number operand. 833 MIB.addImm(Lane); 834 OpIdx += 1; 835 836 // Copy the predicate operands. 837 MIB.add(MI.getOperand(OpIdx++)); 838 MIB.add(MI.getOperand(OpIdx++)); 839 840 // Copy the super-register source to be an implicit source. 841 MO.setImplicit(true); 842 MIB.add(MO); 843 if (TableEntry->IsLoad) 844 // Add an implicit def for the super-register. 845 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 846 TransferImpOps(MI, MIB, MIB); 847 // Transfer memoperands. 848 MIB.cloneMemRefs(MI); 849 MI.eraseFromParent(); 850 } 851 852 /// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ 853 /// register operands to real instructions with D register operands. 854 void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI, 855 unsigned Opc, bool IsExt) { 856 MachineInstr &MI = *MBBI; 857 MachineBasicBlock &MBB = *MI.getParent(); 858 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump()); 859 860 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); 861 unsigned OpIdx = 0; 862 863 // Transfer the destination register operand. 864 MIB.add(MI.getOperand(OpIdx++)); 865 if (IsExt) { 866 MachineOperand VdSrc(MI.getOperand(OpIdx++)); 867 MIB.add(VdSrc); 868 } 869 870 bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 871 Register SrcReg = MI.getOperand(OpIdx++).getReg(); 872 unsigned D0, D1, D2, D3; 873 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3); 874 MIB.addReg(D0); 875 876 // Copy the other source register operand. 877 MachineOperand VmSrc(MI.getOperand(OpIdx++)); 878 MIB.add(VmSrc); 879 880 // Copy the predicate operands. 881 MIB.add(MI.getOperand(OpIdx++)); 882 MIB.add(MI.getOperand(OpIdx++)); 883 884 // Add an implicit kill and use for the super-reg. 885 MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill)); 886 TransferImpOps(MI, MIB, MIB); 887 MI.eraseFromParent(); 888 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump();); 889 } 890 891 void ARMExpandPseudo::ExpandMQQPRLoadStore(MachineBasicBlock::iterator &MBBI) { 892 MachineInstr &MI = *MBBI; 893 MachineBasicBlock &MBB = *MI.getParent(); 894 unsigned NewOpc = 895 MI.getOpcode() == ARM::MQQPRStore || MI.getOpcode() == ARM::MQQQQPRStore 896 ? ARM::VSTMDIA 897 : ARM::VLDMDIA; 898 MachineInstrBuilder MIB = 899 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 900 901 unsigned Flags = getKillRegState(MI.getOperand(0).isKill()) | 902 getDefRegState(MI.getOperand(0).isDef()); 903 Register SrcReg = MI.getOperand(0).getReg(); 904 905 // Copy the destination register. 906 MIB.add(MI.getOperand(1)); 907 MIB.add(predOps(ARMCC::AL)); 908 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_0), Flags); 909 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_1), Flags); 910 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_2), Flags); 911 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_3), Flags); 912 if (MI.getOpcode() == ARM::MQQQQPRStore || 913 MI.getOpcode() == ARM::MQQQQPRLoad) { 914 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_4), Flags); 915 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_5), Flags); 916 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_6), Flags); 917 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_7), Flags); 918 } 919 920 if (NewOpc == ARM::VSTMDIA) 921 MIB.addReg(SrcReg, RegState::Implicit); 922 923 TransferImpOps(MI, MIB, MIB); 924 MIB.cloneMemRefs(MI); 925 MI.eraseFromParent(); 926 } 927 928 static bool IsAnAddressOperand(const MachineOperand &MO) { 929 // This check is overly conservative. Unless we are certain that the machine 930 // operand is not a symbol reference, we return that it is a symbol reference. 931 // This is important as the load pair may not be split up Windows. 932 switch (MO.getType()) { 933 case MachineOperand::MO_Register: 934 case MachineOperand::MO_Immediate: 935 case MachineOperand::MO_CImmediate: 936 case MachineOperand::MO_FPImmediate: 937 case MachineOperand::MO_ShuffleMask: 938 return false; 939 case MachineOperand::MO_MachineBasicBlock: 940 return true; 941 case MachineOperand::MO_FrameIndex: 942 return false; 943 case MachineOperand::MO_ConstantPoolIndex: 944 case MachineOperand::MO_TargetIndex: 945 case MachineOperand::MO_JumpTableIndex: 946 case MachineOperand::MO_ExternalSymbol: 947 case MachineOperand::MO_GlobalAddress: 948 case MachineOperand::MO_BlockAddress: 949 return true; 950 case MachineOperand::MO_RegisterMask: 951 case MachineOperand::MO_RegisterLiveOut: 952 return false; 953 case MachineOperand::MO_Metadata: 954 case MachineOperand::MO_MCSymbol: 955 return true; 956 case MachineOperand::MO_CFIIndex: 957 return false; 958 case MachineOperand::MO_IntrinsicID: 959 case MachineOperand::MO_Predicate: 960 llvm_unreachable("should not exist post-isel"); 961 } 962 llvm_unreachable("unhandled machine operand type"); 963 } 964 965 static MachineOperand makeImplicit(const MachineOperand &MO) { 966 MachineOperand NewMO = MO; 967 NewMO.setImplicit(); 968 return NewMO; 969 } 970 971 void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB, 972 MachineBasicBlock::iterator &MBBI) { 973 MachineInstr &MI = *MBBI; 974 unsigned Opcode = MI.getOpcode(); 975 Register PredReg; 976 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); 977 Register DstReg = MI.getOperand(0).getReg(); 978 bool DstIsDead = MI.getOperand(0).isDead(); 979 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm; 980 const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1); 981 bool RequiresBundling = STI->isTargetWindows() && IsAnAddressOperand(MO); 982 MachineInstrBuilder LO16, HI16; 983 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump()); 984 985 if (!STI->hasV6T2Ops() && 986 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) { 987 // FIXME Windows CE supports older ARM CPUs 988 assert(!STI->isTargetWindows() && "Windows on ARM requires ARMv7+"); 989 990 assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!"); 991 unsigned ImmVal = (unsigned)MO.getImm(); 992 unsigned SOImmValV1 = 0, SOImmValV2 = 0; 993 994 if (ARM_AM::isSOImmTwoPartVal(ImmVal)) { // Expand into a movi + orr. 995 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); 996 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri)) 997 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 998 .addReg(DstReg); 999 SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal); 1000 SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal); 1001 } else { // Expand into a mvn + sub. 1002 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MVNi), DstReg); 1003 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri)) 1004 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 1005 .addReg(DstReg); 1006 SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(-ImmVal); 1007 SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(-ImmVal); 1008 SOImmValV1 = ~(-SOImmValV1); 1009 } 1010 1011 unsigned MIFlags = MI.getFlags(); 1012 LO16 = LO16.addImm(SOImmValV1); 1013 HI16 = HI16.addImm(SOImmValV2); 1014 LO16.cloneMemRefs(MI); 1015 HI16.cloneMemRefs(MI); 1016 LO16.setMIFlags(MIFlags); 1017 HI16.setMIFlags(MIFlags); 1018 LO16.addImm(Pred).addReg(PredReg).add(condCodeOp()); 1019 HI16.addImm(Pred).addReg(PredReg).add(condCodeOp()); 1020 if (isCC) 1021 LO16.add(makeImplicit(MI.getOperand(1))); 1022 TransferImpOps(MI, LO16, HI16); 1023 MI.eraseFromParent(); 1024 return; 1025 } 1026 1027 unsigned LO16Opc = 0; 1028 unsigned HI16Opc = 0; 1029 unsigned MIFlags = MI.getFlags(); 1030 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) { 1031 LO16Opc = ARM::t2MOVi16; 1032 HI16Opc = ARM::t2MOVTi16; 1033 } else { 1034 LO16Opc = ARM::MOVi16; 1035 HI16Opc = ARM::MOVTi16; 1036 } 1037 1038 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg); 1039 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc)) 1040 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 1041 .addReg(DstReg); 1042 1043 LO16.setMIFlags(MIFlags); 1044 HI16.setMIFlags(MIFlags); 1045 1046 switch (MO.getType()) { 1047 case MachineOperand::MO_Immediate: { 1048 unsigned Imm = MO.getImm(); 1049 unsigned Lo16 = Imm & 0xffff; 1050 unsigned Hi16 = (Imm >> 16) & 0xffff; 1051 LO16 = LO16.addImm(Lo16); 1052 HI16 = HI16.addImm(Hi16); 1053 break; 1054 } 1055 case MachineOperand::MO_ExternalSymbol: { 1056 const char *ES = MO.getSymbolName(); 1057 unsigned TF = MO.getTargetFlags(); 1058 LO16 = LO16.addExternalSymbol(ES, TF | ARMII::MO_LO16); 1059 HI16 = HI16.addExternalSymbol(ES, TF | ARMII::MO_HI16); 1060 break; 1061 } 1062 default: { 1063 const GlobalValue *GV = MO.getGlobal(); 1064 unsigned TF = MO.getTargetFlags(); 1065 LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16); 1066 HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16); 1067 break; 1068 } 1069 } 1070 1071 LO16.cloneMemRefs(MI); 1072 HI16.cloneMemRefs(MI); 1073 LO16.addImm(Pred).addReg(PredReg); 1074 HI16.addImm(Pred).addReg(PredReg); 1075 1076 if (RequiresBundling) 1077 finalizeBundle(MBB, LO16->getIterator(), MBBI->getIterator()); 1078 1079 if (isCC) 1080 LO16.add(makeImplicit(MI.getOperand(1))); 1081 TransferImpOps(MI, LO16, HI16); 1082 MI.eraseFromParent(); 1083 LLVM_DEBUG(dbgs() << "To: "; LO16.getInstr()->dump();); 1084 LLVM_DEBUG(dbgs() << "And: "; HI16.getInstr()->dump();); 1085 } 1086 1087 // The size of the area, accessed by that VLSTM/VLLDM 1088 // S0-S31 + FPSCR + 8 more bytes (VPR + pad, or just pad) 1089 static const int CMSE_FP_SAVE_SIZE = 136; 1090 1091 static void determineGPRegsToClear(const MachineInstr &MI, 1092 const std::initializer_list<unsigned> &Regs, 1093 SmallVectorImpl<unsigned> &ClearRegs) { 1094 SmallVector<unsigned, 4> OpRegs; 1095 for (const MachineOperand &Op : MI.operands()) { 1096 if (!Op.isReg() || !Op.isUse()) 1097 continue; 1098 OpRegs.push_back(Op.getReg()); 1099 } 1100 llvm::sort(OpRegs); 1101 1102 std::set_difference(Regs.begin(), Regs.end(), OpRegs.begin(), OpRegs.end(), 1103 std::back_inserter(ClearRegs)); 1104 } 1105 1106 void ARMExpandPseudo::CMSEClearGPRegs( 1107 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 1108 const DebugLoc &DL, const SmallVectorImpl<unsigned> &ClearRegs, 1109 unsigned ClobberReg) { 1110 1111 if (STI->hasV8_1MMainlineOps()) { 1112 // Clear the registers using the CLRM instruction. 1113 MachineInstrBuilder CLRM = 1114 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2CLRM)).add(predOps(ARMCC::AL)); 1115 for (unsigned R : ClearRegs) 1116 CLRM.addReg(R, RegState::Define); 1117 CLRM.addReg(ARM::APSR, RegState::Define); 1118 CLRM.addReg(ARM::CPSR, RegState::Define | RegState::Implicit); 1119 } else { 1120 // Clear the registers and flags by copying ClobberReg into them. 1121 // (Baseline can't do a high register clear in one instruction). 1122 for (unsigned Reg : ClearRegs) { 1123 if (Reg == ClobberReg) 1124 continue; 1125 BuildMI(MBB, MBBI, DL, TII->get(ARM::tMOVr), Reg) 1126 .addReg(ClobberReg) 1127 .add(predOps(ARMCC::AL)); 1128 } 1129 1130 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2MSR_M)) 1131 .addImm(STI->hasDSP() ? 0xc00 : 0x800) 1132 .addReg(ClobberReg) 1133 .add(predOps(ARMCC::AL)); 1134 } 1135 } 1136 1137 // Find which FP registers need to be cleared. The parameter `ClearRegs` is 1138 // initialised with all elements set to true, and this function resets all the 1139 // bits, which correspond to register uses. Returns true if any floating point 1140 // register is defined, false otherwise. 1141 static bool determineFPRegsToClear(const MachineInstr &MI, 1142 BitVector &ClearRegs) { 1143 bool DefFP = false; 1144 for (const MachineOperand &Op : MI.operands()) { 1145 if (!Op.isReg()) 1146 continue; 1147 1148 Register Reg = Op.getReg(); 1149 if (Op.isDef()) { 1150 if ((Reg >= ARM::Q0 && Reg <= ARM::Q7) || 1151 (Reg >= ARM::D0 && Reg <= ARM::D15) || 1152 (Reg >= ARM::S0 && Reg <= ARM::S31)) 1153 DefFP = true; 1154 continue; 1155 } 1156 1157 if (Reg >= ARM::Q0 && Reg <= ARM::Q7) { 1158 int R = Reg - ARM::Q0; 1159 ClearRegs.reset(R * 4, (R + 1) * 4); 1160 } else if (Reg >= ARM::D0 && Reg <= ARM::D15) { 1161 int R = Reg - ARM::D0; 1162 ClearRegs.reset(R * 2, (R + 1) * 2); 1163 } else if (Reg >= ARM::S0 && Reg <= ARM::S31) { 1164 ClearRegs[Reg - ARM::S0] = false; 1165 } 1166 } 1167 return DefFP; 1168 } 1169 1170 MachineBasicBlock & 1171 ARMExpandPseudo::CMSEClearFPRegs(MachineBasicBlock &MBB, 1172 MachineBasicBlock::iterator MBBI) { 1173 BitVector ClearRegs(16, true); 1174 (void)determineFPRegsToClear(*MBBI, ClearRegs); 1175 1176 if (STI->hasV8_1MMainlineOps()) 1177 return CMSEClearFPRegsV81(MBB, MBBI, ClearRegs); 1178 else 1179 return CMSEClearFPRegsV8(MBB, MBBI, ClearRegs); 1180 } 1181 1182 // Clear the FP registers for v8.0-M, by copying over the content 1183 // of LR. Uses R12 as a scratch register. 1184 MachineBasicBlock & 1185 ARMExpandPseudo::CMSEClearFPRegsV8(MachineBasicBlock &MBB, 1186 MachineBasicBlock::iterator MBBI, 1187 const BitVector &ClearRegs) { 1188 if (!STI->hasFPRegs()) 1189 return MBB; 1190 1191 auto &RetI = *MBBI; 1192 const DebugLoc &DL = RetI.getDebugLoc(); 1193 1194 // If optimising for minimum size, clear FP registers unconditionally. 1195 // Otherwise, check the CONTROL.SFPA (Secure Floating-Point Active) bit and 1196 // don't clear them if they belong to the non-secure state. 1197 MachineBasicBlock *ClearBB, *DoneBB; 1198 if (STI->hasMinSize()) { 1199 ClearBB = DoneBB = &MBB; 1200 } else { 1201 MachineFunction *MF = MBB.getParent(); 1202 ClearBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 1203 DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 1204 1205 MF->insert(++MBB.getIterator(), ClearBB); 1206 MF->insert(++ClearBB->getIterator(), DoneBB); 1207 1208 DoneBB->splice(DoneBB->end(), &MBB, MBBI, MBB.end()); 1209 DoneBB->transferSuccessors(&MBB); 1210 MBB.addSuccessor(ClearBB); 1211 MBB.addSuccessor(DoneBB); 1212 ClearBB->addSuccessor(DoneBB); 1213 1214 // At the new basic blocks we need to have live-in the registers, used 1215 // for the return value as well as LR, used to clear registers. 1216 for (const MachineOperand &Op : RetI.operands()) { 1217 if (!Op.isReg()) 1218 continue; 1219 Register Reg = Op.getReg(); 1220 if (Reg == ARM::NoRegister || Reg == ARM::LR) 1221 continue; 1222 assert(Register::isPhysicalRegister(Reg) && "Unallocated register"); 1223 ClearBB->addLiveIn(Reg); 1224 DoneBB->addLiveIn(Reg); 1225 } 1226 ClearBB->addLiveIn(ARM::LR); 1227 DoneBB->addLiveIn(ARM::LR); 1228 1229 // Read the CONTROL register. 1230 BuildMI(MBB, MBB.end(), DL, TII->get(ARM::t2MRS_M), ARM::R12) 1231 .addImm(20) 1232 .add(predOps(ARMCC::AL)); 1233 // Check bit 3 (SFPA). 1234 BuildMI(MBB, MBB.end(), DL, TII->get(ARM::t2TSTri)) 1235 .addReg(ARM::R12) 1236 .addImm(8) 1237 .add(predOps(ARMCC::AL)); 1238 // If SFPA is clear, jump over ClearBB to DoneBB. 1239 BuildMI(MBB, MBB.end(), DL, TII->get(ARM::tBcc)) 1240 .addMBB(DoneBB) 1241 .addImm(ARMCC::EQ) 1242 .addReg(ARM::CPSR, RegState::Kill); 1243 } 1244 1245 // Emit the clearing sequence 1246 for (unsigned D = 0; D < 8; D++) { 1247 // Attempt to clear as double 1248 if (ClearRegs[D * 2 + 0] && ClearRegs[D * 2 + 1]) { 1249 unsigned Reg = ARM::D0 + D; 1250 BuildMI(ClearBB, DL, TII->get(ARM::VMOVDRR), Reg) 1251 .addReg(ARM::LR) 1252 .addReg(ARM::LR) 1253 .add(predOps(ARMCC::AL)); 1254 } else { 1255 // Clear first part as single 1256 if (ClearRegs[D * 2 + 0]) { 1257 unsigned Reg = ARM::S0 + D * 2; 1258 BuildMI(ClearBB, DL, TII->get(ARM::VMOVSR), Reg) 1259 .addReg(ARM::LR) 1260 .add(predOps(ARMCC::AL)); 1261 } 1262 // Clear second part as single 1263 if (ClearRegs[D * 2 + 1]) { 1264 unsigned Reg = ARM::S0 + D * 2 + 1; 1265 BuildMI(ClearBB, DL, TII->get(ARM::VMOVSR), Reg) 1266 .addReg(ARM::LR) 1267 .add(predOps(ARMCC::AL)); 1268 } 1269 } 1270 } 1271 1272 // Clear FPSCR bits 0-4, 7, 28-31 1273 // The other bits are program global according to the AAPCS 1274 BuildMI(ClearBB, DL, TII->get(ARM::VMRS), ARM::R12) 1275 .add(predOps(ARMCC::AL)); 1276 BuildMI(ClearBB, DL, TII->get(ARM::t2BICri), ARM::R12) 1277 .addReg(ARM::R12) 1278 .addImm(0x0000009F) 1279 .add(predOps(ARMCC::AL)) 1280 .add(condCodeOp()); 1281 BuildMI(ClearBB, DL, TII->get(ARM::t2BICri), ARM::R12) 1282 .addReg(ARM::R12) 1283 .addImm(0xF0000000) 1284 .add(predOps(ARMCC::AL)) 1285 .add(condCodeOp()); 1286 BuildMI(ClearBB, DL, TII->get(ARM::VMSR)) 1287 .addReg(ARM::R12) 1288 .add(predOps(ARMCC::AL)); 1289 1290 return *DoneBB; 1291 } 1292 1293 MachineBasicBlock & 1294 ARMExpandPseudo::CMSEClearFPRegsV81(MachineBasicBlock &MBB, 1295 MachineBasicBlock::iterator MBBI, 1296 const BitVector &ClearRegs) { 1297 auto &RetI = *MBBI; 1298 1299 // Emit a sequence of VSCCLRM <sreglist> instructions, one instruction for 1300 // each contiguous sequence of S-registers. 1301 int Start = -1, End = -1; 1302 for (int S = 0, E = ClearRegs.size(); S != E; ++S) { 1303 if (ClearRegs[S] && S == End + 1) { 1304 End = S; // extend range 1305 continue; 1306 } 1307 // Emit current range. 1308 if (Start < End) { 1309 MachineInstrBuilder VSCCLRM = 1310 BuildMI(MBB, MBBI, RetI.getDebugLoc(), TII->get(ARM::VSCCLRMS)) 1311 .add(predOps(ARMCC::AL)); 1312 while (++Start <= End) 1313 VSCCLRM.addReg(ARM::S0 + Start, RegState::Define); 1314 VSCCLRM.addReg(ARM::VPR, RegState::Define); 1315 } 1316 Start = End = S; 1317 } 1318 // Emit last range. 1319 if (Start < End) { 1320 MachineInstrBuilder VSCCLRM = 1321 BuildMI(MBB, MBBI, RetI.getDebugLoc(), TII->get(ARM::VSCCLRMS)) 1322 .add(predOps(ARMCC::AL)); 1323 while (++Start <= End) 1324 VSCCLRM.addReg(ARM::S0 + Start, RegState::Define); 1325 VSCCLRM.addReg(ARM::VPR, RegState::Define); 1326 } 1327 1328 return MBB; 1329 } 1330 1331 void ARMExpandPseudo::CMSESaveClearFPRegs( 1332 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL, 1333 const LivePhysRegs &LiveRegs, SmallVectorImpl<unsigned> &ScratchRegs) { 1334 if (STI->hasV8_1MMainlineOps()) 1335 CMSESaveClearFPRegsV81(MBB, MBBI, DL, LiveRegs); 1336 else if (STI->hasV8MMainlineOps()) 1337 CMSESaveClearFPRegsV8(MBB, MBBI, DL, LiveRegs, ScratchRegs); 1338 } 1339 1340 // Save and clear FP registers if present 1341 void ARMExpandPseudo::CMSESaveClearFPRegsV8( 1342 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL, 1343 const LivePhysRegs &LiveRegs, SmallVectorImpl<unsigned> &ScratchRegs) { 1344 1345 // Store an available register for FPSCR clearing 1346 assert(!ScratchRegs.empty()); 1347 unsigned SpareReg = ScratchRegs.front(); 1348 1349 // save space on stack for VLSTM 1350 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBspi), ARM::SP) 1351 .addReg(ARM::SP) 1352 .addImm(CMSE_FP_SAVE_SIZE >> 2) 1353 .add(predOps(ARMCC::AL)); 1354 1355 // Use ScratchRegs to store the fp regs 1356 std::vector<std::tuple<unsigned, unsigned, unsigned>> ClearedFPRegs; 1357 std::vector<unsigned> NonclearedFPRegs; 1358 for (const MachineOperand &Op : MBBI->operands()) { 1359 if (Op.isReg() && Op.isUse()) { 1360 Register Reg = Op.getReg(); 1361 assert(!ARM::DPRRegClass.contains(Reg) || 1362 ARM::DPR_VFP2RegClass.contains(Reg)); 1363 assert(!ARM::QPRRegClass.contains(Reg)); 1364 if (ARM::DPR_VFP2RegClass.contains(Reg)) { 1365 if (ScratchRegs.size() >= 2) { 1366 unsigned SaveReg2 = ScratchRegs.pop_back_val(); 1367 unsigned SaveReg1 = ScratchRegs.pop_back_val(); 1368 ClearedFPRegs.emplace_back(Reg, SaveReg1, SaveReg2); 1369 1370 // Save the fp register to the normal registers 1371 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRRD)) 1372 .addReg(SaveReg1, RegState::Define) 1373 .addReg(SaveReg2, RegState::Define) 1374 .addReg(Reg) 1375 .add(predOps(ARMCC::AL)); 1376 } else { 1377 NonclearedFPRegs.push_back(Reg); 1378 } 1379 } else if (ARM::SPRRegClass.contains(Reg)) { 1380 if (ScratchRegs.size() >= 1) { 1381 unsigned SaveReg = ScratchRegs.pop_back_val(); 1382 ClearedFPRegs.emplace_back(Reg, SaveReg, 0); 1383 1384 // Save the fp register to the normal registers 1385 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRS), SaveReg) 1386 .addReg(Reg) 1387 .add(predOps(ARMCC::AL)); 1388 } else { 1389 NonclearedFPRegs.push_back(Reg); 1390 } 1391 } 1392 } 1393 } 1394 1395 bool passesFPReg = (!NonclearedFPRegs.empty() || !ClearedFPRegs.empty()); 1396 1397 if (passesFPReg) 1398 assert(STI->hasFPRegs() && "Subtarget needs fpregs"); 1399 1400 // Lazy store all fp registers to the stack. 1401 // This executes as NOP in the absence of floating-point support. 1402 MachineInstrBuilder VLSTM = BuildMI(MBB, MBBI, DL, TII->get(ARM::VLSTM)) 1403 .addReg(ARM::SP) 1404 .add(predOps(ARMCC::AL)); 1405 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, 1406 ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7}) 1407 VLSTM.addReg(R, RegState::Implicit | 1408 (LiveRegs.contains(R) ? 0 : RegState::Undef)); 1409 1410 // Restore all arguments 1411 for (const auto &Regs : ClearedFPRegs) { 1412 unsigned Reg, SaveReg1, SaveReg2; 1413 std::tie(Reg, SaveReg1, SaveReg2) = Regs; 1414 if (ARM::DPR_VFP2RegClass.contains(Reg)) 1415 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg) 1416 .addReg(SaveReg1) 1417 .addReg(SaveReg2) 1418 .add(predOps(ARMCC::AL)); 1419 else if (ARM::SPRRegClass.contains(Reg)) 1420 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVSR), Reg) 1421 .addReg(SaveReg1) 1422 .add(predOps(ARMCC::AL)); 1423 } 1424 1425 for (unsigned Reg : NonclearedFPRegs) { 1426 if (ARM::DPR_VFP2RegClass.contains(Reg)) { 1427 if (STI->isLittle()) { 1428 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRD), Reg) 1429 .addReg(ARM::SP) 1430 .addImm((Reg - ARM::D0) * 2) 1431 .add(predOps(ARMCC::AL)); 1432 } else { 1433 // For big-endian targets we need to load the two subregisters of Reg 1434 // manually because VLDRD would load them in wrong order 1435 unsigned SReg0 = TRI->getSubReg(Reg, ARM::ssub_0); 1436 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), SReg0) 1437 .addReg(ARM::SP) 1438 .addImm((Reg - ARM::D0) * 2) 1439 .add(predOps(ARMCC::AL)); 1440 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), SReg0 + 1) 1441 .addReg(ARM::SP) 1442 .addImm((Reg - ARM::D0) * 2 + 1) 1443 .add(predOps(ARMCC::AL)); 1444 } 1445 } else if (ARM::SPRRegClass.contains(Reg)) { 1446 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), Reg) 1447 .addReg(ARM::SP) 1448 .addImm(Reg - ARM::S0) 1449 .add(predOps(ARMCC::AL)); 1450 } 1451 } 1452 // restore FPSCR from stack and clear bits 0-4, 7, 28-31 1453 // The other bits are program global according to the AAPCS 1454 if (passesFPReg) { 1455 BuildMI(MBB, MBBI, DL, TII->get(ARM::tLDRspi), SpareReg) 1456 .addReg(ARM::SP) 1457 .addImm(0x10) 1458 .add(predOps(ARMCC::AL)); 1459 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), SpareReg) 1460 .addReg(SpareReg) 1461 .addImm(0x0000009F) 1462 .add(predOps(ARMCC::AL)) 1463 .add(condCodeOp()); 1464 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), SpareReg) 1465 .addReg(SpareReg) 1466 .addImm(0xF0000000) 1467 .add(predOps(ARMCC::AL)) 1468 .add(condCodeOp()); 1469 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMSR)) 1470 .addReg(SpareReg) 1471 .add(predOps(ARMCC::AL)); 1472 // The ldr must happen after a floating point instruction. To prevent the 1473 // post-ra scheduler to mess with the order, we create a bundle. 1474 finalizeBundle(MBB, VLSTM->getIterator(), MBBI->getIterator()); 1475 } 1476 } 1477 1478 void ARMExpandPseudo::CMSESaveClearFPRegsV81(MachineBasicBlock &MBB, 1479 MachineBasicBlock::iterator MBBI, 1480 DebugLoc &DL, 1481 const LivePhysRegs &LiveRegs) { 1482 BitVector ClearRegs(32, true); 1483 bool DefFP = determineFPRegsToClear(*MBBI, ClearRegs); 1484 1485 // If the instruction does not write to a FP register and no elements were 1486 // removed from the set, then no FP registers were used to pass 1487 // arguments/returns. 1488 if (!DefFP && ClearRegs.count() == ClearRegs.size()) { 1489 // save space on stack for VLSTM 1490 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBspi), ARM::SP) 1491 .addReg(ARM::SP) 1492 .addImm(CMSE_FP_SAVE_SIZE >> 2) 1493 .add(predOps(ARMCC::AL)); 1494 1495 // Lazy store all FP registers to the stack 1496 MachineInstrBuilder VLSTM = BuildMI(MBB, MBBI, DL, TII->get(ARM::VLSTM)) 1497 .addReg(ARM::SP) 1498 .add(predOps(ARMCC::AL)); 1499 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, 1500 ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7}) 1501 VLSTM.addReg(R, RegState::Implicit | 1502 (LiveRegs.contains(R) ? 0 : RegState::Undef)); 1503 } else { 1504 // Push all the callee-saved registers (s16-s31). 1505 MachineInstrBuilder VPUSH = 1506 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTMSDB_UPD), ARM::SP) 1507 .addReg(ARM::SP) 1508 .add(predOps(ARMCC::AL)); 1509 for (int Reg = ARM::S16; Reg <= ARM::S31; ++Reg) 1510 VPUSH.addReg(Reg); 1511 1512 // Clear FP registers with a VSCCLRM. 1513 (void)CMSEClearFPRegsV81(MBB, MBBI, ClearRegs); 1514 1515 // Save floating-point context. 1516 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTR_FPCXTS_pre), ARM::SP) 1517 .addReg(ARM::SP) 1518 .addImm(-8) 1519 .add(predOps(ARMCC::AL)); 1520 } 1521 } 1522 1523 // Restore FP registers if present 1524 void ARMExpandPseudo::CMSERestoreFPRegs( 1525 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL, 1526 SmallVectorImpl<unsigned> &AvailableRegs) { 1527 if (STI->hasV8_1MMainlineOps()) 1528 CMSERestoreFPRegsV81(MBB, MBBI, DL, AvailableRegs); 1529 else if (STI->hasV8MMainlineOps()) 1530 CMSERestoreFPRegsV8(MBB, MBBI, DL, AvailableRegs); 1531 } 1532 1533 void ARMExpandPseudo::CMSERestoreFPRegsV8( 1534 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL, 1535 SmallVectorImpl<unsigned> &AvailableRegs) { 1536 1537 // Keep a scratch register for the mitigation sequence. 1538 unsigned ScratchReg = ARM::NoRegister; 1539 if (STI->fixCMSE_CVE_2021_35465()) 1540 ScratchReg = AvailableRegs.pop_back_val(); 1541 1542 // Use AvailableRegs to store the fp regs 1543 std::vector<std::tuple<unsigned, unsigned, unsigned>> ClearedFPRegs; 1544 std::vector<unsigned> NonclearedFPRegs; 1545 for (const MachineOperand &Op : MBBI->operands()) { 1546 if (Op.isReg() && Op.isDef()) { 1547 Register Reg = Op.getReg(); 1548 assert(!ARM::DPRRegClass.contains(Reg) || 1549 ARM::DPR_VFP2RegClass.contains(Reg)); 1550 assert(!ARM::QPRRegClass.contains(Reg)); 1551 if (ARM::DPR_VFP2RegClass.contains(Reg)) { 1552 if (AvailableRegs.size() >= 2) { 1553 unsigned SaveReg2 = AvailableRegs.pop_back_val(); 1554 unsigned SaveReg1 = AvailableRegs.pop_back_val(); 1555 ClearedFPRegs.emplace_back(Reg, SaveReg1, SaveReg2); 1556 1557 // Save the fp register to the normal registers 1558 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRRD)) 1559 .addReg(SaveReg1, RegState::Define) 1560 .addReg(SaveReg2, RegState::Define) 1561 .addReg(Reg) 1562 .add(predOps(ARMCC::AL)); 1563 } else { 1564 NonclearedFPRegs.push_back(Reg); 1565 } 1566 } else if (ARM::SPRRegClass.contains(Reg)) { 1567 if (AvailableRegs.size() >= 1) { 1568 unsigned SaveReg = AvailableRegs.pop_back_val(); 1569 ClearedFPRegs.emplace_back(Reg, SaveReg, 0); 1570 1571 // Save the fp register to the normal registers 1572 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRS), SaveReg) 1573 .addReg(Reg) 1574 .add(predOps(ARMCC::AL)); 1575 } else { 1576 NonclearedFPRegs.push_back(Reg); 1577 } 1578 } 1579 } 1580 } 1581 1582 bool returnsFPReg = (!NonclearedFPRegs.empty() || !ClearedFPRegs.empty()); 1583 1584 if (returnsFPReg) 1585 assert(STI->hasFPRegs() && "Subtarget needs fpregs"); 1586 1587 // Push FP regs that cannot be restored via normal registers on the stack 1588 for (unsigned Reg : NonclearedFPRegs) { 1589 if (ARM::DPR_VFP2RegClass.contains(Reg)) 1590 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTRD)) 1591 .addReg(Reg) 1592 .addReg(ARM::SP) 1593 .addImm((Reg - ARM::D0) * 2) 1594 .add(predOps(ARMCC::AL)); 1595 else if (ARM::SPRRegClass.contains(Reg)) 1596 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTRS)) 1597 .addReg(Reg) 1598 .addReg(ARM::SP) 1599 .addImm(Reg - ARM::S0) 1600 .add(predOps(ARMCC::AL)); 1601 } 1602 1603 // Lazy load fp regs from stack. 1604 // This executes as NOP in the absence of floating-point support. 1605 MachineInstrBuilder VLLDM = BuildMI(MBB, MBBI, DL, TII->get(ARM::VLLDM)) 1606 .addReg(ARM::SP) 1607 .add(predOps(ARMCC::AL)); 1608 1609 if (STI->fixCMSE_CVE_2021_35465()) { 1610 auto Bundler = MIBundleBuilder(MBB, VLLDM); 1611 // Read the CONTROL register. 1612 Bundler.append(BuildMI(*MBB.getParent(), DL, TII->get(ARM::t2MRS_M)) 1613 .addReg(ScratchReg, RegState::Define) 1614 .addImm(20) 1615 .add(predOps(ARMCC::AL))); 1616 // Check bit 3 (SFPA). 1617 Bundler.append(BuildMI(*MBB.getParent(), DL, TII->get(ARM::t2TSTri)) 1618 .addReg(ScratchReg) 1619 .addImm(8) 1620 .add(predOps(ARMCC::AL))); 1621 // Emit the IT block. 1622 Bundler.append(BuildMI(*MBB.getParent(), DL, TII->get(ARM::t2IT)) 1623 .addImm(ARMCC::NE) 1624 .addImm(8)); 1625 // If SFPA is clear jump over to VLLDM, otherwise execute an instruction 1626 // which has no functional effect apart from causing context creation: 1627 // vmovne s0, s0. In the absence of FPU we emit .inst.w 0xeeb00a40, 1628 // which is defined as NOP if not executed. 1629 if (STI->hasFPRegs()) 1630 Bundler.append(BuildMI(*MBB.getParent(), DL, TII->get(ARM::VMOVS)) 1631 .addReg(ARM::S0, RegState::Define) 1632 .addReg(ARM::S0, RegState::Undef) 1633 .add(predOps(ARMCC::NE))); 1634 else 1635 Bundler.append(BuildMI(*MBB.getParent(), DL, TII->get(ARM::INLINEASM)) 1636 .addExternalSymbol(".inst.w 0xeeb00a40") 1637 .addImm(InlineAsm::Extra_HasSideEffects)); 1638 finalizeBundle(MBB, Bundler.begin(), Bundler.end()); 1639 } 1640 1641 // Restore all FP registers via normal registers 1642 for (const auto &Regs : ClearedFPRegs) { 1643 unsigned Reg, SaveReg1, SaveReg2; 1644 std::tie(Reg, SaveReg1, SaveReg2) = Regs; 1645 if (ARM::DPR_VFP2RegClass.contains(Reg)) 1646 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg) 1647 .addReg(SaveReg1) 1648 .addReg(SaveReg2) 1649 .add(predOps(ARMCC::AL)); 1650 else if (ARM::SPRRegClass.contains(Reg)) 1651 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVSR), Reg) 1652 .addReg(SaveReg1) 1653 .add(predOps(ARMCC::AL)); 1654 } 1655 1656 // Pop the stack space 1657 BuildMI(MBB, MBBI, DL, TII->get(ARM::tADDspi), ARM::SP) 1658 .addReg(ARM::SP) 1659 .addImm(CMSE_FP_SAVE_SIZE >> 2) 1660 .add(predOps(ARMCC::AL)); 1661 } 1662 1663 static bool definesOrUsesFPReg(const MachineInstr &MI) { 1664 for (const MachineOperand &Op : MI.operands()) { 1665 if (!Op.isReg()) 1666 continue; 1667 Register Reg = Op.getReg(); 1668 if ((Reg >= ARM::Q0 && Reg <= ARM::Q7) || 1669 (Reg >= ARM::D0 && Reg <= ARM::D15) || 1670 (Reg >= ARM::S0 && Reg <= ARM::S31)) 1671 return true; 1672 } 1673 return false; 1674 } 1675 1676 void ARMExpandPseudo::CMSERestoreFPRegsV81( 1677 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL, 1678 SmallVectorImpl<unsigned> &AvailableRegs) { 1679 if (!definesOrUsesFPReg(*MBBI)) { 1680 if (STI->fixCMSE_CVE_2021_35465()) { 1681 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSCCLRMS)) 1682 .add(predOps(ARMCC::AL)) 1683 .addReg(ARM::VPR, RegState::Define); 1684 } 1685 1686 // Load FP registers from stack. 1687 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLLDM)) 1688 .addReg(ARM::SP) 1689 .add(predOps(ARMCC::AL)); 1690 1691 // Pop the stack space 1692 BuildMI(MBB, MBBI, DL, TII->get(ARM::tADDspi), ARM::SP) 1693 .addReg(ARM::SP) 1694 .addImm(CMSE_FP_SAVE_SIZE >> 2) 1695 .add(predOps(ARMCC::AL)); 1696 } else { 1697 // Restore the floating point context. 1698 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(ARM::VLDR_FPCXTS_post), 1699 ARM::SP) 1700 .addReg(ARM::SP) 1701 .addImm(8) 1702 .add(predOps(ARMCC::AL)); 1703 1704 // Pop all the callee-saved registers (s16-s31). 1705 MachineInstrBuilder VPOP = 1706 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDMSIA_UPD), ARM::SP) 1707 .addReg(ARM::SP) 1708 .add(predOps(ARMCC::AL)); 1709 for (int Reg = ARM::S16; Reg <= ARM::S31; ++Reg) 1710 VPOP.addReg(Reg, RegState::Define); 1711 } 1712 } 1713 1714 /// Expand a CMP_SWAP pseudo-inst to an ldrex/strex loop as simply as 1715 /// possible. This only gets used at -O0 so we don't care about efficiency of 1716 /// the generated code. 1717 bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock &MBB, 1718 MachineBasicBlock::iterator MBBI, 1719 unsigned LdrexOp, unsigned StrexOp, 1720 unsigned UxtOp, 1721 MachineBasicBlock::iterator &NextMBBI) { 1722 bool IsThumb = STI->isThumb(); 1723 MachineInstr &MI = *MBBI; 1724 DebugLoc DL = MI.getDebugLoc(); 1725 const MachineOperand &Dest = MI.getOperand(0); 1726 Register TempReg = MI.getOperand(1).getReg(); 1727 // Duplicating undef operands into 2 instructions does not guarantee the same 1728 // value on both; However undef should be replaced by xzr anyway. 1729 assert(!MI.getOperand(2).isUndef() && "cannot handle undef"); 1730 Register AddrReg = MI.getOperand(2).getReg(); 1731 Register DesiredReg = MI.getOperand(3).getReg(); 1732 Register NewReg = MI.getOperand(4).getReg(); 1733 1734 if (IsThumb) { 1735 assert(STI->hasV8MBaselineOps() && 1736 "CMP_SWAP not expected to be custom expanded for Thumb1"); 1737 assert((UxtOp == 0 || UxtOp == ARM::tUXTB || UxtOp == ARM::tUXTH) && 1738 "ARMv8-M.baseline does not have t2UXTB/t2UXTH"); 1739 assert((UxtOp == 0 || ARM::tGPRRegClass.contains(DesiredReg)) && 1740 "DesiredReg used for UXT op must be tGPR"); 1741 } 1742 1743 MachineFunction *MF = MBB.getParent(); 1744 auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 1745 auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 1746 auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 1747 1748 MF->insert(++MBB.getIterator(), LoadCmpBB); 1749 MF->insert(++LoadCmpBB->getIterator(), StoreBB); 1750 MF->insert(++StoreBB->getIterator(), DoneBB); 1751 1752 if (UxtOp) { 1753 MachineInstrBuilder MIB = 1754 BuildMI(MBB, MBBI, DL, TII->get(UxtOp), DesiredReg) 1755 .addReg(DesiredReg, RegState::Kill); 1756 if (!IsThumb) 1757 MIB.addImm(0); 1758 MIB.add(predOps(ARMCC::AL)); 1759 } 1760 1761 // .Lloadcmp: 1762 // ldrex rDest, [rAddr] 1763 // cmp rDest, rDesired 1764 // bne .Ldone 1765 1766 MachineInstrBuilder MIB; 1767 MIB = BuildMI(LoadCmpBB, DL, TII->get(LdrexOp), Dest.getReg()); 1768 MIB.addReg(AddrReg); 1769 if (LdrexOp == ARM::t2LDREX) 1770 MIB.addImm(0); // a 32-bit Thumb ldrex (only) allows an offset. 1771 MIB.add(predOps(ARMCC::AL)); 1772 1773 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr; 1774 BuildMI(LoadCmpBB, DL, TII->get(CMPrr)) 1775 .addReg(Dest.getReg(), getKillRegState(Dest.isDead())) 1776 .addReg(DesiredReg) 1777 .add(predOps(ARMCC::AL)); 1778 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc; 1779 BuildMI(LoadCmpBB, DL, TII->get(Bcc)) 1780 .addMBB(DoneBB) 1781 .addImm(ARMCC::NE) 1782 .addReg(ARM::CPSR, RegState::Kill); 1783 LoadCmpBB->addSuccessor(DoneBB); 1784 LoadCmpBB->addSuccessor(StoreBB); 1785 1786 // .Lstore: 1787 // strex rTempReg, rNew, [rAddr] 1788 // cmp rTempReg, #0 1789 // bne .Lloadcmp 1790 MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), TempReg) 1791 .addReg(NewReg) 1792 .addReg(AddrReg); 1793 if (StrexOp == ARM::t2STREX) 1794 MIB.addImm(0); // a 32-bit Thumb strex (only) allows an offset. 1795 MIB.add(predOps(ARMCC::AL)); 1796 1797 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri; 1798 BuildMI(StoreBB, DL, TII->get(CMPri)) 1799 .addReg(TempReg, RegState::Kill) 1800 .addImm(0) 1801 .add(predOps(ARMCC::AL)); 1802 BuildMI(StoreBB, DL, TII->get(Bcc)) 1803 .addMBB(LoadCmpBB) 1804 .addImm(ARMCC::NE) 1805 .addReg(ARM::CPSR, RegState::Kill); 1806 StoreBB->addSuccessor(LoadCmpBB); 1807 StoreBB->addSuccessor(DoneBB); 1808 1809 DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end()); 1810 DoneBB->transferSuccessors(&MBB); 1811 1812 MBB.addSuccessor(LoadCmpBB); 1813 1814 NextMBBI = MBB.end(); 1815 MI.eraseFromParent(); 1816 1817 // Recompute livein lists. 1818 LivePhysRegs LiveRegs; 1819 computeAndAddLiveIns(LiveRegs, *DoneBB); 1820 computeAndAddLiveIns(LiveRegs, *StoreBB); 1821 computeAndAddLiveIns(LiveRegs, *LoadCmpBB); 1822 // Do an extra pass around the loop to get loop carried registers right. 1823 StoreBB->clearLiveIns(); 1824 computeAndAddLiveIns(LiveRegs, *StoreBB); 1825 LoadCmpBB->clearLiveIns(); 1826 computeAndAddLiveIns(LiveRegs, *LoadCmpBB); 1827 1828 return true; 1829 } 1830 1831 /// ARM's ldrexd/strexd take a consecutive register pair (represented as a 1832 /// single GPRPair register), Thumb's take two separate registers so we need to 1833 /// extract the subregs from the pair. 1834 static void addExclusiveRegPair(MachineInstrBuilder &MIB, MachineOperand &Reg, 1835 unsigned Flags, bool IsThumb, 1836 const TargetRegisterInfo *TRI) { 1837 if (IsThumb) { 1838 Register RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0); 1839 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); 1840 MIB.addReg(RegLo, Flags); 1841 MIB.addReg(RegHi, Flags); 1842 } else 1843 MIB.addReg(Reg.getReg(), Flags); 1844 } 1845 1846 /// Expand a 64-bit CMP_SWAP to an ldrexd/strexd loop. 1847 bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB, 1848 MachineBasicBlock::iterator MBBI, 1849 MachineBasicBlock::iterator &NextMBBI) { 1850 bool IsThumb = STI->isThumb(); 1851 MachineInstr &MI = *MBBI; 1852 DebugLoc DL = MI.getDebugLoc(); 1853 MachineOperand &Dest = MI.getOperand(0); 1854 Register TempReg = MI.getOperand(1).getReg(); 1855 // Duplicating undef operands into 2 instructions does not guarantee the same 1856 // value on both; However undef should be replaced by xzr anyway. 1857 assert(!MI.getOperand(2).isUndef() && "cannot handle undef"); 1858 Register AddrReg = MI.getOperand(2).getReg(); 1859 Register DesiredReg = MI.getOperand(3).getReg(); 1860 MachineOperand New = MI.getOperand(4); 1861 New.setIsKill(false); 1862 1863 Register DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0); 1864 Register DestHi = TRI->getSubReg(Dest.getReg(), ARM::gsub_1); 1865 Register DesiredLo = TRI->getSubReg(DesiredReg, ARM::gsub_0); 1866 Register DesiredHi = TRI->getSubReg(DesiredReg, ARM::gsub_1); 1867 1868 MachineFunction *MF = MBB.getParent(); 1869 auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 1870 auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 1871 auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 1872 1873 MF->insert(++MBB.getIterator(), LoadCmpBB); 1874 MF->insert(++LoadCmpBB->getIterator(), StoreBB); 1875 MF->insert(++StoreBB->getIterator(), DoneBB); 1876 1877 // .Lloadcmp: 1878 // ldrexd rDestLo, rDestHi, [rAddr] 1879 // cmp rDestLo, rDesiredLo 1880 // sbcs dead rTempReg, rDestHi, rDesiredHi 1881 // bne .Ldone 1882 unsigned LDREXD = IsThumb ? ARM::t2LDREXD : ARM::LDREXD; 1883 MachineInstrBuilder MIB; 1884 MIB = BuildMI(LoadCmpBB, DL, TII->get(LDREXD)); 1885 addExclusiveRegPair(MIB, Dest, RegState::Define, IsThumb, TRI); 1886 MIB.addReg(AddrReg).add(predOps(ARMCC::AL)); 1887 1888 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr; 1889 BuildMI(LoadCmpBB, DL, TII->get(CMPrr)) 1890 .addReg(DestLo, getKillRegState(Dest.isDead())) 1891 .addReg(DesiredLo) 1892 .add(predOps(ARMCC::AL)); 1893 1894 BuildMI(LoadCmpBB, DL, TII->get(CMPrr)) 1895 .addReg(DestHi, getKillRegState(Dest.isDead())) 1896 .addReg(DesiredHi) 1897 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill); 1898 1899 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc; 1900 BuildMI(LoadCmpBB, DL, TII->get(Bcc)) 1901 .addMBB(DoneBB) 1902 .addImm(ARMCC::NE) 1903 .addReg(ARM::CPSR, RegState::Kill); 1904 LoadCmpBB->addSuccessor(DoneBB); 1905 LoadCmpBB->addSuccessor(StoreBB); 1906 1907 // .Lstore: 1908 // strexd rTempReg, rNewLo, rNewHi, [rAddr] 1909 // cmp rTempReg, #0 1910 // bne .Lloadcmp 1911 unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD; 1912 MIB = BuildMI(StoreBB, DL, TII->get(STREXD), TempReg); 1913 unsigned Flags = getKillRegState(New.isDead()); 1914 addExclusiveRegPair(MIB, New, Flags, IsThumb, TRI); 1915 MIB.addReg(AddrReg).add(predOps(ARMCC::AL)); 1916 1917 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri; 1918 BuildMI(StoreBB, DL, TII->get(CMPri)) 1919 .addReg(TempReg, RegState::Kill) 1920 .addImm(0) 1921 .add(predOps(ARMCC::AL)); 1922 BuildMI(StoreBB, DL, TII->get(Bcc)) 1923 .addMBB(LoadCmpBB) 1924 .addImm(ARMCC::NE) 1925 .addReg(ARM::CPSR, RegState::Kill); 1926 StoreBB->addSuccessor(LoadCmpBB); 1927 StoreBB->addSuccessor(DoneBB); 1928 1929 DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end()); 1930 DoneBB->transferSuccessors(&MBB); 1931 1932 MBB.addSuccessor(LoadCmpBB); 1933 1934 NextMBBI = MBB.end(); 1935 MI.eraseFromParent(); 1936 1937 // Recompute livein lists. 1938 LivePhysRegs LiveRegs; 1939 computeAndAddLiveIns(LiveRegs, *DoneBB); 1940 computeAndAddLiveIns(LiveRegs, *StoreBB); 1941 computeAndAddLiveIns(LiveRegs, *LoadCmpBB); 1942 // Do an extra pass around the loop to get loop carried registers right. 1943 StoreBB->clearLiveIns(); 1944 computeAndAddLiveIns(LiveRegs, *StoreBB); 1945 LoadCmpBB->clearLiveIns(); 1946 computeAndAddLiveIns(LiveRegs, *LoadCmpBB); 1947 1948 return true; 1949 } 1950 1951 static void CMSEPushCalleeSaves(const TargetInstrInfo &TII, 1952 MachineBasicBlock &MBB, 1953 MachineBasicBlock::iterator MBBI, int JumpReg, 1954 const LivePhysRegs &LiveRegs, bool Thumb1Only) { 1955 const DebugLoc &DL = MBBI->getDebugLoc(); 1956 if (Thumb1Only) { // push Lo and Hi regs separately 1957 MachineInstrBuilder PushMIB = 1958 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL)); 1959 for (int Reg = ARM::R4; Reg < ARM::R8; ++Reg) { 1960 PushMIB.addReg( 1961 Reg, Reg == JumpReg || LiveRegs.contains(Reg) ? 0 : RegState::Undef); 1962 } 1963 1964 // Thumb1 can only tPUSH low regs, so we copy the high regs to the low 1965 // regs that we just saved and push the low regs again, taking care to 1966 // not clobber JumpReg. If JumpReg is one of the low registers, push first 1967 // the values of r9-r11, and then r8. That would leave them ordered in 1968 // memory, and allow us to later pop them with a single instructions. 1969 // FIXME: Could also use any of r0-r3 that are free (including in the 1970 // first PUSH above). 1971 for (int LoReg = ARM::R7, HiReg = ARM::R11; LoReg >= ARM::R4; --LoReg) { 1972 if (JumpReg == LoReg) 1973 continue; 1974 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg) 1975 .addReg(HiReg, LiveRegs.contains(HiReg) ? 0 : RegState::Undef) 1976 .add(predOps(ARMCC::AL)); 1977 --HiReg; 1978 } 1979 MachineInstrBuilder PushMIB2 = 1980 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL)); 1981 for (int Reg = ARM::R4; Reg < ARM::R8; ++Reg) { 1982 if (Reg == JumpReg) 1983 continue; 1984 PushMIB2.addReg(Reg, RegState::Kill); 1985 } 1986 1987 // If we couldn't use a low register for temporary storage (because it was 1988 // the JumpReg), use r4 or r5, whichever is not JumpReg. It has already been 1989 // saved. 1990 if (JumpReg >= ARM::R4 && JumpReg <= ARM::R7) { 1991 int LoReg = JumpReg == ARM::R4 ? ARM::R5 : ARM::R4; 1992 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg) 1993 .addReg(ARM::R8, LiveRegs.contains(ARM::R8) ? 0 : RegState::Undef) 1994 .add(predOps(ARMCC::AL)); 1995 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)) 1996 .add(predOps(ARMCC::AL)) 1997 .addReg(LoReg, RegState::Kill); 1998 } 1999 } else { // push Lo and Hi registers with a single instruction 2000 MachineInstrBuilder PushMIB = 2001 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2STMDB_UPD), ARM::SP) 2002 .addReg(ARM::SP) 2003 .add(predOps(ARMCC::AL)); 2004 for (int Reg = ARM::R4; Reg < ARM::R12; ++Reg) { 2005 PushMIB.addReg( 2006 Reg, Reg == JumpReg || LiveRegs.contains(Reg) ? 0 : RegState::Undef); 2007 } 2008 } 2009 } 2010 2011 static void CMSEPopCalleeSaves(const TargetInstrInfo &TII, 2012 MachineBasicBlock &MBB, 2013 MachineBasicBlock::iterator MBBI, int JumpReg, 2014 bool Thumb1Only) { 2015 const DebugLoc &DL = MBBI->getDebugLoc(); 2016 if (Thumb1Only) { 2017 MachineInstrBuilder PopMIB = 2018 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL)); 2019 for (int R = 0; R < 4; ++R) { 2020 PopMIB.addReg(ARM::R4 + R, RegState::Define); 2021 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), ARM::R8 + R) 2022 .addReg(ARM::R4 + R, RegState::Kill) 2023 .add(predOps(ARMCC::AL)); 2024 } 2025 MachineInstrBuilder PopMIB2 = 2026 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL)); 2027 for (int R = 0; R < 4; ++R) 2028 PopMIB2.addReg(ARM::R4 + R, RegState::Define); 2029 } else { // pop Lo and Hi registers with a single instruction 2030 MachineInstrBuilder PopMIB = 2031 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2LDMIA_UPD), ARM::SP) 2032 .addReg(ARM::SP) 2033 .add(predOps(ARMCC::AL)); 2034 for (int Reg = ARM::R4; Reg < ARM::R12; ++Reg) 2035 PopMIB.addReg(Reg, RegState::Define); 2036 } 2037 } 2038 2039 bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, 2040 MachineBasicBlock::iterator MBBI, 2041 MachineBasicBlock::iterator &NextMBBI) { 2042 MachineInstr &MI = *MBBI; 2043 unsigned Opcode = MI.getOpcode(); 2044 switch (Opcode) { 2045 default: 2046 return false; 2047 2048 case ARM::VBSPd: 2049 case ARM::VBSPq: { 2050 Register DstReg = MI.getOperand(0).getReg(); 2051 if (DstReg == MI.getOperand(3).getReg()) { 2052 // Expand to VBIT 2053 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBITd : ARM::VBITq; 2054 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)) 2055 .add(MI.getOperand(0)) 2056 .add(MI.getOperand(3)) 2057 .add(MI.getOperand(2)) 2058 .add(MI.getOperand(1)) 2059 .addImm(MI.getOperand(4).getImm()) 2060 .add(MI.getOperand(5)); 2061 } else if (DstReg == MI.getOperand(2).getReg()) { 2062 // Expand to VBIF 2063 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBIFd : ARM::VBIFq; 2064 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)) 2065 .add(MI.getOperand(0)) 2066 .add(MI.getOperand(2)) 2067 .add(MI.getOperand(3)) 2068 .add(MI.getOperand(1)) 2069 .addImm(MI.getOperand(4).getImm()) 2070 .add(MI.getOperand(5)); 2071 } else { 2072 // Expand to VBSL 2073 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBSLd : ARM::VBSLq; 2074 if (DstReg == MI.getOperand(1).getReg()) { 2075 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)) 2076 .add(MI.getOperand(0)) 2077 .add(MI.getOperand(1)) 2078 .add(MI.getOperand(2)) 2079 .add(MI.getOperand(3)) 2080 .addImm(MI.getOperand(4).getImm()) 2081 .add(MI.getOperand(5)); 2082 } else { 2083 // Use move to satisfy constraints 2084 unsigned MoveOpc = Opcode == ARM::VBSPd ? ARM::VORRd : ARM::VORRq; 2085 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(MoveOpc)) 2086 .addReg(DstReg, 2087 RegState::Define | 2088 getRenamableRegState(MI.getOperand(0).isRenamable())) 2089 .add(MI.getOperand(1)) 2090 .add(MI.getOperand(1)) 2091 .addImm(MI.getOperand(4).getImm()) 2092 .add(MI.getOperand(5)); 2093 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)) 2094 .add(MI.getOperand(0)) 2095 .addReg(DstReg, 2096 RegState::Kill | 2097 getRenamableRegState(MI.getOperand(0).isRenamable())) 2098 .add(MI.getOperand(2)) 2099 .add(MI.getOperand(3)) 2100 .addImm(MI.getOperand(4).getImm()) 2101 .add(MI.getOperand(5)); 2102 } 2103 } 2104 MI.eraseFromParent(); 2105 return true; 2106 } 2107 2108 case ARM::TCRETURNdi: 2109 case ARM::TCRETURNri: { 2110 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 2111 if (MBBI->getOpcode() == ARM::SEH_EpilogEnd) 2112 MBBI--; 2113 if (MBBI->getOpcode() == ARM::SEH_Nop_Ret) 2114 MBBI--; 2115 assert(MBBI->isReturn() && 2116 "Can only insert epilog into returning blocks"); 2117 unsigned RetOpcode = MBBI->getOpcode(); 2118 DebugLoc dl = MBBI->getDebugLoc(); 2119 const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>( 2120 MBB.getParent()->getSubtarget().getInstrInfo()); 2121 2122 // Tail call return: adjust the stack pointer and jump to callee. 2123 MBBI = MBB.getLastNonDebugInstr(); 2124 if (MBBI->getOpcode() == ARM::SEH_EpilogEnd) 2125 MBBI--; 2126 if (MBBI->getOpcode() == ARM::SEH_Nop_Ret) 2127 MBBI--; 2128 MachineOperand &JumpTarget = MBBI->getOperand(0); 2129 2130 // Jump to label or value in register. 2131 if (RetOpcode == ARM::TCRETURNdi) { 2132 MachineFunction *MF = MBB.getParent(); 2133 bool NeedsWinCFI = MF->getTarget().getMCAsmInfo()->usesWindowsCFI() && 2134 MF->getFunction().needsUnwindTableEntry(); 2135 unsigned TCOpcode = 2136 STI->isThumb() 2137 ? ((STI->isTargetMachO() || NeedsWinCFI) ? ARM::tTAILJMPd 2138 : ARM::tTAILJMPdND) 2139 : ARM::TAILJMPd; 2140 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode)); 2141 if (JumpTarget.isGlobal()) 2142 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), 2143 JumpTarget.getTargetFlags()); 2144 else { 2145 assert(JumpTarget.isSymbol()); 2146 MIB.addExternalSymbol(JumpTarget.getSymbolName(), 2147 JumpTarget.getTargetFlags()); 2148 } 2149 2150 // Add the default predicate in Thumb mode. 2151 if (STI->isThumb()) 2152 MIB.add(predOps(ARMCC::AL)); 2153 } else if (RetOpcode == ARM::TCRETURNri) { 2154 unsigned Opcode = 2155 STI->isThumb() ? ARM::tTAILJMPr 2156 : (STI->hasV4TOps() ? ARM::TAILJMPr : ARM::TAILJMPr4); 2157 BuildMI(MBB, MBBI, dl, 2158 TII.get(Opcode)) 2159 .addReg(JumpTarget.getReg(), RegState::Kill); 2160 } 2161 2162 auto NewMI = std::prev(MBBI); 2163 for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i) 2164 NewMI->addOperand(MBBI->getOperand(i)); 2165 2166 2167 // Update call site info and delete the pseudo instruction TCRETURN. 2168 if (MI.isCandidateForCallSiteEntry()) 2169 MI.getMF()->moveCallSiteInfo(&MI, &*NewMI); 2170 MBB.erase(MBBI); 2171 2172 MBBI = NewMI; 2173 return true; 2174 } 2175 case ARM::tBXNS_RET: { 2176 // For v8.0-M.Main we need to authenticate LR before clearing FPRs, which 2177 // uses R12 as a scratch register. 2178 if (!STI->hasV8_1MMainlineOps() && AFI->shouldSignReturnAddress()) 2179 BuildMI(MBB, MBBI, DebugLoc(), TII->get(ARM::t2AUT)); 2180 2181 MachineBasicBlock &AfterBB = CMSEClearFPRegs(MBB, MBBI); 2182 2183 if (STI->hasV8_1MMainlineOps()) { 2184 // Restore the non-secure floating point context. 2185 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), 2186 TII->get(ARM::VLDR_FPCXTNS_post), ARM::SP) 2187 .addReg(ARM::SP) 2188 .addImm(4) 2189 .add(predOps(ARMCC::AL)); 2190 2191 if (AFI->shouldSignReturnAddress()) 2192 BuildMI(AfterBB, AfterBB.end(), DebugLoc(), TII->get(ARM::t2AUT)); 2193 } 2194 2195 // Clear all GPR that are not a use of the return instruction. 2196 assert(llvm::all_of(MBBI->operands(), [](const MachineOperand &Op) { 2197 return !Op.isReg() || Op.getReg() != ARM::R12; 2198 })); 2199 SmallVector<unsigned, 5> ClearRegs; 2200 determineGPRegsToClear( 2201 *MBBI, {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12}, ClearRegs); 2202 CMSEClearGPRegs(AfterBB, AfterBB.end(), MBBI->getDebugLoc(), ClearRegs, 2203 ARM::LR); 2204 2205 MachineInstrBuilder NewMI = 2206 BuildMI(AfterBB, AfterBB.end(), MBBI->getDebugLoc(), 2207 TII->get(ARM::tBXNS)) 2208 .addReg(ARM::LR) 2209 .add(predOps(ARMCC::AL)); 2210 for (const MachineOperand &Op : MI.operands()) 2211 NewMI->addOperand(Op); 2212 MI.eraseFromParent(); 2213 return true; 2214 } 2215 case ARM::tBLXNS_CALL: { 2216 DebugLoc DL = MBBI->getDebugLoc(); 2217 Register JumpReg = MBBI->getOperand(0).getReg(); 2218 2219 // Figure out which registers are live at the point immediately before the 2220 // call. When we indiscriminately push a set of registers, the live 2221 // registers are added as ordinary use operands, whereas dead registers 2222 // are "undef". 2223 LivePhysRegs LiveRegs(*TRI); 2224 LiveRegs.addLiveOuts(MBB); 2225 for (const MachineInstr &MI : make_range(MBB.rbegin(), MBBI.getReverse())) 2226 LiveRegs.stepBackward(MI); 2227 LiveRegs.stepBackward(*MBBI); 2228 2229 CMSEPushCalleeSaves(*TII, MBB, MBBI, JumpReg, LiveRegs, 2230 AFI->isThumb1OnlyFunction()); 2231 2232 SmallVector<unsigned, 16> ClearRegs; 2233 determineGPRegsToClear(*MBBI, 2234 {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, 2235 ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, 2236 ARM::R10, ARM::R11, ARM::R12}, 2237 ClearRegs); 2238 auto OriginalClearRegs = ClearRegs; 2239 2240 // Get the first cleared register as a scratch (to use later with tBIC). 2241 // We need to use the first so we can ensure it is a low register. 2242 unsigned ScratchReg = ClearRegs.front(); 2243 2244 // Clear LSB of JumpReg 2245 if (AFI->isThumb2Function()) { 2246 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), JumpReg) 2247 .addReg(JumpReg) 2248 .addImm(1) 2249 .add(predOps(ARMCC::AL)) 2250 .add(condCodeOp()); 2251 } else { 2252 // We need to use an extra register to cope with 8M Baseline, 2253 // since we have saved all of the registers we are ok to trash a non 2254 // argument register here. 2255 BuildMI(MBB, MBBI, DL, TII->get(ARM::tMOVi8), ScratchReg) 2256 .add(condCodeOp()) 2257 .addImm(1) 2258 .add(predOps(ARMCC::AL)); 2259 BuildMI(MBB, MBBI, DL, TII->get(ARM::tBIC), JumpReg) 2260 .addReg(ARM::CPSR, RegState::Define) 2261 .addReg(JumpReg) 2262 .addReg(ScratchReg) 2263 .add(predOps(ARMCC::AL)); 2264 } 2265 2266 CMSESaveClearFPRegs(MBB, MBBI, DL, LiveRegs, 2267 ClearRegs); // save+clear FP regs with ClearRegs 2268 CMSEClearGPRegs(MBB, MBBI, DL, ClearRegs, JumpReg); 2269 2270 const MachineInstrBuilder NewCall = 2271 BuildMI(MBB, MBBI, DL, TII->get(ARM::tBLXNSr)) 2272 .add(predOps(ARMCC::AL)) 2273 .addReg(JumpReg, RegState::Kill); 2274 2275 for (const MachineOperand &MO : llvm::drop_begin(MI.operands())) 2276 NewCall->addOperand(MO); 2277 if (MI.isCandidateForCallSiteEntry()) 2278 MI.getMF()->moveCallSiteInfo(&MI, NewCall.getInstr()); 2279 2280 CMSERestoreFPRegs(MBB, MBBI, DL, OriginalClearRegs); // restore FP registers 2281 2282 CMSEPopCalleeSaves(*TII, MBB, MBBI, JumpReg, AFI->isThumb1OnlyFunction()); 2283 2284 MI.eraseFromParent(); 2285 return true; 2286 } 2287 case ARM::VMOVHcc: 2288 case ARM::VMOVScc: 2289 case ARM::VMOVDcc: { 2290 unsigned newOpc = Opcode != ARM::VMOVDcc ? ARM::VMOVS : ARM::VMOVD; 2291 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc), 2292 MI.getOperand(1).getReg()) 2293 .add(MI.getOperand(2)) 2294 .addImm(MI.getOperand(3).getImm()) // 'pred' 2295 .add(MI.getOperand(4)) 2296 .add(makeImplicit(MI.getOperand(1))); 2297 2298 MI.eraseFromParent(); 2299 return true; 2300 } 2301 case ARM::t2MOVCCr: 2302 case ARM::MOVCCr: { 2303 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr; 2304 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), 2305 MI.getOperand(1).getReg()) 2306 .add(MI.getOperand(2)) 2307 .addImm(MI.getOperand(3).getImm()) // 'pred' 2308 .add(MI.getOperand(4)) 2309 .add(condCodeOp()) // 's' bit 2310 .add(makeImplicit(MI.getOperand(1))); 2311 2312 MI.eraseFromParent(); 2313 return true; 2314 } 2315 case ARM::MOVCCsi: { 2316 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), 2317 (MI.getOperand(1).getReg())) 2318 .add(MI.getOperand(2)) 2319 .addImm(MI.getOperand(3).getImm()) 2320 .addImm(MI.getOperand(4).getImm()) // 'pred' 2321 .add(MI.getOperand(5)) 2322 .add(condCodeOp()) // 's' bit 2323 .add(makeImplicit(MI.getOperand(1))); 2324 2325 MI.eraseFromParent(); 2326 return true; 2327 } 2328 case ARM::MOVCCsr: { 2329 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr), 2330 (MI.getOperand(1).getReg())) 2331 .add(MI.getOperand(2)) 2332 .add(MI.getOperand(3)) 2333 .addImm(MI.getOperand(4).getImm()) 2334 .addImm(MI.getOperand(5).getImm()) // 'pred' 2335 .add(MI.getOperand(6)) 2336 .add(condCodeOp()) // 's' bit 2337 .add(makeImplicit(MI.getOperand(1))); 2338 2339 MI.eraseFromParent(); 2340 return true; 2341 } 2342 case ARM::t2MOVCCi16: 2343 case ARM::MOVCCi16: { 2344 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16; 2345 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), 2346 MI.getOperand(1).getReg()) 2347 .addImm(MI.getOperand(2).getImm()) 2348 .addImm(MI.getOperand(3).getImm()) // 'pred' 2349 .add(MI.getOperand(4)) 2350 .add(makeImplicit(MI.getOperand(1))); 2351 MI.eraseFromParent(); 2352 return true; 2353 } 2354 case ARM::t2MOVCCi: 2355 case ARM::MOVCCi: { 2356 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi; 2357 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), 2358 MI.getOperand(1).getReg()) 2359 .addImm(MI.getOperand(2).getImm()) 2360 .addImm(MI.getOperand(3).getImm()) // 'pred' 2361 .add(MI.getOperand(4)) 2362 .add(condCodeOp()) // 's' bit 2363 .add(makeImplicit(MI.getOperand(1))); 2364 2365 MI.eraseFromParent(); 2366 return true; 2367 } 2368 case ARM::t2MVNCCi: 2369 case ARM::MVNCCi: { 2370 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi; 2371 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), 2372 MI.getOperand(1).getReg()) 2373 .addImm(MI.getOperand(2).getImm()) 2374 .addImm(MI.getOperand(3).getImm()) // 'pred' 2375 .add(MI.getOperand(4)) 2376 .add(condCodeOp()) // 's' bit 2377 .add(makeImplicit(MI.getOperand(1))); 2378 2379 MI.eraseFromParent(); 2380 return true; 2381 } 2382 case ARM::t2MOVCClsl: 2383 case ARM::t2MOVCClsr: 2384 case ARM::t2MOVCCasr: 2385 case ARM::t2MOVCCror: { 2386 unsigned NewOpc; 2387 switch (Opcode) { 2388 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break; 2389 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break; 2390 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break; 2391 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break; 2392 default: llvm_unreachable("unexpeced conditional move"); 2393 } 2394 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), 2395 MI.getOperand(1).getReg()) 2396 .add(MI.getOperand(2)) 2397 .addImm(MI.getOperand(3).getImm()) 2398 .addImm(MI.getOperand(4).getImm()) // 'pred' 2399 .add(MI.getOperand(5)) 2400 .add(condCodeOp()) // 's' bit 2401 .add(makeImplicit(MI.getOperand(1))); 2402 MI.eraseFromParent(); 2403 return true; 2404 } 2405 case ARM::Int_eh_sjlj_dispatchsetup: { 2406 MachineFunction &MF = *MI.getParent()->getParent(); 2407 const ARMBaseInstrInfo *AII = 2408 static_cast<const ARMBaseInstrInfo*>(TII); 2409 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo(); 2410 // For functions using a base pointer, we rematerialize it (via the frame 2411 // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it 2412 // for us. Otherwise, expand to nothing. 2413 if (RI.hasBasePointer(MF)) { 2414 int32_t NumBytes = AFI->getFramePtrSpillOffset(); 2415 Register FramePtr = RI.getFrameRegister(MF); 2416 assert(MF.getSubtarget().getFrameLowering()->hasFP(MF) && 2417 "base pointer without frame pointer?"); 2418 2419 if (AFI->isThumb2Function()) { 2420 emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 2421 FramePtr, -NumBytes, ARMCC::AL, 0, *TII); 2422 } else if (AFI->isThumbFunction()) { 2423 emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 2424 FramePtr, -NumBytes, *TII, RI); 2425 } else { 2426 emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 2427 FramePtr, -NumBytes, ARMCC::AL, 0, 2428 *TII); 2429 } 2430 // If there's dynamic realignment, adjust for it. 2431 if (RI.hasStackRealignment(MF)) { 2432 MachineFrameInfo &MFI = MF.getFrameInfo(); 2433 Align MaxAlign = MFI.getMaxAlign(); 2434 assert (!AFI->isThumb1OnlyFunction()); 2435 // Emit bic r6, r6, MaxAlign 2436 assert(MaxAlign <= Align(256) && 2437 "The BIC instruction cannot encode " 2438 "immediates larger than 256 with all lower " 2439 "bits set."); 2440 unsigned bicOpc = AFI->isThumbFunction() ? 2441 ARM::t2BICri : ARM::BICri; 2442 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(bicOpc), ARM::R6) 2443 .addReg(ARM::R6, RegState::Kill) 2444 .addImm(MaxAlign.value() - 1) 2445 .add(predOps(ARMCC::AL)) 2446 .add(condCodeOp()); 2447 } 2448 } 2449 MI.eraseFromParent(); 2450 return true; 2451 } 2452 2453 case ARM::MOVsrl_flag: 2454 case ARM::MOVsra_flag: { 2455 // These are just fancy MOVs instructions. 2456 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), 2457 MI.getOperand(0).getReg()) 2458 .add(MI.getOperand(1)) 2459 .addImm(ARM_AM::getSORegOpc( 2460 (Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr : ARM_AM::asr), 1)) 2461 .add(predOps(ARMCC::AL)) 2462 .addReg(ARM::CPSR, RegState::Define); 2463 MI.eraseFromParent(); 2464 return true; 2465 } 2466 case ARM::RRX: { 2467 // This encodes as "MOVs Rd, Rm, rrx 2468 MachineInstrBuilder MIB = 2469 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), 2470 MI.getOperand(0).getReg()) 2471 .add(MI.getOperand(1)) 2472 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0)) 2473 .add(predOps(ARMCC::AL)) 2474 .add(condCodeOp()); 2475 TransferImpOps(MI, MIB, MIB); 2476 MI.eraseFromParent(); 2477 return true; 2478 } 2479 case ARM::tTPsoft: 2480 case ARM::TPsoft: { 2481 const bool Thumb = Opcode == ARM::tTPsoft; 2482 2483 MachineInstrBuilder MIB; 2484 MachineFunction *MF = MBB.getParent(); 2485 if (STI->genLongCalls()) { 2486 MachineConstantPool *MCP = MF->getConstantPool(); 2487 unsigned PCLabelID = AFI->createPICLabelUId(); 2488 MachineConstantPoolValue *CPV = 2489 ARMConstantPoolSymbol::Create(MF->getFunction().getContext(), 2490 "__aeabi_read_tp", PCLabelID, 0); 2491 Register Reg = MI.getOperand(0).getReg(); 2492 MIB = 2493 BuildMI(MBB, MBBI, MI.getDebugLoc(), 2494 TII->get(Thumb ? ARM::tLDRpci : ARM::LDRi12), Reg) 2495 .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, Align(4))); 2496 if (!Thumb) 2497 MIB.addImm(0); 2498 MIB.add(predOps(ARMCC::AL)); 2499 2500 MIB = 2501 BuildMI(MBB, MBBI, MI.getDebugLoc(), 2502 TII->get(Thumb ? gettBLXrOpcode(*MF) : getBLXOpcode(*MF))); 2503 if (Thumb) 2504 MIB.add(predOps(ARMCC::AL)); 2505 MIB.addReg(Reg, RegState::Kill); 2506 } else { 2507 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 2508 TII->get(Thumb ? ARM::tBL : ARM::BL)); 2509 if (Thumb) 2510 MIB.add(predOps(ARMCC::AL)); 2511 MIB.addExternalSymbol("__aeabi_read_tp", 0); 2512 } 2513 2514 MIB.cloneMemRefs(MI); 2515 TransferImpOps(MI, MIB, MIB); 2516 // Update the call site info. 2517 if (MI.isCandidateForCallSiteEntry()) 2518 MF->moveCallSiteInfo(&MI, &*MIB); 2519 MI.eraseFromParent(); 2520 return true; 2521 } 2522 case ARM::tLDRpci_pic: 2523 case ARM::t2LDRpci_pic: { 2524 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic) 2525 ? ARM::tLDRpci : ARM::t2LDRpci; 2526 Register DstReg = MI.getOperand(0).getReg(); 2527 bool DstIsDead = MI.getOperand(0).isDead(); 2528 MachineInstrBuilder MIB1 = 2529 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewLdOpc), DstReg) 2530 .add(MI.getOperand(1)) 2531 .add(predOps(ARMCC::AL)); 2532 MIB1.cloneMemRefs(MI); 2533 MachineInstrBuilder MIB2 = 2534 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPICADD)) 2535 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 2536 .addReg(DstReg) 2537 .add(MI.getOperand(2)); 2538 TransferImpOps(MI, MIB1, MIB2); 2539 MI.eraseFromParent(); 2540 return true; 2541 } 2542 2543 case ARM::LDRLIT_ga_abs: 2544 case ARM::LDRLIT_ga_pcrel: 2545 case ARM::LDRLIT_ga_pcrel_ldr: 2546 case ARM::tLDRLIT_ga_abs: 2547 case ARM::t2LDRLIT_ga_pcrel: 2548 case ARM::tLDRLIT_ga_pcrel: { 2549 Register DstReg = MI.getOperand(0).getReg(); 2550 bool DstIsDead = MI.getOperand(0).isDead(); 2551 const MachineOperand &MO1 = MI.getOperand(1); 2552 auto Flags = MO1.getTargetFlags(); 2553 const GlobalValue *GV = MO1.getGlobal(); 2554 bool IsARM = Opcode != ARM::tLDRLIT_ga_pcrel && 2555 Opcode != ARM::tLDRLIT_ga_abs && 2556 Opcode != ARM::t2LDRLIT_ga_pcrel; 2557 bool IsPIC = 2558 Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs; 2559 unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci; 2560 if (Opcode == ARM::t2LDRLIT_ga_pcrel) 2561 LDRLITOpc = ARM::t2LDRpci; 2562 unsigned PICAddOpc = 2563 IsARM 2564 ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) 2565 : ARM::tPICADD; 2566 2567 // We need a new const-pool entry to load from. 2568 MachineConstantPool *MCP = MBB.getParent()->getConstantPool(); 2569 unsigned ARMPCLabelIndex = 0; 2570 MachineConstantPoolValue *CPV; 2571 2572 if (IsPIC) { 2573 unsigned PCAdj = IsARM ? 8 : 4; 2574 auto Modifier = (Flags & ARMII::MO_GOT) 2575 ? ARMCP::GOT_PREL 2576 : ARMCP::no_modifier; 2577 ARMPCLabelIndex = AFI->createPICLabelUId(); 2578 CPV = ARMConstantPoolConstant::Create( 2579 GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj, Modifier, 2580 /*AddCurrentAddr*/ Modifier == ARMCP::GOT_PREL); 2581 } else 2582 CPV = ARMConstantPoolConstant::Create(GV, ARMCP::no_modifier); 2583 2584 MachineInstrBuilder MIB = 2585 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LDRLITOpc), DstReg) 2586 .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, Align(4))); 2587 if (IsARM) 2588 MIB.addImm(0); 2589 MIB.add(predOps(ARMCC::AL)); 2590 2591 if (IsPIC) { 2592 MachineInstrBuilder MIB = 2593 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(PICAddOpc)) 2594 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 2595 .addReg(DstReg) 2596 .addImm(ARMPCLabelIndex); 2597 2598 if (IsARM) 2599 MIB.add(predOps(ARMCC::AL)); 2600 } 2601 2602 MI.eraseFromParent(); 2603 return true; 2604 } 2605 case ARM::MOV_ga_pcrel: 2606 case ARM::MOV_ga_pcrel_ldr: 2607 case ARM::t2MOV_ga_pcrel: { 2608 // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode. 2609 unsigned LabelId = AFI->createPICLabelUId(); 2610 Register DstReg = MI.getOperand(0).getReg(); 2611 bool DstIsDead = MI.getOperand(0).isDead(); 2612 const MachineOperand &MO1 = MI.getOperand(1); 2613 const GlobalValue *GV = MO1.getGlobal(); 2614 unsigned TF = MO1.getTargetFlags(); 2615 bool isARM = Opcode != ARM::t2MOV_ga_pcrel; 2616 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel; 2617 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel; 2618 unsigned LO16TF = TF | ARMII::MO_LO16; 2619 unsigned HI16TF = TF | ARMII::MO_HI16; 2620 unsigned PICAddOpc = isARM 2621 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) 2622 : ARM::tPICADD; 2623 MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 2624 TII->get(LO16Opc), DstReg) 2625 .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF) 2626 .addImm(LabelId); 2627 2628 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc), DstReg) 2629 .addReg(DstReg) 2630 .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF) 2631 .addImm(LabelId); 2632 2633 MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 2634 TII->get(PICAddOpc)) 2635 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 2636 .addReg(DstReg).addImm(LabelId); 2637 if (isARM) { 2638 MIB3.add(predOps(ARMCC::AL)); 2639 if (Opcode == ARM::MOV_ga_pcrel_ldr) 2640 MIB3.cloneMemRefs(MI); 2641 } 2642 TransferImpOps(MI, MIB1, MIB3); 2643 MI.eraseFromParent(); 2644 return true; 2645 } 2646 2647 case ARM::MOVi32imm: 2648 case ARM::MOVCCi32imm: 2649 case ARM::t2MOVi32imm: 2650 case ARM::t2MOVCCi32imm: 2651 ExpandMOV32BitImm(MBB, MBBI); 2652 return true; 2653 2654 case ARM::SUBS_PC_LR: { 2655 MachineInstrBuilder MIB = 2656 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC) 2657 .addReg(ARM::LR) 2658 .add(MI.getOperand(0)) 2659 .add(MI.getOperand(1)) 2660 .add(MI.getOperand(2)) 2661 .addReg(ARM::CPSR, RegState::Undef); 2662 TransferImpOps(MI, MIB, MIB); 2663 MI.eraseFromParent(); 2664 return true; 2665 } 2666 case ARM::VLDMQIA: { 2667 unsigned NewOpc = ARM::VLDMDIA; 2668 MachineInstrBuilder MIB = 2669 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 2670 unsigned OpIdx = 0; 2671 2672 // Grab the Q register destination. 2673 bool DstIsDead = MI.getOperand(OpIdx).isDead(); 2674 Register DstReg = MI.getOperand(OpIdx++).getReg(); 2675 2676 // Copy the source register. 2677 MIB.add(MI.getOperand(OpIdx++)); 2678 2679 // Copy the predicate operands. 2680 MIB.add(MI.getOperand(OpIdx++)); 2681 MIB.add(MI.getOperand(OpIdx++)); 2682 2683 // Add the destination operands (D subregs). 2684 Register D0 = TRI->getSubReg(DstReg, ARM::dsub_0); 2685 Register D1 = TRI->getSubReg(DstReg, ARM::dsub_1); 2686 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) 2687 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 2688 2689 // Add an implicit def for the super-register. 2690 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 2691 TransferImpOps(MI, MIB, MIB); 2692 MIB.cloneMemRefs(MI); 2693 MI.eraseFromParent(); 2694 return true; 2695 } 2696 2697 case ARM::VSTMQIA: { 2698 unsigned NewOpc = ARM::VSTMDIA; 2699 MachineInstrBuilder MIB = 2700 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 2701 unsigned OpIdx = 0; 2702 2703 // Grab the Q register source. 2704 bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 2705 Register SrcReg = MI.getOperand(OpIdx++).getReg(); 2706 2707 // Copy the destination register. 2708 MachineOperand Dst(MI.getOperand(OpIdx++)); 2709 MIB.add(Dst); 2710 2711 // Copy the predicate operands. 2712 MIB.add(MI.getOperand(OpIdx++)); 2713 MIB.add(MI.getOperand(OpIdx++)); 2714 2715 // Add the source operands (D subregs). 2716 Register D0 = TRI->getSubReg(SrcReg, ARM::dsub_0); 2717 Register D1 = TRI->getSubReg(SrcReg, ARM::dsub_1); 2718 MIB.addReg(D0, SrcIsKill ? RegState::Kill : 0) 2719 .addReg(D1, SrcIsKill ? RegState::Kill : 0); 2720 2721 if (SrcIsKill) // Add an implicit kill for the Q register. 2722 MIB->addRegisterKilled(SrcReg, TRI, true); 2723 2724 TransferImpOps(MI, MIB, MIB); 2725 MIB.cloneMemRefs(MI); 2726 MI.eraseFromParent(); 2727 return true; 2728 } 2729 2730 case ARM::VLD2q8Pseudo: 2731 case ARM::VLD2q16Pseudo: 2732 case ARM::VLD2q32Pseudo: 2733 case ARM::VLD2q8PseudoWB_fixed: 2734 case ARM::VLD2q16PseudoWB_fixed: 2735 case ARM::VLD2q32PseudoWB_fixed: 2736 case ARM::VLD2q8PseudoWB_register: 2737 case ARM::VLD2q16PseudoWB_register: 2738 case ARM::VLD2q32PseudoWB_register: 2739 case ARM::VLD3d8Pseudo: 2740 case ARM::VLD3d16Pseudo: 2741 case ARM::VLD3d32Pseudo: 2742 case ARM::VLD1d8TPseudo: 2743 case ARM::VLD1d8TPseudoWB_fixed: 2744 case ARM::VLD1d8TPseudoWB_register: 2745 case ARM::VLD1d16TPseudo: 2746 case ARM::VLD1d16TPseudoWB_fixed: 2747 case ARM::VLD1d16TPseudoWB_register: 2748 case ARM::VLD1d32TPseudo: 2749 case ARM::VLD1d32TPseudoWB_fixed: 2750 case ARM::VLD1d32TPseudoWB_register: 2751 case ARM::VLD1d64TPseudo: 2752 case ARM::VLD1d64TPseudoWB_fixed: 2753 case ARM::VLD1d64TPseudoWB_register: 2754 case ARM::VLD3d8Pseudo_UPD: 2755 case ARM::VLD3d16Pseudo_UPD: 2756 case ARM::VLD3d32Pseudo_UPD: 2757 case ARM::VLD3q8Pseudo_UPD: 2758 case ARM::VLD3q16Pseudo_UPD: 2759 case ARM::VLD3q32Pseudo_UPD: 2760 case ARM::VLD3q8oddPseudo: 2761 case ARM::VLD3q16oddPseudo: 2762 case ARM::VLD3q32oddPseudo: 2763 case ARM::VLD3q8oddPseudo_UPD: 2764 case ARM::VLD3q16oddPseudo_UPD: 2765 case ARM::VLD3q32oddPseudo_UPD: 2766 case ARM::VLD4d8Pseudo: 2767 case ARM::VLD4d16Pseudo: 2768 case ARM::VLD4d32Pseudo: 2769 case ARM::VLD1d8QPseudo: 2770 case ARM::VLD1d8QPseudoWB_fixed: 2771 case ARM::VLD1d8QPseudoWB_register: 2772 case ARM::VLD1d16QPseudo: 2773 case ARM::VLD1d16QPseudoWB_fixed: 2774 case ARM::VLD1d16QPseudoWB_register: 2775 case ARM::VLD1d32QPseudo: 2776 case ARM::VLD1d32QPseudoWB_fixed: 2777 case ARM::VLD1d32QPseudoWB_register: 2778 case ARM::VLD1d64QPseudo: 2779 case ARM::VLD1d64QPseudoWB_fixed: 2780 case ARM::VLD1d64QPseudoWB_register: 2781 case ARM::VLD1q8HighQPseudo: 2782 case ARM::VLD1q8HighQPseudo_UPD: 2783 case ARM::VLD1q8LowQPseudo_UPD: 2784 case ARM::VLD1q8HighTPseudo: 2785 case ARM::VLD1q8HighTPseudo_UPD: 2786 case ARM::VLD1q8LowTPseudo_UPD: 2787 case ARM::VLD1q16HighQPseudo: 2788 case ARM::VLD1q16HighQPseudo_UPD: 2789 case ARM::VLD1q16LowQPseudo_UPD: 2790 case ARM::VLD1q16HighTPseudo: 2791 case ARM::VLD1q16HighTPseudo_UPD: 2792 case ARM::VLD1q16LowTPseudo_UPD: 2793 case ARM::VLD1q32HighQPseudo: 2794 case ARM::VLD1q32HighQPseudo_UPD: 2795 case ARM::VLD1q32LowQPseudo_UPD: 2796 case ARM::VLD1q32HighTPseudo: 2797 case ARM::VLD1q32HighTPseudo_UPD: 2798 case ARM::VLD1q32LowTPseudo_UPD: 2799 case ARM::VLD1q64HighQPseudo: 2800 case ARM::VLD1q64HighQPseudo_UPD: 2801 case ARM::VLD1q64LowQPseudo_UPD: 2802 case ARM::VLD1q64HighTPseudo: 2803 case ARM::VLD1q64HighTPseudo_UPD: 2804 case ARM::VLD1q64LowTPseudo_UPD: 2805 case ARM::VLD4d8Pseudo_UPD: 2806 case ARM::VLD4d16Pseudo_UPD: 2807 case ARM::VLD4d32Pseudo_UPD: 2808 case ARM::VLD4q8Pseudo_UPD: 2809 case ARM::VLD4q16Pseudo_UPD: 2810 case ARM::VLD4q32Pseudo_UPD: 2811 case ARM::VLD4q8oddPseudo: 2812 case ARM::VLD4q16oddPseudo: 2813 case ARM::VLD4q32oddPseudo: 2814 case ARM::VLD4q8oddPseudo_UPD: 2815 case ARM::VLD4q16oddPseudo_UPD: 2816 case ARM::VLD4q32oddPseudo_UPD: 2817 case ARM::VLD3DUPd8Pseudo: 2818 case ARM::VLD3DUPd16Pseudo: 2819 case ARM::VLD3DUPd32Pseudo: 2820 case ARM::VLD3DUPd8Pseudo_UPD: 2821 case ARM::VLD3DUPd16Pseudo_UPD: 2822 case ARM::VLD3DUPd32Pseudo_UPD: 2823 case ARM::VLD4DUPd8Pseudo: 2824 case ARM::VLD4DUPd16Pseudo: 2825 case ARM::VLD4DUPd32Pseudo: 2826 case ARM::VLD4DUPd8Pseudo_UPD: 2827 case ARM::VLD4DUPd16Pseudo_UPD: 2828 case ARM::VLD4DUPd32Pseudo_UPD: 2829 case ARM::VLD2DUPq8EvenPseudo: 2830 case ARM::VLD2DUPq8OddPseudo: 2831 case ARM::VLD2DUPq16EvenPseudo: 2832 case ARM::VLD2DUPq16OddPseudo: 2833 case ARM::VLD2DUPq32EvenPseudo: 2834 case ARM::VLD2DUPq32OddPseudo: 2835 case ARM::VLD2DUPq8OddPseudoWB_fixed: 2836 case ARM::VLD2DUPq8OddPseudoWB_register: 2837 case ARM::VLD2DUPq16OddPseudoWB_fixed: 2838 case ARM::VLD2DUPq16OddPseudoWB_register: 2839 case ARM::VLD2DUPq32OddPseudoWB_fixed: 2840 case ARM::VLD2DUPq32OddPseudoWB_register: 2841 case ARM::VLD3DUPq8EvenPseudo: 2842 case ARM::VLD3DUPq8OddPseudo: 2843 case ARM::VLD3DUPq16EvenPseudo: 2844 case ARM::VLD3DUPq16OddPseudo: 2845 case ARM::VLD3DUPq32EvenPseudo: 2846 case ARM::VLD3DUPq32OddPseudo: 2847 case ARM::VLD3DUPq8OddPseudo_UPD: 2848 case ARM::VLD3DUPq16OddPseudo_UPD: 2849 case ARM::VLD3DUPq32OddPseudo_UPD: 2850 case ARM::VLD4DUPq8EvenPseudo: 2851 case ARM::VLD4DUPq8OddPseudo: 2852 case ARM::VLD4DUPq16EvenPseudo: 2853 case ARM::VLD4DUPq16OddPseudo: 2854 case ARM::VLD4DUPq32EvenPseudo: 2855 case ARM::VLD4DUPq32OddPseudo: 2856 case ARM::VLD4DUPq8OddPseudo_UPD: 2857 case ARM::VLD4DUPq16OddPseudo_UPD: 2858 case ARM::VLD4DUPq32OddPseudo_UPD: 2859 ExpandVLD(MBBI); 2860 return true; 2861 2862 case ARM::VST2q8Pseudo: 2863 case ARM::VST2q16Pseudo: 2864 case ARM::VST2q32Pseudo: 2865 case ARM::VST2q8PseudoWB_fixed: 2866 case ARM::VST2q16PseudoWB_fixed: 2867 case ARM::VST2q32PseudoWB_fixed: 2868 case ARM::VST2q8PseudoWB_register: 2869 case ARM::VST2q16PseudoWB_register: 2870 case ARM::VST2q32PseudoWB_register: 2871 case ARM::VST3d8Pseudo: 2872 case ARM::VST3d16Pseudo: 2873 case ARM::VST3d32Pseudo: 2874 case ARM::VST1d8TPseudo: 2875 case ARM::VST1d8TPseudoWB_fixed: 2876 case ARM::VST1d8TPseudoWB_register: 2877 case ARM::VST1d16TPseudo: 2878 case ARM::VST1d16TPseudoWB_fixed: 2879 case ARM::VST1d16TPseudoWB_register: 2880 case ARM::VST1d32TPseudo: 2881 case ARM::VST1d32TPseudoWB_fixed: 2882 case ARM::VST1d32TPseudoWB_register: 2883 case ARM::VST1d64TPseudo: 2884 case ARM::VST1d64TPseudoWB_fixed: 2885 case ARM::VST1d64TPseudoWB_register: 2886 case ARM::VST3d8Pseudo_UPD: 2887 case ARM::VST3d16Pseudo_UPD: 2888 case ARM::VST3d32Pseudo_UPD: 2889 case ARM::VST3q8Pseudo_UPD: 2890 case ARM::VST3q16Pseudo_UPD: 2891 case ARM::VST3q32Pseudo_UPD: 2892 case ARM::VST3q8oddPseudo: 2893 case ARM::VST3q16oddPseudo: 2894 case ARM::VST3q32oddPseudo: 2895 case ARM::VST3q8oddPseudo_UPD: 2896 case ARM::VST3q16oddPseudo_UPD: 2897 case ARM::VST3q32oddPseudo_UPD: 2898 case ARM::VST4d8Pseudo: 2899 case ARM::VST4d16Pseudo: 2900 case ARM::VST4d32Pseudo: 2901 case ARM::VST1d8QPseudo: 2902 case ARM::VST1d8QPseudoWB_fixed: 2903 case ARM::VST1d8QPseudoWB_register: 2904 case ARM::VST1d16QPseudo: 2905 case ARM::VST1d16QPseudoWB_fixed: 2906 case ARM::VST1d16QPseudoWB_register: 2907 case ARM::VST1d32QPseudo: 2908 case ARM::VST1d32QPseudoWB_fixed: 2909 case ARM::VST1d32QPseudoWB_register: 2910 case ARM::VST1d64QPseudo: 2911 case ARM::VST1d64QPseudoWB_fixed: 2912 case ARM::VST1d64QPseudoWB_register: 2913 case ARM::VST4d8Pseudo_UPD: 2914 case ARM::VST4d16Pseudo_UPD: 2915 case ARM::VST4d32Pseudo_UPD: 2916 case ARM::VST1q8HighQPseudo: 2917 case ARM::VST1q8LowQPseudo_UPD: 2918 case ARM::VST1q8HighTPseudo: 2919 case ARM::VST1q8LowTPseudo_UPD: 2920 case ARM::VST1q16HighQPseudo: 2921 case ARM::VST1q16LowQPseudo_UPD: 2922 case ARM::VST1q16HighTPseudo: 2923 case ARM::VST1q16LowTPseudo_UPD: 2924 case ARM::VST1q32HighQPseudo: 2925 case ARM::VST1q32LowQPseudo_UPD: 2926 case ARM::VST1q32HighTPseudo: 2927 case ARM::VST1q32LowTPseudo_UPD: 2928 case ARM::VST1q64HighQPseudo: 2929 case ARM::VST1q64LowQPseudo_UPD: 2930 case ARM::VST1q64HighTPseudo: 2931 case ARM::VST1q64LowTPseudo_UPD: 2932 case ARM::VST1q8HighTPseudo_UPD: 2933 case ARM::VST1q16HighTPseudo_UPD: 2934 case ARM::VST1q32HighTPseudo_UPD: 2935 case ARM::VST1q64HighTPseudo_UPD: 2936 case ARM::VST1q8HighQPseudo_UPD: 2937 case ARM::VST1q16HighQPseudo_UPD: 2938 case ARM::VST1q32HighQPseudo_UPD: 2939 case ARM::VST1q64HighQPseudo_UPD: 2940 case ARM::VST4q8Pseudo_UPD: 2941 case ARM::VST4q16Pseudo_UPD: 2942 case ARM::VST4q32Pseudo_UPD: 2943 case ARM::VST4q8oddPseudo: 2944 case ARM::VST4q16oddPseudo: 2945 case ARM::VST4q32oddPseudo: 2946 case ARM::VST4q8oddPseudo_UPD: 2947 case ARM::VST4q16oddPseudo_UPD: 2948 case ARM::VST4q32oddPseudo_UPD: 2949 ExpandVST(MBBI); 2950 return true; 2951 2952 case ARM::VLD1LNq8Pseudo: 2953 case ARM::VLD1LNq16Pseudo: 2954 case ARM::VLD1LNq32Pseudo: 2955 case ARM::VLD1LNq8Pseudo_UPD: 2956 case ARM::VLD1LNq16Pseudo_UPD: 2957 case ARM::VLD1LNq32Pseudo_UPD: 2958 case ARM::VLD2LNd8Pseudo: 2959 case ARM::VLD2LNd16Pseudo: 2960 case ARM::VLD2LNd32Pseudo: 2961 case ARM::VLD2LNq16Pseudo: 2962 case ARM::VLD2LNq32Pseudo: 2963 case ARM::VLD2LNd8Pseudo_UPD: 2964 case ARM::VLD2LNd16Pseudo_UPD: 2965 case ARM::VLD2LNd32Pseudo_UPD: 2966 case ARM::VLD2LNq16Pseudo_UPD: 2967 case ARM::VLD2LNq32Pseudo_UPD: 2968 case ARM::VLD3LNd8Pseudo: 2969 case ARM::VLD3LNd16Pseudo: 2970 case ARM::VLD3LNd32Pseudo: 2971 case ARM::VLD3LNq16Pseudo: 2972 case ARM::VLD3LNq32Pseudo: 2973 case ARM::VLD3LNd8Pseudo_UPD: 2974 case ARM::VLD3LNd16Pseudo_UPD: 2975 case ARM::VLD3LNd32Pseudo_UPD: 2976 case ARM::VLD3LNq16Pseudo_UPD: 2977 case ARM::VLD3LNq32Pseudo_UPD: 2978 case ARM::VLD4LNd8Pseudo: 2979 case ARM::VLD4LNd16Pseudo: 2980 case ARM::VLD4LNd32Pseudo: 2981 case ARM::VLD4LNq16Pseudo: 2982 case ARM::VLD4LNq32Pseudo: 2983 case ARM::VLD4LNd8Pseudo_UPD: 2984 case ARM::VLD4LNd16Pseudo_UPD: 2985 case ARM::VLD4LNd32Pseudo_UPD: 2986 case ARM::VLD4LNq16Pseudo_UPD: 2987 case ARM::VLD4LNq32Pseudo_UPD: 2988 case ARM::VST1LNq8Pseudo: 2989 case ARM::VST1LNq16Pseudo: 2990 case ARM::VST1LNq32Pseudo: 2991 case ARM::VST1LNq8Pseudo_UPD: 2992 case ARM::VST1LNq16Pseudo_UPD: 2993 case ARM::VST1LNq32Pseudo_UPD: 2994 case ARM::VST2LNd8Pseudo: 2995 case ARM::VST2LNd16Pseudo: 2996 case ARM::VST2LNd32Pseudo: 2997 case ARM::VST2LNq16Pseudo: 2998 case ARM::VST2LNq32Pseudo: 2999 case ARM::VST2LNd8Pseudo_UPD: 3000 case ARM::VST2LNd16Pseudo_UPD: 3001 case ARM::VST2LNd32Pseudo_UPD: 3002 case ARM::VST2LNq16Pseudo_UPD: 3003 case ARM::VST2LNq32Pseudo_UPD: 3004 case ARM::VST3LNd8Pseudo: 3005 case ARM::VST3LNd16Pseudo: 3006 case ARM::VST3LNd32Pseudo: 3007 case ARM::VST3LNq16Pseudo: 3008 case ARM::VST3LNq32Pseudo: 3009 case ARM::VST3LNd8Pseudo_UPD: 3010 case ARM::VST3LNd16Pseudo_UPD: 3011 case ARM::VST3LNd32Pseudo_UPD: 3012 case ARM::VST3LNq16Pseudo_UPD: 3013 case ARM::VST3LNq32Pseudo_UPD: 3014 case ARM::VST4LNd8Pseudo: 3015 case ARM::VST4LNd16Pseudo: 3016 case ARM::VST4LNd32Pseudo: 3017 case ARM::VST4LNq16Pseudo: 3018 case ARM::VST4LNq32Pseudo: 3019 case ARM::VST4LNd8Pseudo_UPD: 3020 case ARM::VST4LNd16Pseudo_UPD: 3021 case ARM::VST4LNd32Pseudo_UPD: 3022 case ARM::VST4LNq16Pseudo_UPD: 3023 case ARM::VST4LNq32Pseudo_UPD: 3024 ExpandLaneOp(MBBI); 3025 return true; 3026 3027 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true; 3028 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true; 3029 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true; 3030 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true; 3031 3032 case ARM::MQQPRLoad: 3033 case ARM::MQQPRStore: 3034 case ARM::MQQQQPRLoad: 3035 case ARM::MQQQQPRStore: 3036 ExpandMQQPRLoadStore(MBBI); 3037 return true; 3038 3039 case ARM::tCMP_SWAP_8: 3040 assert(STI->isThumb()); 3041 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXB, ARM::t2STREXB, ARM::tUXTB, 3042 NextMBBI); 3043 case ARM::tCMP_SWAP_16: 3044 assert(STI->isThumb()); 3045 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXH, ARM::t2STREXH, ARM::tUXTH, 3046 NextMBBI); 3047 3048 case ARM::CMP_SWAP_8: 3049 assert(!STI->isThumb()); 3050 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXB, ARM::STREXB, ARM::UXTB, 3051 NextMBBI); 3052 case ARM::CMP_SWAP_16: 3053 assert(!STI->isThumb()); 3054 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXH, ARM::STREXH, ARM::UXTH, 3055 NextMBBI); 3056 case ARM::CMP_SWAP_32: 3057 if (STI->isThumb()) 3058 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREX, ARM::t2STREX, 0, 3059 NextMBBI); 3060 else 3061 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI); 3062 3063 case ARM::CMP_SWAP_64: 3064 return ExpandCMP_SWAP_64(MBB, MBBI, NextMBBI); 3065 3066 case ARM::tBL_PUSHLR: 3067 case ARM::BL_PUSHLR: { 3068 const bool Thumb = Opcode == ARM::tBL_PUSHLR; 3069 Register Reg = MI.getOperand(0).getReg(); 3070 assert(Reg == ARM::LR && "expect LR register!"); 3071 MachineInstrBuilder MIB; 3072 if (Thumb) { 3073 // push {lr} 3074 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPUSH)) 3075 .add(predOps(ARMCC::AL)) 3076 .addReg(Reg); 3077 3078 // bl __gnu_mcount_nc 3079 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tBL)); 3080 } else { 3081 // stmdb sp!, {lr} 3082 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::STMDB_UPD)) 3083 .addReg(ARM::SP, RegState::Define) 3084 .addReg(ARM::SP) 3085 .add(predOps(ARMCC::AL)) 3086 .addReg(Reg); 3087 3088 // bl __gnu_mcount_nc 3089 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::BL)); 3090 } 3091 MIB.cloneMemRefs(MI); 3092 for (const MachineOperand &MO : llvm::drop_begin(MI.operands())) 3093 MIB.add(MO); 3094 MI.eraseFromParent(); 3095 return true; 3096 } 3097 case ARM::t2CALL_BTI: { 3098 MachineFunction &MF = *MI.getMF(); 3099 MachineInstrBuilder MIB = 3100 BuildMI(MF, MI.getDebugLoc(), TII->get(ARM::tBL)); 3101 MIB.cloneMemRefs(MI); 3102 for (unsigned i = 0; i < MI.getNumOperands(); ++i) 3103 MIB.add(MI.getOperand(i)); 3104 if (MI.isCandidateForCallSiteEntry()) 3105 MF.moveCallSiteInfo(&MI, MIB.getInstr()); 3106 MIBundleBuilder Bundler(MBB, MI); 3107 Bundler.append(MIB); 3108 Bundler.append(BuildMI(MF, MI.getDebugLoc(), TII->get(ARM::t2BTI))); 3109 finalizeBundle(MBB, Bundler.begin(), Bundler.end()); 3110 MI.eraseFromParent(); 3111 return true; 3112 } 3113 case ARM::LOADDUAL: 3114 case ARM::STOREDUAL: { 3115 Register PairReg = MI.getOperand(0).getReg(); 3116 3117 MachineInstrBuilder MIB = 3118 BuildMI(MBB, MBBI, MI.getDebugLoc(), 3119 TII->get(Opcode == ARM::LOADDUAL ? ARM::LDRD : ARM::STRD)) 3120 .addReg(TRI->getSubReg(PairReg, ARM::gsub_0), 3121 Opcode == ARM::LOADDUAL ? RegState::Define : 0) 3122 .addReg(TRI->getSubReg(PairReg, ARM::gsub_1), 3123 Opcode == ARM::LOADDUAL ? RegState::Define : 0); 3124 for (const MachineOperand &MO : llvm::drop_begin(MI.operands())) 3125 MIB.add(MO); 3126 MIB.add(predOps(ARMCC::AL)); 3127 MIB.cloneMemRefs(MI); 3128 MI.eraseFromParent(); 3129 return true; 3130 } 3131 } 3132 } 3133 3134 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { 3135 bool Modified = false; 3136 3137 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); 3138 while (MBBI != E) { 3139 MachineBasicBlock::iterator NMBBI = std::next(MBBI); 3140 Modified |= ExpandMI(MBB, MBBI, NMBBI); 3141 MBBI = NMBBI; 3142 } 3143 3144 return Modified; 3145 } 3146 3147 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) { 3148 STI = &MF.getSubtarget<ARMSubtarget>(); 3149 TII = STI->getInstrInfo(); 3150 TRI = STI->getRegisterInfo(); 3151 AFI = MF.getInfo<ARMFunctionInfo>(); 3152 3153 LLVM_DEBUG(dbgs() << "********** ARM EXPAND PSEUDO INSTRUCTIONS **********\n" 3154 << "********** Function: " << MF.getName() << '\n'); 3155 3156 bool Modified = false; 3157 for (MachineBasicBlock &MBB : MF) 3158 Modified |= ExpandMBB(MBB); 3159 if (VerifyARMPseudo) 3160 MF.verify(this, "After expanding ARM pseudo instructions."); 3161 3162 LLVM_DEBUG(dbgs() << "***************************************************\n"); 3163 return Modified; 3164 } 3165 3166 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction 3167 /// expansion pass. 3168 FunctionPass *llvm::createARMExpandPseudoPass() { 3169 return new ARMExpandPseudo(); 3170 } 3171