1 //===-- ARMInstrInfo.cpp - ARM Instruction Information --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the ARM implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARMInstrInfo.h"
14 #include "ARM.h"
15 #include "ARMConstantPoolValue.h"
16 #include "ARMMachineFunctionInfo.h"
17 #include "ARMTargetMachine.h"
18 #include "MCTargetDesc/ARMAddressingModes.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/LiveVariables.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/GlobalVariable.h"
27 #include "llvm/MC/MCAsmInfo.h"
28 #include "llvm/MC/MCInst.h"
29 using namespace llvm;
30 
31 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
32     : ARMBaseInstrInfo(STI), RI() {}
33 
34 /// Return the noop instruction to use for a noop.
35 MCInst ARMInstrInfo::getNop() const {
36   MCInst NopInst;
37   if (hasNOP()) {
38     NopInst.setOpcode(ARM::HINT);
39     NopInst.addOperand(MCOperand::createImm(0));
40     NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
41     NopInst.addOperand(MCOperand::createReg(0));
42   } else {
43     NopInst.setOpcode(ARM::MOVr);
44     NopInst.addOperand(MCOperand::createReg(ARM::R0));
45     NopInst.addOperand(MCOperand::createReg(ARM::R0));
46     NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
47     NopInst.addOperand(MCOperand::createReg(0));
48     NopInst.addOperand(MCOperand::createReg(0));
49   }
50   return NopInst;
51 }
52 
53 unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
54   switch (Opc) {
55   default:
56     break;
57   case ARM::LDR_PRE_IMM:
58   case ARM::LDR_PRE_REG:
59   case ARM::LDR_POST_IMM:
60   case ARM::LDR_POST_REG:
61     return ARM::LDRi12;
62   case ARM::LDRH_PRE:
63   case ARM::LDRH_POST:
64     return ARM::LDRH;
65   case ARM::LDRB_PRE_IMM:
66   case ARM::LDRB_PRE_REG:
67   case ARM::LDRB_POST_IMM:
68   case ARM::LDRB_POST_REG:
69     return ARM::LDRBi12;
70   case ARM::LDRSH_PRE:
71   case ARM::LDRSH_POST:
72     return ARM::LDRSH;
73   case ARM::LDRSB_PRE:
74   case ARM::LDRSB_POST:
75     return ARM::LDRSB;
76   case ARM::STR_PRE_IMM:
77   case ARM::STR_PRE_REG:
78   case ARM::STR_POST_IMM:
79   case ARM::STR_POST_REG:
80     return ARM::STRi12;
81   case ARM::STRH_PRE:
82   case ARM::STRH_POST:
83     return ARM::STRH;
84   case ARM::STRB_PRE_IMM:
85   case ARM::STRB_PRE_REG:
86   case ARM::STRB_POST_IMM:
87   case ARM::STRB_POST_REG:
88     return ARM::STRBi12;
89   }
90 
91   return 0;
92 }
93 
94 void ARMInstrInfo::expandLoadStackGuard(MachineBasicBlock::iterator MI) const {
95   MachineFunction &MF = *MI->getParent()->getParent();
96   const ARMSubtarget &Subtarget = MF.getSubtarget<ARMSubtarget>();
97   const TargetMachine &TM = MF.getTarget();
98 
99   if (!Subtarget.useMovt()) {
100     if (TM.isPositionIndependent())
101       expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_pcrel, ARM::LDRi12);
102     else
103       expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_abs, ARM::LDRi12);
104     return;
105   }
106 
107   if (!TM.isPositionIndependent()) {
108     expandLoadStackGuardBase(MI, ARM::MOVi32imm, ARM::LDRi12);
109     return;
110   }
111 
112   const GlobalValue *GV =
113       cast<GlobalValue>((*MI->memoperands_begin())->getValue());
114 
115   if (!Subtarget.isGVIndirectSymbol(GV)) {
116     expandLoadStackGuardBase(MI, ARM::MOV_ga_pcrel, ARM::LDRi12);
117     return;
118   }
119 
120   MachineBasicBlock &MBB = *MI->getParent();
121   DebugLoc DL = MI->getDebugLoc();
122   Register Reg = MI->getOperand(0).getReg();
123   MachineInstrBuilder MIB;
124 
125   MIB = BuildMI(MBB, MI, DL, get(ARM::MOV_ga_pcrel_ldr), Reg)
126             .addGlobalAddress(GV, 0, ARMII::MO_NONLAZY);
127   auto Flags = MachineMemOperand::MOLoad |
128                MachineMemOperand::MODereferenceable |
129                MachineMemOperand::MOInvariant;
130   MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
131       MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 4, Align(4));
132   MIB.addMemOperand(MMO);
133   BuildMI(MBB, MI, DL, get(ARM::LDRi12), Reg)
134       .addReg(Reg, RegState::Kill)
135       .addImm(0)
136       .cloneMemRefs(*MI)
137       .add(predOps(ARMCC::AL));
138 }
139