1 //===- ARMRegisterBankInfo.cpp -----------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements the targeting of the RegisterBankInfo class for ARM. 10 /// \todo This should be generated by TableGen. 11 //===----------------------------------------------------------------------===// 12 13 #include "ARMRegisterBankInfo.h" 14 #include "ARMInstrInfo.h" // For the register classes 15 #include "ARMSubtarget.h" 16 #include "llvm/CodeGen/GlobalISel/RegisterBank.h" 17 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" 18 #include "llvm/CodeGen/MachineRegisterInfo.h" 19 #include "llvm/CodeGen/TargetRegisterInfo.h" 20 21 #define GET_TARGET_REGBANK_IMPL 22 #include "ARMGenRegisterBank.inc" 23 24 using namespace llvm; 25 26 // FIXME: TableGen this. 27 // If it grows too much and TableGen still isn't ready to do the job, extract it 28 // into an ARMGenRegisterBankInfo.def (similar to AArch64). 29 namespace llvm { 30 namespace ARM { 31 enum PartialMappingIdx { 32 PMI_GPR, 33 PMI_SPR, 34 PMI_DPR, 35 PMI_Min = PMI_GPR, 36 }; 37 38 RegisterBankInfo::PartialMapping PartMappings[]{ 39 // GPR Partial Mapping 40 {0, 32, GPRRegBank}, 41 // SPR Partial Mapping 42 {0, 32, FPRRegBank}, 43 // DPR Partial Mapping 44 {0, 64, FPRRegBank}, 45 }; 46 47 #ifndef NDEBUG 48 static bool checkPartMapping(const RegisterBankInfo::PartialMapping &PM, 49 unsigned Start, unsigned Length, 50 unsigned RegBankID) { 51 return PM.StartIdx == Start && PM.Length == Length && 52 PM.RegBank->getID() == RegBankID; 53 } 54 55 static void checkPartialMappings() { 56 assert( 57 checkPartMapping(PartMappings[PMI_GPR - PMI_Min], 0, 32, GPRRegBankID) && 58 "Wrong mapping for GPR"); 59 assert( 60 checkPartMapping(PartMappings[PMI_SPR - PMI_Min], 0, 32, FPRRegBankID) && 61 "Wrong mapping for SPR"); 62 assert( 63 checkPartMapping(PartMappings[PMI_DPR - PMI_Min], 0, 64, FPRRegBankID) && 64 "Wrong mapping for DPR"); 65 } 66 #endif 67 68 enum ValueMappingIdx { 69 InvalidIdx = 0, 70 GPR3OpsIdx = 1, 71 SPR3OpsIdx = 4, 72 DPR3OpsIdx = 7, 73 }; 74 75 RegisterBankInfo::ValueMapping ValueMappings[] = { 76 // invalid 77 {nullptr, 0}, 78 // 3 ops in GPRs 79 {&PartMappings[PMI_GPR - PMI_Min], 1}, 80 {&PartMappings[PMI_GPR - PMI_Min], 1}, 81 {&PartMappings[PMI_GPR - PMI_Min], 1}, 82 // 3 ops in SPRs 83 {&PartMappings[PMI_SPR - PMI_Min], 1}, 84 {&PartMappings[PMI_SPR - PMI_Min], 1}, 85 {&PartMappings[PMI_SPR - PMI_Min], 1}, 86 // 3 ops in DPRs 87 {&PartMappings[PMI_DPR - PMI_Min], 1}, 88 {&PartMappings[PMI_DPR - PMI_Min], 1}, 89 {&PartMappings[PMI_DPR - PMI_Min], 1}}; 90 91 #ifndef NDEBUG 92 static bool checkValueMapping(const RegisterBankInfo::ValueMapping &VM, 93 RegisterBankInfo::PartialMapping *BreakDown) { 94 return VM.NumBreakDowns == 1 && VM.BreakDown == BreakDown; 95 } 96 97 static void checkValueMappings() { 98 assert(checkValueMapping(ValueMappings[GPR3OpsIdx], 99 &PartMappings[PMI_GPR - PMI_Min]) && 100 "Wrong value mapping for 3 GPR ops instruction"); 101 assert(checkValueMapping(ValueMappings[GPR3OpsIdx + 1], 102 &PartMappings[PMI_GPR - PMI_Min]) && 103 "Wrong value mapping for 3 GPR ops instruction"); 104 assert(checkValueMapping(ValueMappings[GPR3OpsIdx + 2], 105 &PartMappings[PMI_GPR - PMI_Min]) && 106 "Wrong value mapping for 3 GPR ops instruction"); 107 108 assert(checkValueMapping(ValueMappings[SPR3OpsIdx], 109 &PartMappings[PMI_SPR - PMI_Min]) && 110 "Wrong value mapping for 3 SPR ops instruction"); 111 assert(checkValueMapping(ValueMappings[SPR3OpsIdx + 1], 112 &PartMappings[PMI_SPR - PMI_Min]) && 113 "Wrong value mapping for 3 SPR ops instruction"); 114 assert(checkValueMapping(ValueMappings[SPR3OpsIdx + 2], 115 &PartMappings[PMI_SPR - PMI_Min]) && 116 "Wrong value mapping for 3 SPR ops instruction"); 117 118 assert(checkValueMapping(ValueMappings[DPR3OpsIdx], 119 &PartMappings[PMI_DPR - PMI_Min]) && 120 "Wrong value mapping for 3 DPR ops instruction"); 121 assert(checkValueMapping(ValueMappings[DPR3OpsIdx + 1], 122 &PartMappings[PMI_DPR - PMI_Min]) && 123 "Wrong value mapping for 3 DPR ops instruction"); 124 assert(checkValueMapping(ValueMappings[DPR3OpsIdx + 2], 125 &PartMappings[PMI_DPR - PMI_Min]) && 126 "Wrong value mapping for 3 DPR ops instruction"); 127 } 128 #endif 129 } // end namespace arm 130 } // end namespace llvm 131 132 ARMRegisterBankInfo::ARMRegisterBankInfo(const TargetRegisterInfo &TRI) 133 : ARMGenRegisterBankInfo() { 134 // We have only one set of register banks, whatever the subtarget 135 // is. Therefore, the initialization of the RegBanks table should be 136 // done only once. Indeed the table of all register banks 137 // (ARM::RegBanks) is unique in the compiler. At some point, it 138 // will get tablegen'ed and the whole constructor becomes empty. 139 static llvm::once_flag InitializeRegisterBankFlag; 140 141 static auto InitializeRegisterBankOnce = [&]() { 142 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID); 143 (void)RBGPR; 144 assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up"); 145 146 // Initialize the GPR bank. 147 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) && 148 "Subclass not added?"); 149 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) && 150 "Subclass not added?"); 151 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) && 152 "Subclass not added?"); 153 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) && 154 "Subclass not added?"); 155 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) && 156 "Subclass not added?"); 157 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) && 158 "Subclass not added?"); 159 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnoip_and_tcGPRRegClassID)) && 160 "Subclass not added?"); 161 assert(RBGPR.covers(*TRI.getRegClass( 162 ARM::tGPREven_and_GPRnoip_and_tcGPRRegClassID)) && 163 "Subclass not added?"); 164 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPROdd_and_tcGPRRegClassID)) && 165 "Subclass not added?"); 166 assert(RBGPR.getSize() == 32 && "GPRs should hold up to 32-bit"); 167 168 #ifndef NDEBUG 169 ARM::checkPartialMappings(); 170 ARM::checkValueMappings(); 171 #endif 172 }; 173 174 llvm::call_once(InitializeRegisterBankFlag, InitializeRegisterBankOnce); 175 } 176 177 const RegisterBank & 178 ARMRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, 179 LLT) const { 180 using namespace ARM; 181 182 switch (RC.getID()) { 183 case GPRRegClassID: 184 case GPRwithAPSRRegClassID: 185 case GPRnoipRegClassID: 186 case GPRnopcRegClassID: 187 case GPRnoip_and_GPRnopcRegClassID: 188 case rGPRRegClassID: 189 case GPRspRegClassID: 190 case GPRnoip_and_tcGPRRegClassID: 191 case tcGPRRegClassID: 192 case tGPRRegClassID: 193 case tGPREvenRegClassID: 194 case tGPROddRegClassID: 195 case tGPR_and_tGPREvenRegClassID: 196 case tGPR_and_tGPROddRegClassID: 197 case tGPREven_and_tcGPRRegClassID: 198 case tGPREven_and_GPRnoip_and_tcGPRRegClassID: 199 case tGPROdd_and_tcGPRRegClassID: 200 return getRegBank(ARM::GPRRegBankID); 201 case HPRRegClassID: 202 case SPR_8RegClassID: 203 case SPRRegClassID: 204 case DPR_8RegClassID: 205 case DPRRegClassID: 206 case QPRRegClassID: 207 return getRegBank(ARM::FPRRegBankID); 208 default: 209 llvm_unreachable("Unsupported register kind"); 210 } 211 212 llvm_unreachable("Switch should handle all register classes"); 213 } 214 215 const RegisterBankInfo::InstructionMapping & 216 ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { 217 auto Opc = MI.getOpcode(); 218 219 // Try the default logic for non-generic instructions that are either copies 220 // or already have some operands assigned to banks. 221 if (!isPreISelGenericOpcode(Opc) || Opc == TargetOpcode::G_PHI) { 222 const InstructionMapping &Mapping = getInstrMappingImpl(MI); 223 if (Mapping.isValid()) 224 return Mapping; 225 } 226 227 using namespace TargetOpcode; 228 229 const MachineFunction &MF = *MI.getParent()->getParent(); 230 const MachineRegisterInfo &MRI = MF.getRegInfo(); 231 unsigned NumOperands = MI.getNumOperands(); 232 const ValueMapping *OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx]; 233 234 switch (Opc) { 235 case G_ADD: 236 case G_SUB: { 237 // Integer operations where the source and destination are in the 238 // same register class. 239 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 240 OperandsMapping = Ty.getSizeInBits() == 64 241 ? &ARM::ValueMappings[ARM::DPR3OpsIdx] 242 : &ARM::ValueMappings[ARM::GPR3OpsIdx]; 243 break; 244 } 245 case G_MUL: 246 case G_AND: 247 case G_OR: 248 case G_XOR: 249 case G_LSHR: 250 case G_ASHR: 251 case G_SHL: 252 case G_SDIV: 253 case G_UDIV: 254 case G_SEXT: 255 case G_ZEXT: 256 case G_ANYEXT: 257 case G_PTR_ADD: 258 case G_INTTOPTR: 259 case G_PTRTOINT: 260 case G_CTLZ: 261 // FIXME: We're abusing the fact that everything lives in a GPR for now; in 262 // the real world we would use different mappings. 263 OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx]; 264 break; 265 case G_TRUNC: { 266 // In some cases we may end up with a G_TRUNC from a 64-bit value to a 267 // 32-bit value. This isn't a real floating point trunc (that would be a 268 // G_FPTRUNC). Instead it is an integer trunc in disguise, which can appear 269 // because the legalizer doesn't distinguish between integer and floating 270 // point values so it may leave some 64-bit integers un-narrowed. Until we 271 // have a more principled solution that doesn't let such things sneak all 272 // the way to this point, just map the source to a DPR and the destination 273 // to a GPR. 274 LLT LargeTy = MRI.getType(MI.getOperand(1).getReg()); 275 OperandsMapping = 276 LargeTy.getSizeInBits() <= 32 277 ? &ARM::ValueMappings[ARM::GPR3OpsIdx] 278 : getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], 279 &ARM::ValueMappings[ARM::DPR3OpsIdx]}); 280 break; 281 } 282 case G_LOAD: 283 case G_STORE: { 284 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 285 OperandsMapping = 286 Ty.getSizeInBits() == 64 287 ? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx], 288 &ARM::ValueMappings[ARM::GPR3OpsIdx]}) 289 : &ARM::ValueMappings[ARM::GPR3OpsIdx]; 290 break; 291 } 292 case G_FADD: 293 case G_FSUB: 294 case G_FMUL: 295 case G_FDIV: 296 case G_FNEG: { 297 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 298 OperandsMapping =Ty.getSizeInBits() == 64 299 ? &ARM::ValueMappings[ARM::DPR3OpsIdx] 300 : &ARM::ValueMappings[ARM::SPR3OpsIdx]; 301 break; 302 } 303 case G_FMA: { 304 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 305 OperandsMapping = 306 Ty.getSizeInBits() == 64 307 ? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx], 308 &ARM::ValueMappings[ARM::DPR3OpsIdx], 309 &ARM::ValueMappings[ARM::DPR3OpsIdx], 310 &ARM::ValueMappings[ARM::DPR3OpsIdx]}) 311 : getOperandsMapping({&ARM::ValueMappings[ARM::SPR3OpsIdx], 312 &ARM::ValueMappings[ARM::SPR3OpsIdx], 313 &ARM::ValueMappings[ARM::SPR3OpsIdx], 314 &ARM::ValueMappings[ARM::SPR3OpsIdx]}); 315 break; 316 } 317 case G_FPEXT: { 318 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); 319 LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); 320 if (ToTy.getSizeInBits() == 64 && FromTy.getSizeInBits() == 32) 321 OperandsMapping = 322 getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx], 323 &ARM::ValueMappings[ARM::SPR3OpsIdx]}); 324 break; 325 } 326 case G_FPTRUNC: { 327 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); 328 LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); 329 if (ToTy.getSizeInBits() == 32 && FromTy.getSizeInBits() == 64) 330 OperandsMapping = 331 getOperandsMapping({&ARM::ValueMappings[ARM::SPR3OpsIdx], 332 &ARM::ValueMappings[ARM::DPR3OpsIdx]}); 333 break; 334 } 335 case G_FPTOSI: 336 case G_FPTOUI: { 337 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); 338 LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); 339 if ((FromTy.getSizeInBits() == 32 || FromTy.getSizeInBits() == 64) && 340 ToTy.getSizeInBits() == 32) 341 OperandsMapping = 342 FromTy.getSizeInBits() == 64 343 ? getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], 344 &ARM::ValueMappings[ARM::DPR3OpsIdx]}) 345 : getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], 346 &ARM::ValueMappings[ARM::SPR3OpsIdx]}); 347 break; 348 } 349 case G_SITOFP: 350 case G_UITOFP: { 351 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); 352 LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); 353 if (FromTy.getSizeInBits() == 32 && 354 (ToTy.getSizeInBits() == 32 || ToTy.getSizeInBits() == 64)) 355 OperandsMapping = 356 ToTy.getSizeInBits() == 64 357 ? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx], 358 &ARM::ValueMappings[ARM::GPR3OpsIdx]}) 359 : getOperandsMapping({&ARM::ValueMappings[ARM::SPR3OpsIdx], 360 &ARM::ValueMappings[ARM::GPR3OpsIdx]}); 361 break; 362 } 363 case G_FCONSTANT: { 364 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 365 OperandsMapping = getOperandsMapping( 366 {Ty.getSizeInBits() == 64 ? &ARM::ValueMappings[ARM::DPR3OpsIdx] 367 : &ARM::ValueMappings[ARM::SPR3OpsIdx], 368 nullptr}); 369 break; 370 } 371 case G_CONSTANT: 372 case G_FRAME_INDEX: 373 case G_GLOBAL_VALUE: 374 OperandsMapping = 375 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr}); 376 break; 377 case G_SELECT: { 378 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 379 (void)Ty; 380 LLT Ty2 = MRI.getType(MI.getOperand(1).getReg()); 381 (void)Ty2; 382 assert(Ty.getSizeInBits() == 32 && "Unsupported size for G_SELECT"); 383 assert(Ty2.getSizeInBits() == 1 && "Unsupported size for G_SELECT"); 384 OperandsMapping = 385 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], 386 &ARM::ValueMappings[ARM::GPR3OpsIdx], 387 &ARM::ValueMappings[ARM::GPR3OpsIdx], 388 &ARM::ValueMappings[ARM::GPR3OpsIdx]}); 389 break; 390 } 391 case G_ICMP: { 392 LLT Ty2 = MRI.getType(MI.getOperand(2).getReg()); 393 (void)Ty2; 394 assert(Ty2.getSizeInBits() == 32 && "Unsupported size for G_ICMP"); 395 OperandsMapping = 396 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr, 397 &ARM::ValueMappings[ARM::GPR3OpsIdx], 398 &ARM::ValueMappings[ARM::GPR3OpsIdx]}); 399 break; 400 } 401 case G_FCMP: { 402 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 403 (void)Ty; 404 LLT Ty1 = MRI.getType(MI.getOperand(2).getReg()); 405 LLT Ty2 = MRI.getType(MI.getOperand(3).getReg()); 406 (void)Ty2; 407 assert(Ty.getSizeInBits() == 1 && "Unsupported size for G_FCMP"); 408 assert(Ty1.getSizeInBits() == Ty2.getSizeInBits() && 409 "Mismatched operand sizes for G_FCMP"); 410 411 unsigned Size = Ty1.getSizeInBits(); 412 assert((Size == 32 || Size == 64) && "Unsupported size for G_FCMP"); 413 414 auto FPRValueMapping = Size == 32 ? &ARM::ValueMappings[ARM::SPR3OpsIdx] 415 : &ARM::ValueMappings[ARM::DPR3OpsIdx]; 416 OperandsMapping = 417 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr, 418 FPRValueMapping, FPRValueMapping}); 419 break; 420 } 421 case G_MERGE_VALUES: { 422 // We only support G_MERGE_VALUES for creating a double precision floating 423 // point value out of two GPRs. 424 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 425 LLT Ty1 = MRI.getType(MI.getOperand(1).getReg()); 426 LLT Ty2 = MRI.getType(MI.getOperand(2).getReg()); 427 if (Ty.getSizeInBits() != 64 || Ty1.getSizeInBits() != 32 || 428 Ty2.getSizeInBits() != 32) 429 return getInvalidInstructionMapping(); 430 OperandsMapping = 431 getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx], 432 &ARM::ValueMappings[ARM::GPR3OpsIdx], 433 &ARM::ValueMappings[ARM::GPR3OpsIdx]}); 434 break; 435 } 436 case G_UNMERGE_VALUES: { 437 // We only support G_UNMERGE_VALUES for splitting a double precision 438 // floating point value into two GPRs. 439 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 440 LLT Ty1 = MRI.getType(MI.getOperand(1).getReg()); 441 LLT Ty2 = MRI.getType(MI.getOperand(2).getReg()); 442 if (Ty.getSizeInBits() != 32 || Ty1.getSizeInBits() != 32 || 443 Ty2.getSizeInBits() != 64) 444 return getInvalidInstructionMapping(); 445 OperandsMapping = 446 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], 447 &ARM::ValueMappings[ARM::GPR3OpsIdx], 448 &ARM::ValueMappings[ARM::DPR3OpsIdx]}); 449 break; 450 } 451 case G_BR: 452 OperandsMapping = getOperandsMapping({nullptr}); 453 break; 454 case G_BRCOND: 455 OperandsMapping = 456 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr}); 457 break; 458 case DBG_VALUE: { 459 SmallVector<const ValueMapping *, 4> OperandBanks(NumOperands); 460 const MachineOperand &MaybeReg = MI.getOperand(0); 461 if (MaybeReg.isReg() && MaybeReg.getReg()) { 462 unsigned Size = MRI.getType(MaybeReg.getReg()).getSizeInBits(); 463 if (Size > 32 && Size != 64) 464 return getInvalidInstructionMapping(); 465 OperandBanks[0] = Size == 64 ? &ARM::ValueMappings[ARM::DPR3OpsIdx] 466 : &ARM::ValueMappings[ARM::GPR3OpsIdx]; 467 } 468 OperandsMapping = getOperandsMapping(OperandBanks); 469 break; 470 } 471 default: 472 return getInvalidInstructionMapping(); 473 } 474 475 #ifndef NDEBUG 476 for (unsigned i = 0; i < NumOperands; i++) { 477 for (const auto &Mapping : OperandsMapping[i]) { 478 assert( 479 (Mapping.RegBank->getID() != ARM::FPRRegBankID || 480 MF.getSubtarget<ARMSubtarget>().hasVFP2Base()) && 481 "Trying to use floating point register bank on target without vfp"); 482 } 483 } 484 #endif 485 486 return getInstructionMapping(DefaultMappingID, /*Cost=*/1, OperandsMapping, 487 NumOperands); 488 } 489