1 //===- ARMRegisterBankInfo.cpp -----------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the targeting of the RegisterBankInfo class for ARM.
10 /// \todo This should be generated by TableGen.
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARMRegisterBankInfo.h"
14 #include "ARMInstrInfo.h" // For the register classes
15 #include "ARMSubtarget.h"
16 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
17 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/CodeGen/TargetRegisterInfo.h"
20 
21 #define GET_TARGET_REGBANK_IMPL
22 #include "ARMGenRegisterBank.inc"
23 
24 using namespace llvm;
25 
26 // FIXME: TableGen this.
27 // If it grows too much and TableGen still isn't ready to do the job, extract it
28 // into an ARMGenRegisterBankInfo.def (similar to AArch64).
29 namespace llvm {
30 namespace ARM {
31 enum PartialMappingIdx {
32   PMI_GPR,
33   PMI_SPR,
34   PMI_DPR,
35   PMI_Min = PMI_GPR,
36 };
37 
38 RegisterBankInfo::PartialMapping PartMappings[]{
39     // GPR Partial Mapping
40     {0, 32, GPRRegBank},
41     // SPR Partial Mapping
42     {0, 32, FPRRegBank},
43     // DPR Partial Mapping
44     {0, 64, FPRRegBank},
45 };
46 
47 #ifndef NDEBUG
48 static bool checkPartMapping(const RegisterBankInfo::PartialMapping &PM,
49                              unsigned Start, unsigned Length,
50                              unsigned RegBankID) {
51   return PM.StartIdx == Start && PM.Length == Length &&
52          PM.RegBank->getID() == RegBankID;
53 }
54 
55 static void checkPartialMappings() {
56   assert(
57       checkPartMapping(PartMappings[PMI_GPR - PMI_Min], 0, 32, GPRRegBankID) &&
58       "Wrong mapping for GPR");
59   assert(
60       checkPartMapping(PartMappings[PMI_SPR - PMI_Min], 0, 32, FPRRegBankID) &&
61       "Wrong mapping for SPR");
62   assert(
63       checkPartMapping(PartMappings[PMI_DPR - PMI_Min], 0, 64, FPRRegBankID) &&
64       "Wrong mapping for DPR");
65 }
66 #endif
67 
68 enum ValueMappingIdx {
69   InvalidIdx = 0,
70   GPR3OpsIdx = 1,
71   SPR3OpsIdx = 4,
72   DPR3OpsIdx = 7,
73 };
74 
75 RegisterBankInfo::ValueMapping ValueMappings[] = {
76     // invalid
77     {nullptr, 0},
78     // 3 ops in GPRs
79     {&PartMappings[PMI_GPR - PMI_Min], 1},
80     {&PartMappings[PMI_GPR - PMI_Min], 1},
81     {&PartMappings[PMI_GPR - PMI_Min], 1},
82     // 3 ops in SPRs
83     {&PartMappings[PMI_SPR - PMI_Min], 1},
84     {&PartMappings[PMI_SPR - PMI_Min], 1},
85     {&PartMappings[PMI_SPR - PMI_Min], 1},
86     // 3 ops in DPRs
87     {&PartMappings[PMI_DPR - PMI_Min], 1},
88     {&PartMappings[PMI_DPR - PMI_Min], 1},
89     {&PartMappings[PMI_DPR - PMI_Min], 1}};
90 
91 #ifndef NDEBUG
92 static bool checkValueMapping(const RegisterBankInfo::ValueMapping &VM,
93                               RegisterBankInfo::PartialMapping *BreakDown) {
94   return VM.NumBreakDowns == 1 && VM.BreakDown == BreakDown;
95 }
96 
97 static void checkValueMappings() {
98   assert(checkValueMapping(ValueMappings[GPR3OpsIdx],
99                            &PartMappings[PMI_GPR - PMI_Min]) &&
100          "Wrong value mapping for 3 GPR ops instruction");
101   assert(checkValueMapping(ValueMappings[GPR3OpsIdx + 1],
102                            &PartMappings[PMI_GPR - PMI_Min]) &&
103          "Wrong value mapping for 3 GPR ops instruction");
104   assert(checkValueMapping(ValueMappings[GPR3OpsIdx + 2],
105                            &PartMappings[PMI_GPR - PMI_Min]) &&
106          "Wrong value mapping for 3 GPR ops instruction");
107 
108   assert(checkValueMapping(ValueMappings[SPR3OpsIdx],
109                            &PartMappings[PMI_SPR - PMI_Min]) &&
110          "Wrong value mapping for 3 SPR ops instruction");
111   assert(checkValueMapping(ValueMappings[SPR3OpsIdx + 1],
112                            &PartMappings[PMI_SPR - PMI_Min]) &&
113          "Wrong value mapping for 3 SPR ops instruction");
114   assert(checkValueMapping(ValueMappings[SPR3OpsIdx + 2],
115                            &PartMappings[PMI_SPR - PMI_Min]) &&
116          "Wrong value mapping for 3 SPR ops instruction");
117 
118   assert(checkValueMapping(ValueMappings[DPR3OpsIdx],
119                            &PartMappings[PMI_DPR - PMI_Min]) &&
120          "Wrong value mapping for 3 DPR ops instruction");
121   assert(checkValueMapping(ValueMappings[DPR3OpsIdx + 1],
122                            &PartMappings[PMI_DPR - PMI_Min]) &&
123          "Wrong value mapping for 3 DPR ops instruction");
124   assert(checkValueMapping(ValueMappings[DPR3OpsIdx + 2],
125                            &PartMappings[PMI_DPR - PMI_Min]) &&
126          "Wrong value mapping for 3 DPR ops instruction");
127 }
128 #endif
129 } // end namespace arm
130 } // end namespace llvm
131 
132 ARMRegisterBankInfo::ARMRegisterBankInfo(const TargetRegisterInfo &TRI)
133     : ARMGenRegisterBankInfo() {
134   static bool AlreadyInit = false;
135   // We have only one set of register banks, whatever the subtarget
136   // is. Therefore, the initialization of the RegBanks table should be
137   // done only once. Indeed the table of all register banks
138   // (ARM::RegBanks) is unique in the compiler. At some point, it
139   // will get tablegen'ed and the whole constructor becomes empty.
140   if (AlreadyInit)
141     return;
142   AlreadyInit = true;
143 
144   const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID);
145   (void)RBGPR;
146   assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up");
147 
148   // Initialize the GPR bank.
149   assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) &&
150          "Subclass not added?");
151   assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) &&
152          "Subclass not added?");
153   assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) &&
154          "Subclass not added?");
155   assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) &&
156          "Subclass not added?");
157   assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) &&
158          "Subclass not added?");
159   assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) &&
160          "Subclass not added?");
161   assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPR_and_tcGPRRegClassID)) &&
162          "Subclass not added?");
163   assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPREven_and_tGPR_and_tcGPRRegClassID)) &&
164          "Subclass not added?");
165   assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPROdd_and_tcGPRRegClassID)) &&
166          "Subclass not added?");
167   assert(RBGPR.getSize() == 32 && "GPRs should hold up to 32-bit");
168 
169 #ifndef NDEBUG
170   ARM::checkPartialMappings();
171   ARM::checkValueMappings();
172 #endif
173 }
174 
175 const RegisterBank &
176 ARMRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
177                                             LLT) const {
178   using namespace ARM;
179 
180   switch (RC.getID()) {
181   case GPRRegClassID:
182   case GPRwithAPSRRegClassID:
183   case GPRnopcRegClassID:
184   case rGPRRegClassID:
185   case GPRspRegClassID:
186   case tGPR_and_tcGPRRegClassID:
187   case tcGPRRegClassID:
188   case tGPRRegClassID:
189   case tGPREvenRegClassID:
190   case tGPROddRegClassID:
191   case tGPR_and_tGPREvenRegClassID:
192   case tGPR_and_tGPROddRegClassID:
193   case tGPREven_and_tcGPRRegClassID:
194   case tGPREven_and_tGPR_and_tcGPRRegClassID:
195   case tGPROdd_and_tcGPRRegClassID:
196     return getRegBank(ARM::GPRRegBankID);
197   case HPRRegClassID:
198   case SPR_8RegClassID:
199   case SPRRegClassID:
200   case DPR_8RegClassID:
201   case DPRRegClassID:
202   case QPRRegClassID:
203     return getRegBank(ARM::FPRRegBankID);
204   default:
205     llvm_unreachable("Unsupported register kind");
206   }
207 
208   llvm_unreachable("Switch should handle all register classes");
209 }
210 
211 const RegisterBankInfo::InstructionMapping &
212 ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
213   auto Opc = MI.getOpcode();
214 
215   // Try the default logic for non-generic instructions that are either copies
216   // or already have some operands assigned to banks.
217   if (!isPreISelGenericOpcode(Opc) || Opc == TargetOpcode::G_PHI) {
218     const InstructionMapping &Mapping = getInstrMappingImpl(MI);
219     if (Mapping.isValid())
220       return Mapping;
221   }
222 
223   using namespace TargetOpcode;
224 
225   const MachineFunction &MF = *MI.getParent()->getParent();
226   const MachineRegisterInfo &MRI = MF.getRegInfo();
227   unsigned NumOperands = MI.getNumOperands();
228   const ValueMapping *OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx];
229 
230   switch (Opc) {
231   case G_ADD:
232   case G_SUB: {
233     // Integer operations where the source and destination are in the
234     // same register class.
235     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
236     OperandsMapping = Ty.getSizeInBits() == 64
237                           ? &ARM::ValueMappings[ARM::DPR3OpsIdx]
238                           : &ARM::ValueMappings[ARM::GPR3OpsIdx];
239     break;
240   }
241   case G_MUL:
242   case G_AND:
243   case G_OR:
244   case G_XOR:
245   case G_LSHR:
246   case G_ASHR:
247   case G_SHL:
248   case G_SDIV:
249   case G_UDIV:
250   case G_SEXT:
251   case G_ZEXT:
252   case G_ANYEXT:
253   case G_PTR_ADD:
254   case G_INTTOPTR:
255   case G_PTRTOINT:
256   case G_CTLZ:
257     // FIXME: We're abusing the fact that everything lives in a GPR for now; in
258     // the real world we would use different mappings.
259     OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx];
260     break;
261   case G_TRUNC: {
262     // In some cases we may end up with a G_TRUNC from a 64-bit value to a
263     // 32-bit value. This isn't a real floating point trunc (that would be a
264     // G_FPTRUNC). Instead it is an integer trunc in disguise, which can appear
265     // because the legalizer doesn't distinguish between integer and floating
266     // point values so it may leave some 64-bit integers un-narrowed. Until we
267     // have a more principled solution that doesn't let such things sneak all
268     // the way to this point, just map the source to a DPR and the destination
269     // to a GPR.
270     LLT LargeTy = MRI.getType(MI.getOperand(1).getReg());
271     OperandsMapping =
272         LargeTy.getSizeInBits() <= 32
273             ? &ARM::ValueMappings[ARM::GPR3OpsIdx]
274             : getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
275                                   &ARM::ValueMappings[ARM::DPR3OpsIdx]});
276     break;
277   }
278   case G_LOAD:
279   case G_STORE: {
280     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
281     OperandsMapping =
282         Ty.getSizeInBits() == 64
283             ? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
284                                   &ARM::ValueMappings[ARM::GPR3OpsIdx]})
285             : &ARM::ValueMappings[ARM::GPR3OpsIdx];
286     break;
287   }
288   case G_FADD:
289   case G_FSUB:
290   case G_FMUL:
291   case G_FDIV:
292   case G_FNEG: {
293     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
294     OperandsMapping =Ty.getSizeInBits() == 64
295                           ? &ARM::ValueMappings[ARM::DPR3OpsIdx]
296                           : &ARM::ValueMappings[ARM::SPR3OpsIdx];
297     break;
298   }
299   case G_FMA: {
300     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
301     OperandsMapping =
302         Ty.getSizeInBits() == 64
303             ? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
304                                   &ARM::ValueMappings[ARM::DPR3OpsIdx],
305                                   &ARM::ValueMappings[ARM::DPR3OpsIdx],
306                                   &ARM::ValueMappings[ARM::DPR3OpsIdx]})
307             : getOperandsMapping({&ARM::ValueMappings[ARM::SPR3OpsIdx],
308                                   &ARM::ValueMappings[ARM::SPR3OpsIdx],
309                                   &ARM::ValueMappings[ARM::SPR3OpsIdx],
310                                   &ARM::ValueMappings[ARM::SPR3OpsIdx]});
311     break;
312   }
313   case G_FPEXT: {
314     LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
315     LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
316     if (ToTy.getSizeInBits() == 64 && FromTy.getSizeInBits() == 32)
317       OperandsMapping =
318           getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
319                               &ARM::ValueMappings[ARM::SPR3OpsIdx]});
320     break;
321   }
322   case G_FPTRUNC: {
323     LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
324     LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
325     if (ToTy.getSizeInBits() == 32 && FromTy.getSizeInBits() == 64)
326       OperandsMapping =
327           getOperandsMapping({&ARM::ValueMappings[ARM::SPR3OpsIdx],
328                               &ARM::ValueMappings[ARM::DPR3OpsIdx]});
329     break;
330   }
331   case G_FPTOSI:
332   case G_FPTOUI: {
333     LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
334     LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
335     if ((FromTy.getSizeInBits() == 32 || FromTy.getSizeInBits() == 64) &&
336         ToTy.getSizeInBits() == 32)
337       OperandsMapping =
338           FromTy.getSizeInBits() == 64
339               ? getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
340                                     &ARM::ValueMappings[ARM::DPR3OpsIdx]})
341               : getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
342                                     &ARM::ValueMappings[ARM::SPR3OpsIdx]});
343     break;
344   }
345   case G_SITOFP:
346   case G_UITOFP: {
347     LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
348     LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
349     if (FromTy.getSizeInBits() == 32 &&
350         (ToTy.getSizeInBits() == 32 || ToTy.getSizeInBits() == 64))
351       OperandsMapping =
352           ToTy.getSizeInBits() == 64
353               ? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
354                                     &ARM::ValueMappings[ARM::GPR3OpsIdx]})
355               : getOperandsMapping({&ARM::ValueMappings[ARM::SPR3OpsIdx],
356                                     &ARM::ValueMappings[ARM::GPR3OpsIdx]});
357     break;
358   }
359   case G_FCONSTANT: {
360     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
361     OperandsMapping = getOperandsMapping(
362         {Ty.getSizeInBits() == 64 ? &ARM::ValueMappings[ARM::DPR3OpsIdx]
363                                   : &ARM::ValueMappings[ARM::SPR3OpsIdx],
364          nullptr});
365     break;
366   }
367   case G_CONSTANT:
368   case G_FRAME_INDEX:
369   case G_GLOBAL_VALUE:
370     OperandsMapping =
371         getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr});
372     break;
373   case G_SELECT: {
374     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
375     (void)Ty;
376     LLT Ty2 = MRI.getType(MI.getOperand(1).getReg());
377     (void)Ty2;
378     assert(Ty.getSizeInBits() == 32 && "Unsupported size for G_SELECT");
379     assert(Ty2.getSizeInBits() == 1 && "Unsupported size for G_SELECT");
380     OperandsMapping =
381         getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
382                             &ARM::ValueMappings[ARM::GPR3OpsIdx],
383                             &ARM::ValueMappings[ARM::GPR3OpsIdx],
384                             &ARM::ValueMappings[ARM::GPR3OpsIdx]});
385     break;
386   }
387   case G_ICMP: {
388     LLT Ty2 = MRI.getType(MI.getOperand(2).getReg());
389     (void)Ty2;
390     assert(Ty2.getSizeInBits() == 32 && "Unsupported size for G_ICMP");
391     OperandsMapping =
392         getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr,
393                             &ARM::ValueMappings[ARM::GPR3OpsIdx],
394                             &ARM::ValueMappings[ARM::GPR3OpsIdx]});
395     break;
396   }
397   case G_FCMP: {
398     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
399     (void)Ty;
400     LLT Ty1 = MRI.getType(MI.getOperand(2).getReg());
401     LLT Ty2 = MRI.getType(MI.getOperand(3).getReg());
402     (void)Ty2;
403     assert(Ty.getSizeInBits() == 1 && "Unsupported size for G_FCMP");
404     assert(Ty1.getSizeInBits() == Ty2.getSizeInBits() &&
405            "Mismatched operand sizes for G_FCMP");
406 
407     unsigned Size = Ty1.getSizeInBits();
408     assert((Size == 32 || Size == 64) && "Unsupported size for G_FCMP");
409 
410     auto FPRValueMapping = Size == 32 ? &ARM::ValueMappings[ARM::SPR3OpsIdx]
411                                       : &ARM::ValueMappings[ARM::DPR3OpsIdx];
412     OperandsMapping =
413         getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr,
414                             FPRValueMapping, FPRValueMapping});
415     break;
416   }
417   case G_MERGE_VALUES: {
418     // We only support G_MERGE_VALUES for creating a double precision floating
419     // point value out of two GPRs.
420     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
421     LLT Ty1 = MRI.getType(MI.getOperand(1).getReg());
422     LLT Ty2 = MRI.getType(MI.getOperand(2).getReg());
423     if (Ty.getSizeInBits() != 64 || Ty1.getSizeInBits() != 32 ||
424         Ty2.getSizeInBits() != 32)
425       return getInvalidInstructionMapping();
426     OperandsMapping =
427         getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
428                             &ARM::ValueMappings[ARM::GPR3OpsIdx],
429                             &ARM::ValueMappings[ARM::GPR3OpsIdx]});
430     break;
431   }
432   case G_UNMERGE_VALUES: {
433     // We only support G_UNMERGE_VALUES for splitting a double precision
434     // floating point value into two GPRs.
435     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
436     LLT Ty1 = MRI.getType(MI.getOperand(1).getReg());
437     LLT Ty2 = MRI.getType(MI.getOperand(2).getReg());
438     if (Ty.getSizeInBits() != 32 || Ty1.getSizeInBits() != 32 ||
439         Ty2.getSizeInBits() != 64)
440       return getInvalidInstructionMapping();
441     OperandsMapping =
442         getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
443                             &ARM::ValueMappings[ARM::GPR3OpsIdx],
444                             &ARM::ValueMappings[ARM::DPR3OpsIdx]});
445     break;
446   }
447   case G_BR:
448     OperandsMapping = getOperandsMapping({nullptr});
449     break;
450   case G_BRCOND:
451     OperandsMapping =
452         getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr});
453     break;
454   case DBG_VALUE: {
455     SmallVector<const ValueMapping *, 4> OperandBanks(NumOperands);
456     const MachineOperand &MaybeReg = MI.getOperand(0);
457     if (MaybeReg.isReg() && MaybeReg.getReg()) {
458       unsigned Size = MRI.getType(MaybeReg.getReg()).getSizeInBits();
459       if (Size > 32 && Size != 64)
460         return getInvalidInstructionMapping();
461       OperandBanks[0] = Size == 64 ? &ARM::ValueMappings[ARM::DPR3OpsIdx]
462                                    : &ARM::ValueMappings[ARM::GPR3OpsIdx];
463     }
464     OperandsMapping = getOperandsMapping(OperandBanks);
465     break;
466   }
467   default:
468     return getInvalidInstructionMapping();
469   }
470 
471 #ifndef NDEBUG
472   for (unsigned i = 0; i < NumOperands; i++) {
473     for (const auto &Mapping : OperandsMapping[i]) {
474       assert(
475           (Mapping.RegBank->getID() != ARM::FPRRegBankID ||
476            MF.getSubtarget<ARMSubtarget>().hasVFP2Base()) &&
477           "Trying to use floating point register bank on target without vfp");
478     }
479   }
480 #endif
481 
482   return getInstructionMapping(DefaultMappingID, /*Cost=*/1, OperandsMapping,
483                                NumOperands);
484 }
485