1 //===- ARMRegisterBankInfo ---------------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the RegisterBankInfo class for ARM.
10 /// \todo This should be generated by TableGen.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_ARM_ARMREGISTERBANKINFO_H
14 #define LLVM_LIB_TARGET_ARM_ARMREGISTERBANKINFO_H
15 
16 #include "llvm/CodeGen/RegisterBankInfo.h"
17 
18 #define GET_REGBANK_DECLARATIONS
19 #include "ARMGenRegisterBank.inc"
20 
21 namespace llvm {
22 
23 class TargetRegisterInfo;
24 
25 class ARMGenRegisterBankInfo : public RegisterBankInfo {
26 #define GET_TARGET_REGBANK_CLASS
27 #include "ARMGenRegisterBank.inc"
28 };
29 
30 /// This class provides the information for the target register banks.
31 class ARMRegisterBankInfo final : public ARMGenRegisterBankInfo {
32 public:
33   ARMRegisterBankInfo(const TargetRegisterInfo &TRI);
34 
35   const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
36                                              LLT) const override;
37 
38   const InstructionMapping &
39   getInstrMapping(const MachineInstr &MI) const override;
40 };
41 } // End llvm namespace.
42 #endif
43