1//===-- ARMRegisterInfo.td - ARM Register defs -------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9include "ARMSystemRegister.td" 10 11//===----------------------------------------------------------------------===// 12// Declarations that describe the ARM register file 13//===----------------------------------------------------------------------===// 14 15// Registers are identified with 4-bit ID numbers. 16class ARMReg<bits<16> Enc, string n, list<Register> subregs = [], 17 list<string> altNames = []> : Register<n, altNames> { 18 let HWEncoding = Enc; 19 let Namespace = "ARM"; 20 let SubRegs = subregs; 21 // All bits of ARM registers with sub-registers are covered by sub-registers. 22 let CoveredBySubRegs = 1; 23} 24 25class ARMFReg<bits<16> Enc, string n> : Register<n> { 26 let HWEncoding = Enc; 27 let Namespace = "ARM"; 28} 29 30let Namespace = "ARM", 31 FallbackRegAltNameIndex = NoRegAltName in { 32 def RegNamesRaw : RegAltNameIndex; 33} 34 35// Subregister indices. 36let Namespace = "ARM" in { 37def qqsub_0 : SubRegIndex<256>; 38def qqsub_1 : SubRegIndex<256, 256>; 39 40// Note: Code depends on these having consecutive numbers. 41def qsub_0 : SubRegIndex<128>; 42def qsub_1 : SubRegIndex<128, 128>; 43def qsub_2 : ComposedSubRegIndex<qqsub_1, qsub_0>; 44def qsub_3 : ComposedSubRegIndex<qqsub_1, qsub_1>; 45 46def dsub_0 : SubRegIndex<64>; 47def dsub_1 : SubRegIndex<64, 64>; 48def dsub_2 : ComposedSubRegIndex<qsub_1, dsub_0>; 49def dsub_3 : ComposedSubRegIndex<qsub_1, dsub_1>; 50def dsub_4 : ComposedSubRegIndex<qsub_2, dsub_0>; 51def dsub_5 : ComposedSubRegIndex<qsub_2, dsub_1>; 52def dsub_6 : ComposedSubRegIndex<qsub_3, dsub_0>; 53def dsub_7 : ComposedSubRegIndex<qsub_3, dsub_1>; 54 55def ssub_0 : SubRegIndex<32>; 56def ssub_1 : SubRegIndex<32, 32>; 57def ssub_2 : ComposedSubRegIndex<dsub_1, ssub_0>; 58def ssub_3 : ComposedSubRegIndex<dsub_1, ssub_1>; 59def ssub_4 : ComposedSubRegIndex<dsub_2, ssub_0>; 60def ssub_5 : ComposedSubRegIndex<dsub_2, ssub_1>; 61def ssub_6 : ComposedSubRegIndex<dsub_3, ssub_0>; 62def ssub_7 : ComposedSubRegIndex<dsub_3, ssub_1>; 63def ssub_8 : ComposedSubRegIndex<dsub_4, ssub_0>; 64def ssub_9 : ComposedSubRegIndex<dsub_4, ssub_1>; 65def ssub_10 : ComposedSubRegIndex<dsub_5, ssub_0>; 66def ssub_11 : ComposedSubRegIndex<dsub_5, ssub_1>; 67def ssub_12 : ComposedSubRegIndex<dsub_6, ssub_0>; 68def ssub_13 : ComposedSubRegIndex<dsub_6, ssub_1>; 69def ssub_14 : ComposedSubRegIndex<dsub_7, ssub_0>; 70def ssub_15 : ComposedSubRegIndex<dsub_7, ssub_1>; 71 72def gsub_0 : SubRegIndex<32>; 73def gsub_1 : SubRegIndex<32, 32>; 74// Let TableGen synthesize the remaining 12 ssub_* indices. 75// We don't need to name them. 76} 77 78// Integer registers 79def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>; 80def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>; 81def R2 : ARMReg< 2, "r2">, DwarfRegNum<[2]>; 82def R3 : ARMReg< 3, "r3">, DwarfRegNum<[3]>; 83def R4 : ARMReg< 4, "r4">, DwarfRegNum<[4]>; 84def R5 : ARMReg< 5, "r5">, DwarfRegNum<[5]>; 85def R6 : ARMReg< 6, "r6">, DwarfRegNum<[6]>; 86def R7 : ARMReg< 7, "r7">, DwarfRegNum<[7]>; 87// These require 32-bit instructions. 88let CostPerUse = [1] in { 89def R8 : ARMReg< 8, "r8">, DwarfRegNum<[8]>; 90def R9 : ARMReg< 9, "r9">, DwarfRegNum<[9]>; 91def R10 : ARMReg<10, "r10">, DwarfRegNum<[10]>; 92def R11 : ARMReg<11, "r11">, DwarfRegNum<[11]>; 93def R12 : ARMReg<12, "r12">, DwarfRegNum<[12]>; 94let RegAltNameIndices = [RegNamesRaw] in { 95def SP : ARMReg<13, "sp", [], ["r13"]>, DwarfRegNum<[13]>; 96def LR : ARMReg<14, "lr", [], ["r14"]>, DwarfRegNum<[14]>; 97def PC : ARMReg<15, "pc", [], ["r15"]>, DwarfRegNum<[15]>; 98} 99} 100 101// Float registers 102def S0 : ARMFReg< 0, "s0">; def S1 : ARMFReg< 1, "s1">; 103def S2 : ARMFReg< 2, "s2">; def S3 : ARMFReg< 3, "s3">; 104def S4 : ARMFReg< 4, "s4">; def S5 : ARMFReg< 5, "s5">; 105def S6 : ARMFReg< 6, "s6">; def S7 : ARMFReg< 7, "s7">; 106def S8 : ARMFReg< 8, "s8">; def S9 : ARMFReg< 9, "s9">; 107def S10 : ARMFReg<10, "s10">; def S11 : ARMFReg<11, "s11">; 108def S12 : ARMFReg<12, "s12">; def S13 : ARMFReg<13, "s13">; 109def S14 : ARMFReg<14, "s14">; def S15 : ARMFReg<15, "s15">; 110def S16 : ARMFReg<16, "s16">; def S17 : ARMFReg<17, "s17">; 111def S18 : ARMFReg<18, "s18">; def S19 : ARMFReg<19, "s19">; 112def S20 : ARMFReg<20, "s20">; def S21 : ARMFReg<21, "s21">; 113def S22 : ARMFReg<22, "s22">; def S23 : ARMFReg<23, "s23">; 114def S24 : ARMFReg<24, "s24">; def S25 : ARMFReg<25, "s25">; 115def S26 : ARMFReg<26, "s26">; def S27 : ARMFReg<27, "s27">; 116def S28 : ARMFReg<28, "s28">; def S29 : ARMFReg<29, "s29">; 117def S30 : ARMFReg<30, "s30">; def S31 : ARMFReg<31, "s31">; 118 119// Aliases of the F* registers used to hold 64-bit fp values (doubles) 120let SubRegIndices = [ssub_0, ssub_1] in { 121def D0 : ARMReg< 0, "d0", [S0, S1]>, DwarfRegNum<[256]>; 122def D1 : ARMReg< 1, "d1", [S2, S3]>, DwarfRegNum<[257]>; 123def D2 : ARMReg< 2, "d2", [S4, S5]>, DwarfRegNum<[258]>; 124def D3 : ARMReg< 3, "d3", [S6, S7]>, DwarfRegNum<[259]>; 125def D4 : ARMReg< 4, "d4", [S8, S9]>, DwarfRegNum<[260]>; 126def D5 : ARMReg< 5, "d5", [S10, S11]>, DwarfRegNum<[261]>; 127def D6 : ARMReg< 6, "d6", [S12, S13]>, DwarfRegNum<[262]>; 128def D7 : ARMReg< 7, "d7", [S14, S15]>, DwarfRegNum<[263]>; 129def D8 : ARMReg< 8, "d8", [S16, S17]>, DwarfRegNum<[264]>; 130def D9 : ARMReg< 9, "d9", [S18, S19]>, DwarfRegNum<[265]>; 131def D10 : ARMReg<10, "d10", [S20, S21]>, DwarfRegNum<[266]>; 132def D11 : ARMReg<11, "d11", [S22, S23]>, DwarfRegNum<[267]>; 133def D12 : ARMReg<12, "d12", [S24, S25]>, DwarfRegNum<[268]>; 134def D13 : ARMReg<13, "d13", [S26, S27]>, DwarfRegNum<[269]>; 135def D14 : ARMReg<14, "d14", [S28, S29]>, DwarfRegNum<[270]>; 136def D15 : ARMReg<15, "d15", [S30, S31]>, DwarfRegNum<[271]>; 137} 138 139// VFP3 defines 16 additional double registers 140def D16 : ARMFReg<16, "d16">, DwarfRegNum<[272]>; 141def D17 : ARMFReg<17, "d17">, DwarfRegNum<[273]>; 142def D18 : ARMFReg<18, "d18">, DwarfRegNum<[274]>; 143def D19 : ARMFReg<19, "d19">, DwarfRegNum<[275]>; 144def D20 : ARMFReg<20, "d20">, DwarfRegNum<[276]>; 145def D21 : ARMFReg<21, "d21">, DwarfRegNum<[277]>; 146def D22 : ARMFReg<22, "d22">, DwarfRegNum<[278]>; 147def D23 : ARMFReg<23, "d23">, DwarfRegNum<[279]>; 148def D24 : ARMFReg<24, "d24">, DwarfRegNum<[280]>; 149def D25 : ARMFReg<25, "d25">, DwarfRegNum<[281]>; 150def D26 : ARMFReg<26, "d26">, DwarfRegNum<[282]>; 151def D27 : ARMFReg<27, "d27">, DwarfRegNum<[283]>; 152def D28 : ARMFReg<28, "d28">, DwarfRegNum<[284]>; 153def D29 : ARMFReg<29, "d29">, DwarfRegNum<[285]>; 154def D30 : ARMFReg<30, "d30">, DwarfRegNum<[286]>; 155def D31 : ARMFReg<31, "d31">, DwarfRegNum<[287]>; 156 157// Advanced SIMD (NEON) defines 16 quad-word aliases 158let SubRegIndices = [dsub_0, dsub_1] in { 159def Q0 : ARMReg< 0, "q0", [D0, D1]>; 160def Q1 : ARMReg< 1, "q1", [D2, D3]>; 161def Q2 : ARMReg< 2, "q2", [D4, D5]>; 162def Q3 : ARMReg< 3, "q3", [D6, D7]>; 163def Q4 : ARMReg< 4, "q4", [D8, D9]>; 164def Q5 : ARMReg< 5, "q5", [D10, D11]>; 165def Q6 : ARMReg< 6, "q6", [D12, D13]>; 166def Q7 : ARMReg< 7, "q7", [D14, D15]>; 167} 168let SubRegIndices = [dsub_0, dsub_1] in { 169def Q8 : ARMReg< 8, "q8", [D16, D17]>; 170def Q9 : ARMReg< 9, "q9", [D18, D19]>; 171def Q10 : ARMReg<10, "q10", [D20, D21]>; 172def Q11 : ARMReg<11, "q11", [D22, D23]>; 173def Q12 : ARMReg<12, "q12", [D24, D25]>; 174def Q13 : ARMReg<13, "q13", [D26, D27]>; 175def Q14 : ARMReg<14, "q14", [D28, D29]>; 176def Q15 : ARMReg<15, "q15", [D30, D31]>; 177} 178 179// Current Program Status Register. 180// We model fpscr with two registers: FPSCR models the control bits and will be 181// reserved. FPSCR_NZCV models the flag bits and will be unreserved. APSR_NZCV 182// models the APSR when it's accessed by some special instructions. In such cases 183// it has the same encoding as PC. 184def CPSR : ARMReg<0, "cpsr">; 185def APSR : ARMReg<15, "apsr">; 186def APSR_NZCV : ARMReg<15, "apsr_nzcv">; 187def SPSR : ARMReg<2, "spsr">; 188def FPSCR : ARMReg<3, "fpscr">; 189def FPSCR_NZCV : ARMReg<3, "fpscr_nzcv"> { 190 let Aliases = [FPSCR]; 191} 192def ITSTATE : ARMReg<4, "itstate">; 193 194// Special Registers - only available in privileged mode. 195def FPSID : ARMReg<0, "fpsid">; 196def MVFR2 : ARMReg<5, "mvfr2">; 197def MVFR1 : ARMReg<6, "mvfr1">; 198def MVFR0 : ARMReg<7, "mvfr0">; 199def FPEXC : ARMReg<8, "fpexc">; 200def FPINST : ARMReg<9, "fpinst">; 201def FPINST2 : ARMReg<10, "fpinst2">; 202// These encodings aren't actual instruction encodings, their encoding depends 203// on the instruction they are used in and for VPR 32 was chosen such that it 204// always comes last in spr_reglist_with_vpr. 205def VPR : ARMReg<32, "vpr">; 206def FPSCR_NZCVQC 207 : ARMReg<2, "fpscr_nzcvqc">; 208def P0 : ARMReg<13, "p0">; 209def FPCXTNS : ARMReg<14, "fpcxtns">; 210def FPCXTS : ARMReg<15, "fpcxts">; 211 212def ZR : ARMReg<15, "zr">, DwarfRegNum<[15]>; 213 214def RA_AUTH_CODE : ARMReg<12, "ra_auth_code">, DwarfRegNum<[143]>; 215 216// Register classes. 217// 218// pc == Program Counter 219// lr == Link Register 220// sp == Stack Pointer 221// r12 == ip (scratch) 222// r7 == Frame Pointer (thumb-style backtraces) 223// r9 == May be reserved as Thread Register 224// r11 == Frame Pointer (arm-style backtraces) 225// r10 == Stack Limit 226// 227def GPR : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12), 228 SP, LR, PC)> { 229 // Allocate LR as the first CSR since it is always saved anyway. 230 // For Thumb1 mode, we don't want to allocate hi regs at all, as we don't 231 // know how to spill them. If we make our prologue/epilogue code smarter at 232 // some point, we can go back to using the above allocation orders for the 233 // Thumb1 instructions that know how to use hi regs. 234 let AltOrders = [(add LR, GPR), (trunc GPR, 8), 235 (add (trunc GPR, 8), R12, LR, (shl GPR, 8))]; 236 let AltOrderSelect = [{ 237 return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF); 238 }]; 239 let DiagnosticString = "operand must be a register in range [r0, r15]"; 240} 241 242// Register set that excludes registers that are reserved for procedure calls. 243// This is used for pseudo-instructions that are actually implemented using a 244// procedure call. 245def GPRnoip : RegisterClass<"ARM", [i32], 32, (sub GPR, R12, LR)> { 246 // Allocate LR as the first CSR since it is always saved anyway. 247 // For Thumb1 mode, we don't want to allocate hi regs at all, as we don't 248 // know how to spill them. If we make our prologue/epilogue code smarter at 249 // some point, we can go back to using the above allocation orders for the 250 // Thumb1 instructions that know how to use hi regs. 251 let AltOrders = [(add GPRnoip, GPRnoip), (trunc GPRnoip, 8), 252 (add (trunc GPRnoip, 8), (shl GPRnoip, 8))]; 253 let AltOrderSelect = [{ 254 return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF); 255 }]; 256 let DiagnosticString = "operand must be a register in range [r0, r14]"; 257} 258 259// GPRs without the PC. Some ARM instructions do not allow the PC in 260// certain operand slots, particularly as the destination. Primarily 261// useful for disassembly. 262def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> { 263 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8), 264 (add (trunc GPRnopc, 8), R12, LR, (shl GPRnopc, 8))]; 265 let AltOrderSelect = [{ 266 return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF); 267 }]; 268 let DiagnosticString = "operand must be a register in range [r0, r14]"; 269} 270 271// GPRs without the PC but with APSR. Some instructions allow accessing the 272// APSR, while actually encoding PC in the register field. This is useful 273// for assembly and disassembly only. 274def GPRwithAPSR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), APSR_NZCV)> { 275 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)]; 276 let AltOrderSelect = [{ 277 return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only(); 278 }]; 279 let DiagnosticString = "operand must be a register in range [r0, r14] or apsr_nzcv"; 280} 281 282// GPRs without the SP register. Used for BXAUT and AUTG 283def GPRnosp : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12), LR, PC)> { 284 let AltOrders = [(add LR, GPRnosp), (trunc GPRnosp, 8), 285 (add (trunc GPRnosp, 8), R12, LR, (shl GPRnosp, 8))]; 286 let AltOrderSelect = [{ 287 return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF); 288 }]; 289 let DiagnosticString = "operand must be a register in range [r0, r12] or LR or PC"; 290} 291 292// GPRs without the PC and SP registers but with APSR. Used by CLRM instruction. 293def GPRwithAPSRnosp : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12), LR, APSR)> { 294 let isAllocatable = 0; 295} 296 297def GPRwithZR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), ZR)> { 298 let AltOrders = [(add LR, GPRwithZR), (trunc GPRwithZR, 8)]; 299 let AltOrderSelect = [{ 300 return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only(); 301 }]; 302 let DiagnosticString = "operand must be a register in range [r0, r14] or zr"; 303} 304 305def GPRwithZRnosp : RegisterClass<"ARM", [i32], 32, (sub GPRwithZR, SP)> { 306 let AltOrders = [(add LR, GPRwithZRnosp), (trunc GPRwithZRnosp, 8)]; 307 let AltOrderSelect = [{ 308 return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only(); 309 }]; 310 let DiagnosticString = "operand must be a register in range [r0, r12] or r14 or zr"; 311} 312 313// GPRsp - Only the SP is legal. Used by Thumb1 instructions that want the 314// implied SP argument list. 315// FIXME: It would be better to not use this at all and refactor the 316// instructions to not have SP an an explicit argument. That makes 317// frame index resolution a bit trickier, though. 318def GPRsp : RegisterClass<"ARM", [i32], 32, (add SP)> { 319 let DiagnosticString = "operand must be a register sp"; 320} 321 322// GPRlr - Only LR is legal. Used by ARMv8.1-M Low Overhead Loop instructions 323// where LR is the only legal loop counter register. 324def GPRlr : RegisterClass<"ARM", [i32], 32, (add LR)>; 325 326// restricted GPR register class. Many Thumb2 instructions allow the full 327// register range for operands, but have undefined behaviours when PC 328// or SP (R13 or R15) are used. The ARM ISA refers to these operands 329// via the BadReg() pseudo-code description. 330def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> { 331 let AltOrders = [(add LR, rGPR), (trunc rGPR, 8), 332 (add (trunc rGPR, 8), R12, LR, (shl rGPR, 8))]; 333 let AltOrderSelect = [{ 334 return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF); 335 }]; 336 let DiagnosticType = "rGPR"; 337} 338 339// GPRs without the PC and SP but with APSR_NZCV.Some instructions allow 340// accessing the APSR_NZCV, while actually encoding PC in the register field. 341// This is useful for assembly and disassembly only. 342// Currently used by the CDE extension. 343def GPRwithAPSR_NZCVnosp 344 : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12), LR, APSR_NZCV)> { 345 let isAllocatable = 0; 346 let DiagnosticString = 347 "operand must be a register in the range [r0, r12], r14 or apsr_nzcv"; 348} 349 350// Thumb registers are R0-R7 normally. Some instructions can still use 351// the general GPR register class above (MOV, e.g.) 352def tGPR : RegisterClass<"ARM", [i32], 32, (trunc GPR, 8)> { 353 let DiagnosticString = "operand must be a register in range [r0, r7]"; 354} 355 356// Thumb registers R0-R7 and the PC. Some instructions like TBB or THH allow 357// the PC to be used as a destination operand as well. 358def tGPRwithpc : RegisterClass<"ARM", [i32], 32, (add tGPR, PC)>; 359 360// The high registers in thumb mode, R8-R15. 361def hGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, tGPR)> { 362 let DiagnosticString = "operand must be a register in range [r8, r15]"; 363} 364 365// For tail calls, we can't use callee-saved registers, as they are restored 366// to the saved value before the tail call, which would clobber a call address. 367// Note, getMinimalPhysRegClass(R0) returns tGPR because of the names of 368// this class and the preceding one(!) This is what we want. 369def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R12)> { 370 let AltOrders = [(and tcGPR, tGPR)]; 371 let AltOrderSelect = [{ 372 return MF.getSubtarget<ARMSubtarget>().isThumb1Only(); 373 }]; 374} 375 376def tGPROdd : RegisterClass<"ARM", [i32], 32, (add R1, R3, R5, R7, R9, R11)> { 377 let AltOrders = [(and tGPROdd, tGPR)]; 378 let AltOrderSelect = [{ 379 return MF.getSubtarget<ARMSubtarget>().isThumb1Only(); 380 }]; 381 let DiagnosticString = 382 "operand must be an odd-numbered register in range [r1,r11]"; 383} 384 385def tGPREven : RegisterClass<"ARM", [i32], 32, (add R0, R2, R4, R6, R8, R10, R12, LR)> { 386 let AltOrders = [(and tGPREven, tGPR)]; 387 let AltOrderSelect = [{ 388 return MF.getSubtarget<ARMSubtarget>().isThumb1Only(); 389 }]; 390 let DiagnosticString = "operand must be an even-numbered register"; 391} 392 393// Condition code registers. 394def CCR : RegisterClass<"ARM", [i32], 32, (add CPSR)> { 395 let CopyCost = -1; // Don't allow copying of status registers. 396 let isAllocatable = 0; 397} 398 399// MVE Condition code register. 400def VCCR : RegisterClass<"ARM", [i32, v16i1, v8i1, v4i1, v2i1], 32, (add VPR)> { 401// let CopyCost = -1; // Don't allow copying of status registers. 402} 403 404// FPSCR, when the flags at the top of it are used as the input or 405// output to an instruction such as MVE VADC. 406def cl_FPSCR_NZCV : RegisterClass<"ARM", [i32], 32, (add FPSCR_NZCV)>; 407 408// Scalar single precision floating point register class.. 409// FIXME: Allocation order changed to s0, s2, ... or s0, s4, ... as a quick hack 410// to avoid partial-write dependencies on D or Q (depending on platform) 411// registers (S registers are renamed as portions of D/Q registers). 412def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> { 413 let AltOrders = [(add (decimate SPR, 2), SPR), 414 (add (decimate SPR, 4), 415 (decimate SPR, 2), 416 (decimate (rotl SPR, 1), 4), 417 (decimate (rotl SPR, 1), 2))]; 418 let AltOrderSelect = [{ 419 return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs(); 420 }]; 421 let DiagnosticString = "operand must be a register in range [s0, s31]"; 422} 423 424def HPR : RegisterClass<"ARM", [f16, bf16], 32, (sequence "S%u", 0, 31)> { 425 let AltOrders = [(add (decimate HPR, 2), SPR), 426 (add (decimate HPR, 4), 427 (decimate HPR, 2), 428 (decimate (rotl HPR, 1), 4), 429 (decimate (rotl HPR, 1), 2))]; 430 let AltOrderSelect = [{ 431 return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs(); 432 }]; 433 let DiagnosticString = "operand must be a register in range [s0, s31]"; 434} 435 436// Subset of SPR which can be used as a source of NEON scalars for 16-bit 437// operations 438def SPR_8 : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 15)> { 439 let DiagnosticString = "operand must be a register in range [s0, s15]"; 440} 441 442// Scalar double precision floating point / generic 64-bit vector register 443// class. 444// ARM requires only word alignment for double. It's more performant if it 445// is double-word alignment though. 446def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16, v4bf16], 64, 447 (sequence "D%u", 0, 31)> { 448 // Allocate non-VFP2 registers D16-D31 first, and prefer even registers on 449 // Darwin platforms. 450 let AltOrders = [(rotl DPR, 16), 451 (add (decimate (rotl DPR, 16), 2), (rotl DPR, 16))]; 452 let AltOrderSelect = [{ 453 return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs(); 454 }]; 455 let DiagnosticType = "DPR"; 456} 457 458// Scalar single and double precision floating point and VPR register class, 459// this is only used for parsing, don't use it anywhere else as the size and 460// types don't match! 461def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> { 462 let isAllocatable = 0; 463} 464 465// Subset of DPR that are accessible with VFP2 (and so that also have 466// 32-bit SPR subregs). 467def DPR_VFP2 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16, v4bf16], 64, 468 (trunc DPR, 16)> { 469 let DiagnosticString = "operand must be a register in range [d0, d15]"; 470} 471 472// Subset of DPR which can be used as a source of NEON scalars for 16-bit 473// operations 474def DPR_8 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16, v4bf16], 64, 475 (trunc DPR, 8)> { 476 let DiagnosticString = "operand must be a register in range [d0, d7]"; 477} 478 479// Generic 128-bit vector register class. 480def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16, v8bf16], 128, 481 (sequence "Q%u", 0, 15)> { 482 // Allocate non-VFP2 aliases Q8-Q15 first. 483 let AltOrders = [(rotl QPR, 8), (trunc QPR, 8)]; 484 let AltOrderSelect = [{ 485 return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps(); 486 }]; 487 let DiagnosticString = "operand must be a register in range [q0, q15]"; 488} 489 490// Subset of QPR that have 32-bit SPR subregs. 491def QPR_VFP2 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 492 128, (trunc QPR, 8)> { 493 let DiagnosticString = "operand must be a register in range [q0, q7]"; 494} 495 496// Subset of QPR that have DPR_8 and SPR_8 subregs. 497def QPR_8 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 498 128, (trunc QPR, 4)> { 499 let DiagnosticString = "operand must be a register in range [q0, q3]"; 500} 501 502// MVE 128-bit vector register class. This class is only really needed for 503// parsing assembly, since we still have to truncate the register set in the QPR 504// class anyway. 505def MQPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16], 506 128, (trunc QPR, 8)>; 507 508// Pseudo-registers representing odd-even pairs of D registers. The even-odd 509// pairs are already represented by the Q registers. 510// These are needed by NEON instructions requiring two consecutive D registers. 511// There is no D31_D0 register as that is always an UNPREDICTABLE encoding. 512def TuplesOE2D : RegisterTuples<[dsub_0, dsub_1], 513 [(decimate (shl DPR, 1), 2), 514 (decimate (shl DPR, 2), 2)]>; 515 516// Register class representing a pair of consecutive D registers. 517// Use the Q registers for the even-odd pairs. 518def DPair : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 519 128, (interleave QPR, TuplesOE2D)> { 520 // Allocate starting at non-VFP2 registers D16-D31 first. 521 // Prefer even-odd pairs as they are easier to copy. 522 let AltOrders = [(add (rotl QPR, 8), (rotl DPair, 16)), 523 (add (trunc QPR, 8), (trunc DPair, 16))]; 524 let AltOrderSelect = [{ 525 return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps(); 526 }]; 527} 528 529// Pseudo-registers representing even-odd pairs of GPRs from R1 to R13/SP. 530// These are needed by instructions (e.g. ldrexd/strexd) requiring even-odd GPRs. 531def Tuples2Rnosp : RegisterTuples<[gsub_0, gsub_1], 532 [(add R0, R2, R4, R6, R8, R10), 533 (add R1, R3, R5, R7, R9, R11)]>; 534 535def Tuples2Rsp : RegisterTuples<[gsub_0, gsub_1], 536 [(add R12), (add SP)]>; 537 538// Register class representing a pair of even-odd GPRs. 539def GPRPair : RegisterClass<"ARM", [untyped], 64, (add Tuples2Rnosp, Tuples2Rsp)> { 540 let Size = 64; // 2 x 32 bits, we have no predefined type of that size. 541} 542 543// Register class representing a pair of even-odd GPRs, except (R12, SP). 544def GPRPairnosp : RegisterClass<"ARM", [untyped], 64, (add Tuples2Rnosp)> { 545 let Size = 64; // 2 x 32 bits, we have no predefined type of that size. 546} 547 548// Pseudo-registers representing 3 consecutive D registers. 549def Tuples3D : RegisterTuples<[dsub_0, dsub_1, dsub_2], 550 [(shl DPR, 0), 551 (shl DPR, 1), 552 (shl DPR, 2)]>; 553 554// 3 consecutive D registers. 555def DTriple : RegisterClass<"ARM", [untyped], 64, (add Tuples3D)> { 556 let Size = 192; // 3 x 64 bits, we have no predefined type of that size. 557} 558 559// Pseudo 256-bit registers to represent pairs of Q registers. These should 560// never be present in the emitted code. 561// These are used for NEON load / store instructions, e.g., vld4, vst3. 562def Tuples2Q : RegisterTuples<[qsub_0, qsub_1], [(shl QPR, 0), (shl QPR, 1)]>; 563 564// Pseudo 256-bit vector register class to model pairs of Q registers 565// (4 consecutive D registers). 566def QQPR : RegisterClass<"ARM", [v4i64], 256, (add Tuples2Q)> { 567 // Allocate non-VFP2 aliases first. 568 let AltOrders = [(rotl QQPR, 8)]; 569 let AltOrderSelect = [{ return 1; }]; 570} 571 572// Same as QQPR but for MVE, containing the 7 register pairs made up from Q0-Q7. 573def MQQPR : RegisterClass<"ARM", [v4i64], 256, (trunc QQPR, 7)>; 574 575// Tuples of 4 D regs that isn't also a pair of Q regs. 576def TuplesOE4D : RegisterTuples<[dsub_0, dsub_1, dsub_2, dsub_3], 577 [(decimate (shl DPR, 1), 2), 578 (decimate (shl DPR, 2), 2), 579 (decimate (shl DPR, 3), 2), 580 (decimate (shl DPR, 4), 2)]>; 581 582// 4 consecutive D registers. 583def DQuad : RegisterClass<"ARM", [v4i64], 256, 584 (interleave Tuples2Q, TuplesOE4D)>; 585 586// Pseudo 512-bit registers to represent four consecutive Q registers. 587def Tuples2QQ : RegisterTuples<[qqsub_0, qqsub_1], 588 [(shl QQPR, 0), (shl QQPR, 2)]>; 589 590// Pseudo 512-bit vector register class to model 4 consecutive Q registers 591// (8 consecutive D registers). 592def QQQQPR : RegisterClass<"ARM", [v8i64], 256, (add Tuples2QQ)> { 593 // Allocate non-VFP2 aliases first. 594 let AltOrders = [(rotl QQQQPR, 8)]; 595 let AltOrderSelect = [{ return 1; }]; 596} 597 598// Same as QQPR but for MVE, containing the 5 register quads made up from Q0-Q7. 599def MQQQQPR : RegisterClass<"ARM", [v8i64], 256, (trunc QQQQPR, 5)>; 600 601 602// Pseudo-registers representing 2-spaced consecutive D registers. 603def Tuples2DSpc : RegisterTuples<[dsub_0, dsub_2], 604 [(shl DPR, 0), 605 (shl DPR, 2)]>; 606 607// Spaced pairs of D registers. 608def DPairSpc : RegisterClass<"ARM", [v2i64], 64, (add Tuples2DSpc)>; 609 610def Tuples3DSpc : RegisterTuples<[dsub_0, dsub_2, dsub_4], 611 [(shl DPR, 0), 612 (shl DPR, 2), 613 (shl DPR, 4)]>; 614 615// Spaced triples of D registers. 616def DTripleSpc : RegisterClass<"ARM", [untyped], 64, (add Tuples3DSpc)> { 617 let Size = 192; // 3 x 64 bits, we have no predefined type of that size. 618} 619 620def Tuples4DSpc : RegisterTuples<[dsub_0, dsub_2, dsub_4, dsub_6], 621 [(shl DPR, 0), 622 (shl DPR, 2), 623 (shl DPR, 4), 624 (shl DPR, 6)]>; 625 626// Spaced quads of D registers. 627def DQuadSpc : RegisterClass<"ARM", [v4i64], 64, (add Tuples3DSpc)>; 628 629// FP context payload 630def FPCXTRegs : RegisterClass<"ARM", [i32], 32, (add FPCXTNS)>; 631