1//===-- ARMRegisterInfo.td - ARM Register defs -------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9include "ARMSystemRegister.td" 10 11//===----------------------------------------------------------------------===// 12// Declarations that describe the ARM register file 13//===----------------------------------------------------------------------===// 14 15// Registers are identified with 4-bit ID numbers. 16class ARMReg<bits<16> Enc, string n, list<Register> subregs = [], 17 list<string> altNames = []> : Register<n, altNames> { 18 let HWEncoding = Enc; 19 let Namespace = "ARM"; 20 let SubRegs = subregs; 21 // All bits of ARM registers with sub-registers are covered by sub-registers. 22 let CoveredBySubRegs = 1; 23} 24 25class ARMFReg<bits<16> Enc, string n> : Register<n> { 26 let HWEncoding = Enc; 27 let Namespace = "ARM"; 28} 29 30let Namespace = "ARM", 31 FallbackRegAltNameIndex = NoRegAltName in { 32 def RegNamesRaw : RegAltNameIndex; 33} 34 35// Subregister indices. 36let Namespace = "ARM" in { 37def qqsub_0 : SubRegIndex<256>; 38def qqsub_1 : SubRegIndex<256, 256>; 39 40// Note: Code depends on these having consecutive numbers. 41def qsub_0 : SubRegIndex<128>; 42def qsub_1 : SubRegIndex<128, 128>; 43def qsub_2 : ComposedSubRegIndex<qqsub_1, qsub_0>; 44def qsub_3 : ComposedSubRegIndex<qqsub_1, qsub_1>; 45 46def dsub_0 : SubRegIndex<64>; 47def dsub_1 : SubRegIndex<64, 64>; 48def dsub_2 : ComposedSubRegIndex<qsub_1, dsub_0>; 49def dsub_3 : ComposedSubRegIndex<qsub_1, dsub_1>; 50def dsub_4 : ComposedSubRegIndex<qsub_2, dsub_0>; 51def dsub_5 : ComposedSubRegIndex<qsub_2, dsub_1>; 52def dsub_6 : ComposedSubRegIndex<qsub_3, dsub_0>; 53def dsub_7 : ComposedSubRegIndex<qsub_3, dsub_1>; 54 55def ssub_0 : SubRegIndex<32>; 56def ssub_1 : SubRegIndex<32, 32>; 57def ssub_2 : ComposedSubRegIndex<dsub_1, ssub_0>; 58def ssub_3 : ComposedSubRegIndex<dsub_1, ssub_1>; 59def ssub_4 : ComposedSubRegIndex<dsub_2, ssub_0>; 60def ssub_5 : ComposedSubRegIndex<dsub_2, ssub_1>; 61def ssub_6 : ComposedSubRegIndex<dsub_3, ssub_0>; 62def ssub_7 : ComposedSubRegIndex<dsub_3, ssub_1>; 63def ssub_8 : ComposedSubRegIndex<dsub_4, ssub_0>; 64def ssub_9 : ComposedSubRegIndex<dsub_4, ssub_1>; 65def ssub_10 : ComposedSubRegIndex<dsub_5, ssub_0>; 66def ssub_11 : ComposedSubRegIndex<dsub_5, ssub_1>; 67def ssub_12 : ComposedSubRegIndex<dsub_6, ssub_0>; 68def ssub_13 : ComposedSubRegIndex<dsub_6, ssub_1>; 69 70def gsub_0 : SubRegIndex<32>; 71def gsub_1 : SubRegIndex<32, 32>; 72// Let TableGen synthesize the remaining 12 ssub_* indices. 73// We don't need to name them. 74} 75 76// Integer registers 77def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>; 78def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>; 79def R2 : ARMReg< 2, "r2">, DwarfRegNum<[2]>; 80def R3 : ARMReg< 3, "r3">, DwarfRegNum<[3]>; 81def R4 : ARMReg< 4, "r4">, DwarfRegNum<[4]>; 82def R5 : ARMReg< 5, "r5">, DwarfRegNum<[5]>; 83def R6 : ARMReg< 6, "r6">, DwarfRegNum<[6]>; 84def R7 : ARMReg< 7, "r7">, DwarfRegNum<[7]>; 85// These require 32-bit instructions. 86let CostPerUse = 1 in { 87def R8 : ARMReg< 8, "r8">, DwarfRegNum<[8]>; 88def R9 : ARMReg< 9, "r9">, DwarfRegNum<[9]>; 89def R10 : ARMReg<10, "r10">, DwarfRegNum<[10]>; 90def R11 : ARMReg<11, "r11">, DwarfRegNum<[11]>; 91def R12 : ARMReg<12, "r12">, DwarfRegNum<[12]>; 92let RegAltNameIndices = [RegNamesRaw] in { 93def SP : ARMReg<13, "sp", [], ["r13"]>, DwarfRegNum<[13]>; 94def LR : ARMReg<14, "lr", [], ["r14"]>, DwarfRegNum<[14]>; 95def PC : ARMReg<15, "pc", [], ["r15"]>, DwarfRegNum<[15]>; 96} 97} 98 99// Float registers 100def S0 : ARMFReg< 0, "s0">; def S1 : ARMFReg< 1, "s1">; 101def S2 : ARMFReg< 2, "s2">; def S3 : ARMFReg< 3, "s3">; 102def S4 : ARMFReg< 4, "s4">; def S5 : ARMFReg< 5, "s5">; 103def S6 : ARMFReg< 6, "s6">; def S7 : ARMFReg< 7, "s7">; 104def S8 : ARMFReg< 8, "s8">; def S9 : ARMFReg< 9, "s9">; 105def S10 : ARMFReg<10, "s10">; def S11 : ARMFReg<11, "s11">; 106def S12 : ARMFReg<12, "s12">; def S13 : ARMFReg<13, "s13">; 107def S14 : ARMFReg<14, "s14">; def S15 : ARMFReg<15, "s15">; 108def S16 : ARMFReg<16, "s16">; def S17 : ARMFReg<17, "s17">; 109def S18 : ARMFReg<18, "s18">; def S19 : ARMFReg<19, "s19">; 110def S20 : ARMFReg<20, "s20">; def S21 : ARMFReg<21, "s21">; 111def S22 : ARMFReg<22, "s22">; def S23 : ARMFReg<23, "s23">; 112def S24 : ARMFReg<24, "s24">; def S25 : ARMFReg<25, "s25">; 113def S26 : ARMFReg<26, "s26">; def S27 : ARMFReg<27, "s27">; 114def S28 : ARMFReg<28, "s28">; def S29 : ARMFReg<29, "s29">; 115def S30 : ARMFReg<30, "s30">; def S31 : ARMFReg<31, "s31">; 116 117// Aliases of the F* registers used to hold 64-bit fp values (doubles) 118let SubRegIndices = [ssub_0, ssub_1] in { 119def D0 : ARMReg< 0, "d0", [S0, S1]>, DwarfRegNum<[256]>; 120def D1 : ARMReg< 1, "d1", [S2, S3]>, DwarfRegNum<[257]>; 121def D2 : ARMReg< 2, "d2", [S4, S5]>, DwarfRegNum<[258]>; 122def D3 : ARMReg< 3, "d3", [S6, S7]>, DwarfRegNum<[259]>; 123def D4 : ARMReg< 4, "d4", [S8, S9]>, DwarfRegNum<[260]>; 124def D5 : ARMReg< 5, "d5", [S10, S11]>, DwarfRegNum<[261]>; 125def D6 : ARMReg< 6, "d6", [S12, S13]>, DwarfRegNum<[262]>; 126def D7 : ARMReg< 7, "d7", [S14, S15]>, DwarfRegNum<[263]>; 127def D8 : ARMReg< 8, "d8", [S16, S17]>, DwarfRegNum<[264]>; 128def D9 : ARMReg< 9, "d9", [S18, S19]>, DwarfRegNum<[265]>; 129def D10 : ARMReg<10, "d10", [S20, S21]>, DwarfRegNum<[266]>; 130def D11 : ARMReg<11, "d11", [S22, S23]>, DwarfRegNum<[267]>; 131def D12 : ARMReg<12, "d12", [S24, S25]>, DwarfRegNum<[268]>; 132def D13 : ARMReg<13, "d13", [S26, S27]>, DwarfRegNum<[269]>; 133def D14 : ARMReg<14, "d14", [S28, S29]>, DwarfRegNum<[270]>; 134def D15 : ARMReg<15, "d15", [S30, S31]>, DwarfRegNum<[271]>; 135} 136 137// VFP3 defines 16 additional double registers 138def D16 : ARMFReg<16, "d16">, DwarfRegNum<[272]>; 139def D17 : ARMFReg<17, "d17">, DwarfRegNum<[273]>; 140def D18 : ARMFReg<18, "d18">, DwarfRegNum<[274]>; 141def D19 : ARMFReg<19, "d19">, DwarfRegNum<[275]>; 142def D20 : ARMFReg<20, "d20">, DwarfRegNum<[276]>; 143def D21 : ARMFReg<21, "d21">, DwarfRegNum<[277]>; 144def D22 : ARMFReg<22, "d22">, DwarfRegNum<[278]>; 145def D23 : ARMFReg<23, "d23">, DwarfRegNum<[279]>; 146def D24 : ARMFReg<24, "d24">, DwarfRegNum<[280]>; 147def D25 : ARMFReg<25, "d25">, DwarfRegNum<[281]>; 148def D26 : ARMFReg<26, "d26">, DwarfRegNum<[282]>; 149def D27 : ARMFReg<27, "d27">, DwarfRegNum<[283]>; 150def D28 : ARMFReg<28, "d28">, DwarfRegNum<[284]>; 151def D29 : ARMFReg<29, "d29">, DwarfRegNum<[285]>; 152def D30 : ARMFReg<30, "d30">, DwarfRegNum<[286]>; 153def D31 : ARMFReg<31, "d31">, DwarfRegNum<[287]>; 154 155// Advanced SIMD (NEON) defines 16 quad-word aliases 156let SubRegIndices = [dsub_0, dsub_1] in { 157def Q0 : ARMReg< 0, "q0", [D0, D1]>; 158def Q1 : ARMReg< 1, "q1", [D2, D3]>; 159def Q2 : ARMReg< 2, "q2", [D4, D5]>; 160def Q3 : ARMReg< 3, "q3", [D6, D7]>; 161def Q4 : ARMReg< 4, "q4", [D8, D9]>; 162def Q5 : ARMReg< 5, "q5", [D10, D11]>; 163def Q6 : ARMReg< 6, "q6", [D12, D13]>; 164def Q7 : ARMReg< 7, "q7", [D14, D15]>; 165} 166let SubRegIndices = [dsub_0, dsub_1] in { 167def Q8 : ARMReg< 8, "q8", [D16, D17]>; 168def Q9 : ARMReg< 9, "q9", [D18, D19]>; 169def Q10 : ARMReg<10, "q10", [D20, D21]>; 170def Q11 : ARMReg<11, "q11", [D22, D23]>; 171def Q12 : ARMReg<12, "q12", [D24, D25]>; 172def Q13 : ARMReg<13, "q13", [D26, D27]>; 173def Q14 : ARMReg<14, "q14", [D28, D29]>; 174def Q15 : ARMReg<15, "q15", [D30, D31]>; 175} 176 177// Current Program Status Register. 178// We model fpscr with two registers: FPSCR models the control bits and will be 179// reserved. FPSCR_NZCV models the flag bits and will be unreserved. APSR_NZCV 180// models the APSR when it's accessed by some special instructions. In such cases 181// it has the same encoding as PC. 182def CPSR : ARMReg<0, "cpsr">; 183def APSR : ARMReg<15, "apsr">; 184def APSR_NZCV : ARMReg<15, "apsr_nzcv">; 185def SPSR : ARMReg<2, "spsr">; 186def FPSCR : ARMReg<3, "fpscr">; 187def FPSCR_NZCV : ARMReg<3, "fpscr_nzcv"> { 188 let Aliases = [FPSCR]; 189} 190def ITSTATE : ARMReg<4, "itstate">; 191 192// Special Registers - only available in privileged mode. 193def FPSID : ARMReg<0, "fpsid">; 194def MVFR2 : ARMReg<5, "mvfr2">; 195def MVFR1 : ARMReg<6, "mvfr1">; 196def MVFR0 : ARMReg<7, "mvfr0">; 197def FPEXC : ARMReg<8, "fpexc">; 198def FPINST : ARMReg<9, "fpinst">; 199def FPINST2 : ARMReg<10, "fpinst2">; 200// These encodings aren't actual instruction encodings, their encoding depends 201// on the instruction they are used in and for VPR 32 was chosen such that it 202// always comes last in spr_reglist_with_vpr. 203def VPR : ARMReg<32, "vpr">; 204def FPSCR_NZCVQC 205 : ARMReg<2, "fpscr_nzcvqc">; 206def P0 : ARMReg<13, "p0">; 207def FPCXTNS : ARMReg<14, "fpcxtns">; 208def FPCXTS : ARMReg<15, "fpcxts">; 209 210def ZR : ARMReg<15, "zr">, DwarfRegNum<[15]>; 211 212// Register classes. 213// 214// pc == Program Counter 215// lr == Link Register 216// sp == Stack Pointer 217// r12 == ip (scratch) 218// r7 == Frame Pointer (thumb-style backtraces) 219// r9 == May be reserved as Thread Register 220// r11 == Frame Pointer (arm-style backtraces) 221// r10 == Stack Limit 222// 223def GPR : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12), 224 SP, LR, PC)> { 225 // Allocate LR as the first CSR since it is always saved anyway. 226 // For Thumb1 mode, we don't want to allocate hi regs at all, as we don't 227 // know how to spill them. If we make our prologue/epilogue code smarter at 228 // some point, we can go back to using the above allocation orders for the 229 // Thumb1 instructions that know how to use hi regs. 230 let AltOrders = [(add LR, GPR), (trunc GPR, 8), 231 (add (trunc GPR, 8), R12, LR, (shl GPR, 8))]; 232 let AltOrderSelect = [{ 233 return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF); 234 }]; 235 let DiagnosticString = "operand must be a register in range [r0, r15]"; 236} 237 238// GPRs without the PC. Some ARM instructions do not allow the PC in 239// certain operand slots, particularly as the destination. Primarily 240// useful for disassembly. 241def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> { 242 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8), 243 (add (trunc GPRnopc, 8), R12, LR, (shl GPRnopc, 8))]; 244 let AltOrderSelect = [{ 245 return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF); 246 }]; 247 let DiagnosticString = "operand must be a register in range [r0, r14]"; 248} 249 250// GPRs without the PC but with APSR. Some instructions allow accessing the 251// APSR, while actually encoding PC in the register field. This is useful 252// for assembly and disassembly only. 253def GPRwithAPSR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), APSR_NZCV)> { 254 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)]; 255 let AltOrderSelect = [{ 256 return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only(); 257 }]; 258 let DiagnosticString = "operand must be a register in range [r0, r14] or apsr_nzcv"; 259} 260 261// GPRs without the PC and SP registers but with APSR. Used by CLRM instruction. 262def GPRwithAPSRnosp : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12), LR, APSR)> { 263 let isAllocatable = 0; 264} 265 266def GPRwithZR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), ZR)> { 267 let AltOrders = [(add LR, GPRwithZR), (trunc GPRwithZR, 8)]; 268 let AltOrderSelect = [{ 269 return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only(); 270 }]; 271 let DiagnosticString = "operand must be a register in range [r0, r14] or zr"; 272} 273 274def GPRwithZRnosp : RegisterClass<"ARM", [i32], 32, (sub GPRwithZR, SP)> { 275 let AltOrders = [(add LR, GPRwithZRnosp), (trunc GPRwithZRnosp, 8)]; 276 let AltOrderSelect = [{ 277 return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only(); 278 }]; 279 let DiagnosticString = "operand must be a register in range [r0, r12] or r14 or zr"; 280} 281 282// GPRsp - Only the SP is legal. Used by Thumb1 instructions that want the 283// implied SP argument list. 284// FIXME: It would be better to not use this at all and refactor the 285// instructions to not have SP an an explicit argument. That makes 286// frame index resolution a bit trickier, though. 287def GPRsp : RegisterClass<"ARM", [i32], 32, (add SP)> { 288 let DiagnosticString = "operand must be a register sp"; 289} 290 291// GPRlr - Only LR is legal. Used by ARMv8.1-M Low Overhead Loop instructions 292// where LR is the only legal loop counter register. 293def GPRlr : RegisterClass<"ARM", [i32], 32, (add LR)>; 294 295// restricted GPR register class. Many Thumb2 instructions allow the full 296// register range for operands, but have undefined behaviours when PC 297// or SP (R13 or R15) are used. The ARM ISA refers to these operands 298// via the BadReg() pseudo-code description. 299def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> { 300 let AltOrders = [(add LR, rGPR), (trunc rGPR, 8), 301 (add (trunc rGPR, 8), R12, LR, (shl rGPR, 8))]; 302 let AltOrderSelect = [{ 303 return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF); 304 }]; 305 let DiagnosticType = "rGPR"; 306} 307 308// Thumb registers are R0-R7 normally. Some instructions can still use 309// the general GPR register class above (MOV, e.g.) 310def tGPR : RegisterClass<"ARM", [i32], 32, (trunc GPR, 8)> { 311 let DiagnosticString = "operand must be a register in range [r0, r7]"; 312} 313 314// Thumb registers R0-R7 and the PC. Some instructions like TBB or THH allow 315// the PC to be used as a destination operand as well. 316def tGPRwithpc : RegisterClass<"ARM", [i32], 32, (add tGPR, PC)>; 317 318// The high registers in thumb mode, R8-R15. 319def hGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, tGPR)> { 320 let DiagnosticString = "operand must be a register in range [r8, r15]"; 321} 322 323// For tail calls, we can't use callee-saved registers, as they are restored 324// to the saved value before the tail call, which would clobber a call address. 325// Note, getMinimalPhysRegClass(R0) returns tGPR because of the names of 326// this class and the preceding one(!) This is what we want. 327def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R12)> { 328 let AltOrders = [(and tcGPR, tGPR)]; 329 let AltOrderSelect = [{ 330 return MF.getSubtarget<ARMSubtarget>().isThumb1Only(); 331 }]; 332} 333 334def tGPROdd : RegisterClass<"ARM", [i32], 32, (add R1, R3, R5, R7, R9, R11)> { 335 let AltOrders = [(and tGPROdd, tGPR)]; 336 let AltOrderSelect = [{ 337 return MF.getSubtarget<ARMSubtarget>().isThumb1Only(); 338 }]; 339 let DiagnosticString = 340 "operand must be an odd-numbered register in range [r1,r11]"; 341} 342 343def tGPREven : RegisterClass<"ARM", [i32], 32, (add R0, R2, R4, R6, R8, R10, R12, LR)> { 344 let AltOrders = [(and tGPREven, tGPR)]; 345 let AltOrderSelect = [{ 346 return MF.getSubtarget<ARMSubtarget>().isThumb1Only(); 347 }]; 348 let DiagnosticString = "operand must be an even-numbered register"; 349} 350 351// Condition code registers. 352def CCR : RegisterClass<"ARM", [i32], 32, (add CPSR)> { 353 let CopyCost = -1; // Don't allow copying of status registers. 354 let isAllocatable = 0; 355} 356 357// MVE Condition code register. 358def VCCR : RegisterClass<"ARM", [i32, v16i1, v8i1, v4i1], 32, (add VPR)> { 359// let CopyCost = -1; // Don't allow copying of status registers. 360} 361 362// FPSCR, when the flags at the top of it are used as the input or 363// output to an instruction such as MVE VADC. 364def cl_FPSCR_NZCV : RegisterClass<"ARM", [i32], 32, (add FPSCR_NZCV)>; 365 366// Scalar single precision floating point register class.. 367// FIXME: Allocation order changed to s0, s2, ... or s0, s4, ... as a quick hack 368// to avoid partial-write dependencies on D or Q (depending on platform) 369// registers (S registers are renamed as portions of D/Q registers). 370def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> { 371 let AltOrders = [(add (decimate SPR, 2), SPR), 372 (add (decimate SPR, 4), 373 (decimate SPR, 2), 374 (decimate (rotl SPR, 1), 4), 375 (decimate (rotl SPR, 1), 2))]; 376 let AltOrderSelect = [{ 377 return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs(); 378 }]; 379 let DiagnosticString = "operand must be a register in range [s0, s31]"; 380} 381 382def HPR : RegisterClass<"ARM", [f16], 32, (sequence "S%u", 0, 31)> { 383 let AltOrders = [(add (decimate HPR, 2), SPR), 384 (add (decimate HPR, 4), 385 (decimate HPR, 2), 386 (decimate (rotl HPR, 1), 4), 387 (decimate (rotl HPR, 1), 2))]; 388 let AltOrderSelect = [{ 389 return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs(); 390 }]; 391 let DiagnosticString = "operand must be a register in range [s0, s31]"; 392} 393 394// Subset of SPR which can be used as a source of NEON scalars for 16-bit 395// operations 396def SPR_8 : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 15)> { 397 let DiagnosticString = "operand must be a register in range [s0, s15]"; 398} 399 400// Scalar double precision floating point / generic 64-bit vector register 401// class. 402// ARM requires only word alignment for double. It's more performant if it 403// is double-word alignment though. 404def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16], 64, 405 (sequence "D%u", 0, 31)> { 406 // Allocate non-VFP2 registers D16-D31 first, and prefer even registers on 407 // Darwin platforms. 408 let AltOrders = [(rotl DPR, 16), 409 (add (decimate (rotl DPR, 16), 2), (rotl DPR, 16))]; 410 let AltOrderSelect = [{ 411 return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs(); 412 }]; 413 let DiagnosticType = "DPR"; 414} 415 416// Scalar single and double precision floating point and VPR register class, 417// this is only used for parsing, don't use it anywhere else as the size and 418// types don't match! 419def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> { 420 let isAllocatable = 0; 421} 422 423// Subset of DPR that are accessible with VFP2 (and so that also have 424// 32-bit SPR subregs). 425def DPR_VFP2 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16], 64, 426 (trunc DPR, 16)> { 427 let DiagnosticString = "operand must be a register in range [d0, d15]"; 428} 429 430// Subset of DPR which can be used as a source of NEON scalars for 16-bit 431// operations 432def DPR_8 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16], 64, 433 (trunc DPR, 8)> { 434 let DiagnosticString = "operand must be a register in range [d0, d7]"; 435} 436 437// Generic 128-bit vector register class. 438def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16], 128, 439 (sequence "Q%u", 0, 15)> { 440 // Allocate non-VFP2 aliases Q8-Q15 first. 441 let AltOrders = [(rotl QPR, 8), (trunc QPR, 8)]; 442 let AltOrderSelect = [{ 443 return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps(); 444 }]; 445 let DiagnosticString = "operand must be a register in range [q0, q15]"; 446} 447 448// Subset of QPR that have 32-bit SPR subregs. 449def QPR_VFP2 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 450 128, (trunc QPR, 8)> { 451 let DiagnosticString = "operand must be a register in range [q0, q7]"; 452} 453 454// Subset of QPR that have DPR_8 and SPR_8 subregs. 455def QPR_8 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 456 128, (trunc QPR, 4)> { 457 let DiagnosticString = "operand must be a register in range [q0, q3]"; 458} 459 460// MVE 128-bit vector register class. This class is only really needed for 461// parsing assembly, since we still have to truncate the register set in the QPR 462// class anyway. 463def MQPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16], 464 128, (trunc QPR, 8)>; 465 466// Pseudo-registers representing odd-even pairs of D registers. The even-odd 467// pairs are already represented by the Q registers. 468// These are needed by NEON instructions requiring two consecutive D registers. 469// There is no D31_D0 register as that is always an UNPREDICTABLE encoding. 470def TuplesOE2D : RegisterTuples<[dsub_0, dsub_1], 471 [(decimate (shl DPR, 1), 2), 472 (decimate (shl DPR, 2), 2)]>; 473 474// Register class representing a pair of consecutive D registers. 475// Use the Q registers for the even-odd pairs. 476def DPair : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 477 128, (interleave QPR, TuplesOE2D)> { 478 // Allocate starting at non-VFP2 registers D16-D31 first. 479 // Prefer even-odd pairs as they are easier to copy. 480 let AltOrders = [(add (rotl QPR, 8), (rotl DPair, 16)), 481 (add (trunc QPR, 8), (trunc DPair, 16))]; 482 let AltOrderSelect = [{ 483 return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps(); 484 }]; 485} 486 487// Pseudo-registers representing even-odd pairs of GPRs from R1 to R13/SP. 488// These are needed by instructions (e.g. ldrexd/strexd) requiring even-odd GPRs. 489def Tuples2Rnosp : RegisterTuples<[gsub_0, gsub_1], 490 [(add R0, R2, R4, R6, R8, R10), 491 (add R1, R3, R5, R7, R9, R11)]>; 492 493def Tuples2Rsp : RegisterTuples<[gsub_0, gsub_1], 494 [(add R12), (add SP)]>; 495 496// Register class representing a pair of even-odd GPRs. 497def GPRPair : RegisterClass<"ARM", [untyped], 64, (add Tuples2Rnosp, Tuples2Rsp)> { 498 let Size = 64; // 2 x 32 bits, we have no predefined type of that size. 499} 500 501// Register class representing a pair of even-odd GPRs, except (R12, SP). 502def GPRPairnosp : RegisterClass<"ARM", [untyped], 64, (add Tuples2Rnosp)> { 503 let Size = 64; // 2 x 32 bits, we have no predefined type of that size. 504} 505 506// Pseudo-registers representing 3 consecutive D registers. 507def Tuples3D : RegisterTuples<[dsub_0, dsub_1, dsub_2], 508 [(shl DPR, 0), 509 (shl DPR, 1), 510 (shl DPR, 2)]>; 511 512// 3 consecutive D registers. 513def DTriple : RegisterClass<"ARM", [untyped], 64, (add Tuples3D)> { 514 let Size = 192; // 3 x 64 bits, we have no predefined type of that size. 515} 516 517// Pseudo 256-bit registers to represent pairs of Q registers. These should 518// never be present in the emitted code. 519// These are used for NEON load / store instructions, e.g., vld4, vst3. 520def Tuples2Q : RegisterTuples<[qsub_0, qsub_1], [(shl QPR, 0), (shl QPR, 1)]>; 521 522// Pseudo 256-bit vector register class to model pairs of Q registers 523// (4 consecutive D registers). 524def QQPR : RegisterClass<"ARM", [v4i64], 256, (add Tuples2Q)> { 525 // Allocate non-VFP2 aliases first. 526 let AltOrders = [(rotl QQPR, 8)]; 527 let AltOrderSelect = [{ return 1; }]; 528} 529 530// Tuples of 4 D regs that isn't also a pair of Q regs. 531def TuplesOE4D : RegisterTuples<[dsub_0, dsub_1, dsub_2, dsub_3], 532 [(decimate (shl DPR, 1), 2), 533 (decimate (shl DPR, 2), 2), 534 (decimate (shl DPR, 3), 2), 535 (decimate (shl DPR, 4), 2)]>; 536 537// 4 consecutive D registers. 538def DQuad : RegisterClass<"ARM", [v4i64], 256, 539 (interleave Tuples2Q, TuplesOE4D)>; 540 541// Pseudo 512-bit registers to represent four consecutive Q registers. 542def Tuples2QQ : RegisterTuples<[qqsub_0, qqsub_1], 543 [(shl QQPR, 0), (shl QQPR, 2)]>; 544 545// Pseudo 512-bit vector register class to model 4 consecutive Q registers 546// (8 consecutive D registers). 547def QQQQPR : RegisterClass<"ARM", [v8i64], 256, (add Tuples2QQ)> { 548 // Allocate non-VFP2 aliases first. 549 let AltOrders = [(rotl QQQQPR, 8)]; 550 let AltOrderSelect = [{ return 1; }]; 551} 552 553 554// Pseudo-registers representing 2-spaced consecutive D registers. 555def Tuples2DSpc : RegisterTuples<[dsub_0, dsub_2], 556 [(shl DPR, 0), 557 (shl DPR, 2)]>; 558 559// Spaced pairs of D registers. 560def DPairSpc : RegisterClass<"ARM", [v2i64], 64, (add Tuples2DSpc)>; 561 562def Tuples3DSpc : RegisterTuples<[dsub_0, dsub_2, dsub_4], 563 [(shl DPR, 0), 564 (shl DPR, 2), 565 (shl DPR, 4)]>; 566 567// Spaced triples of D registers. 568def DTripleSpc : RegisterClass<"ARM", [untyped], 64, (add Tuples3DSpc)> { 569 let Size = 192; // 3 x 64 bits, we have no predefined type of that size. 570} 571 572def Tuples4DSpc : RegisterTuples<[dsub_0, dsub_2, dsub_4, dsub_6], 573 [(shl DPR, 0), 574 (shl DPR, 2), 575 (shl DPR, 4), 576 (shl DPR, 6)]>; 577 578// Spaced quads of D registers. 579def DQuadSpc : RegisterClass<"ARM", [v4i64], 64, (add Tuples3DSpc)>; 580