1 //===- ARMSLSHardening.cpp - Harden Straight Line Missspeculation ---------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a pass to insert code to mitigate against side channel
10 // vulnerabilities that may happen under straight line miss-speculation.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARM.h"
15 #include "ARMInstrInfo.h"
16 #include "ARMSubtarget.h"
17 #include "llvm/CodeGen/IndirectThunks.h"
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineOperand.h"
24 #include "llvm/IR/DebugLoc.h"
25 #include <cassert>
26 
27 using namespace llvm;
28 
29 #define DEBUG_TYPE "arm-sls-hardening"
30 
31 #define ARM_SLS_HARDENING_NAME "ARM sls hardening pass"
32 
33 namespace {
34 
35 class ARMSLSHardening : public MachineFunctionPass {
36 public:
37   const TargetInstrInfo *TII;
38   const ARMSubtarget *ST;
39 
40   static char ID;
41 
42   ARMSLSHardening() : MachineFunctionPass(ID) {
43     initializeARMSLSHardeningPass(*PassRegistry::getPassRegistry());
44   }
45 
46   bool runOnMachineFunction(MachineFunction &Fn) override;
47 
48   StringRef getPassName() const override { return ARM_SLS_HARDENING_NAME; }
49 
50   void getAnalysisUsage(AnalysisUsage &AU) const override {
51     AU.setPreservesCFG();
52     MachineFunctionPass::getAnalysisUsage(AU);
53   }
54 
55 private:
56   bool hardenReturnsAndBRs(MachineBasicBlock &MBB) const;
57   bool hardenIndirectCalls(MachineBasicBlock &MBB) const;
58   MachineBasicBlock &
59   ConvertIndirectCallToIndirectJump(MachineBasicBlock &MBB,
60                                     MachineBasicBlock::iterator) const;
61 };
62 
63 } // end anonymous namespace
64 
65 char ARMSLSHardening::ID = 0;
66 
67 INITIALIZE_PASS(ARMSLSHardening, "arm-sls-hardening",
68                 ARM_SLS_HARDENING_NAME, false, false)
69 
70 static void insertSpeculationBarrier(const ARMSubtarget *ST,
71                                      MachineBasicBlock &MBB,
72                                      MachineBasicBlock::iterator MBBI,
73                                      DebugLoc DL,
74                                      bool AlwaysUseISBDSB = false) {
75   assert(MBBI != MBB.begin() &&
76          "Must not insert SpeculationBarrierEndBB as only instruction in MBB.");
77   assert(std::prev(MBBI)->isBarrier() &&
78          "SpeculationBarrierEndBB must only follow unconditional control flow "
79          "instructions.");
80   assert(std::prev(MBBI)->isTerminator() &&
81          "SpeculationBarrierEndBB must only follow terminators.");
82   const TargetInstrInfo *TII = ST->getInstrInfo();
83   assert(ST->hasDataBarrier() || ST->hasSB());
84   bool ProduceSB = ST->hasSB() && !AlwaysUseISBDSB;
85   unsigned BarrierOpc =
86       ProduceSB ? (ST->isThumb() ? ARM::t2SpeculationBarrierSBEndBB
87                                  : ARM::SpeculationBarrierSBEndBB)
88                 : (ST->isThumb() ? ARM::t2SpeculationBarrierISBDSBEndBB
89                                  : ARM::SpeculationBarrierISBDSBEndBB);
90   if (MBBI == MBB.end() || !isSpeculationBarrierEndBBOpcode(MBBI->getOpcode()))
91     BuildMI(MBB, MBBI, DL, TII->get(BarrierOpc));
92 }
93 
94 bool ARMSLSHardening::runOnMachineFunction(MachineFunction &MF) {
95   ST = &MF.getSubtarget<ARMSubtarget>();
96   TII = MF.getSubtarget().getInstrInfo();
97 
98   bool Modified = false;
99   for (auto &MBB : MF) {
100     Modified |= hardenReturnsAndBRs(MBB);
101     Modified |= hardenIndirectCalls(MBB);
102   }
103 
104   return Modified;
105 }
106 
107 bool ARMSLSHardening::hardenReturnsAndBRs(MachineBasicBlock &MBB) const {
108   if (!ST->hardenSlsRetBr())
109     return false;
110   assert(!ST->isThumb1Only());
111   bool Modified = false;
112   MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator(), E = MBB.end();
113   MachineBasicBlock::iterator NextMBBI;
114   for (; MBBI != E; MBBI = NextMBBI) {
115     MachineInstr &MI = *MBBI;
116     NextMBBI = std::next(MBBI);
117     if (isIndirectControlFlowNotComingBack(MI)) {
118       assert(MI.isTerminator());
119       assert(!TII->isPredicated(MI));
120       insertSpeculationBarrier(ST, MBB, std::next(MBBI), MI.getDebugLoc());
121       Modified = true;
122     }
123   }
124   return Modified;
125 }
126 
127 static const char SLSBLRNamePrefix[] = "__llvm_slsblr_thunk_";
128 
129 static const struct ThunkNameRegMode {
130   const char* Name;
131   Register Reg;
132   bool isThumb;
133 } SLSBLRThunks[] = {
134     {"__llvm_slsblr_thunk_arm_r0", ARM::R0, false},
135     {"__llvm_slsblr_thunk_arm_r1", ARM::R1, false},
136     {"__llvm_slsblr_thunk_arm_r2", ARM::R2, false},
137     {"__llvm_slsblr_thunk_arm_r3", ARM::R3, false},
138     {"__llvm_slsblr_thunk_arm_r4", ARM::R4, false},
139     {"__llvm_slsblr_thunk_arm_r5", ARM::R5, false},
140     {"__llvm_slsblr_thunk_arm_r6", ARM::R6, false},
141     {"__llvm_slsblr_thunk_arm_r7", ARM::R7, false},
142     {"__llvm_slsblr_thunk_arm_r8", ARM::R8, false},
143     {"__llvm_slsblr_thunk_arm_r9", ARM::R9, false},
144     {"__llvm_slsblr_thunk_arm_r10", ARM::R10, false},
145     {"__llvm_slsblr_thunk_arm_r11", ARM::R11, false},
146     {"__llvm_slsblr_thunk_arm_sp", ARM::SP, false},
147     {"__llvm_slsblr_thunk_arm_pc", ARM::PC, false},
148     {"__llvm_slsblr_thunk_thumb_r0", ARM::R0, true},
149     {"__llvm_slsblr_thunk_thumb_r1", ARM::R1, true},
150     {"__llvm_slsblr_thunk_thumb_r2", ARM::R2, true},
151     {"__llvm_slsblr_thunk_thumb_r3", ARM::R3, true},
152     {"__llvm_slsblr_thunk_thumb_r4", ARM::R4, true},
153     {"__llvm_slsblr_thunk_thumb_r5", ARM::R5, true},
154     {"__llvm_slsblr_thunk_thumb_r6", ARM::R6, true},
155     {"__llvm_slsblr_thunk_thumb_r7", ARM::R7, true},
156     {"__llvm_slsblr_thunk_thumb_r8", ARM::R8, true},
157     {"__llvm_slsblr_thunk_thumb_r9", ARM::R9, true},
158     {"__llvm_slsblr_thunk_thumb_r10", ARM::R10, true},
159     {"__llvm_slsblr_thunk_thumb_r11", ARM::R11, true},
160     {"__llvm_slsblr_thunk_thumb_sp", ARM::SP, true},
161     {"__llvm_slsblr_thunk_thumb_pc", ARM::PC, true},
162 };
163 
164 namespace {
165 struct SLSBLRThunkInserter : ThunkInserter<SLSBLRThunkInserter> {
166   const char *getThunkPrefix() { return SLSBLRNamePrefix; }
167   bool mayUseThunk(const MachineFunction &MF) {
168     // FIXME: This could also check if there are any indirect calls in the
169     // function to more accurately reflect if a thunk will be needed.
170     return MF.getSubtarget<ARMSubtarget>().hardenSlsBlr();
171   }
172   void insertThunks(MachineModuleInfo &MMI);
173   void populateThunk(MachineFunction &MF);
174 };
175 } // namespace
176 
177 void SLSBLRThunkInserter::insertThunks(MachineModuleInfo &MMI) {
178   // FIXME: It probably would be possible to filter which thunks to produce
179   // based on which registers are actually used in indirect calls in this
180   // function. But would that be a worthwhile optimization?
181   for (auto T : SLSBLRThunks)
182     createThunkFunction(MMI, T.Name);
183 }
184 
185 void SLSBLRThunkInserter::populateThunk(MachineFunction &MF) {
186   // FIXME: How to better communicate Register number, rather than through
187   // name and lookup table?
188   assert(MF.getName().startswith(getThunkPrefix()));
189   auto ThunkIt = llvm::find_if(
190       SLSBLRThunks, [&MF](auto T) { return T.Name == MF.getName(); });
191   assert(ThunkIt != std::end(SLSBLRThunks));
192   Register ThunkReg = ThunkIt->Reg;
193   bool isThumb = ThunkIt->isThumb;
194 
195   const TargetInstrInfo *TII = MF.getSubtarget<ARMSubtarget>().getInstrInfo();
196   MachineBasicBlock *Entry = &MF.front();
197   Entry->clear();
198 
199   //  These thunks need to consist of the following instructions:
200   //  __llvm_slsblr_thunk_(arm/thumb)_rN:
201   //      bx  rN
202   //      barrierInsts
203   Entry->addLiveIn(ThunkReg);
204   if (isThumb)
205     BuildMI(Entry, DebugLoc(), TII->get(ARM::tBX))
206         .addReg(ThunkReg)
207         .add(predOps(ARMCC::AL));
208   else
209     BuildMI(Entry, DebugLoc(), TII->get(ARM::BX))
210         .addReg(ThunkReg);
211 
212   // Make sure the thunks do not make use of the SB extension in case there is
213   // a function somewhere that will call to it that for some reason disabled
214   // the SB extension locally on that function, even though it's enabled for
215   // the module otherwise. Therefore set AlwaysUseISBSDB to true.
216   insertSpeculationBarrier(&MF.getSubtarget<ARMSubtarget>(), *Entry,
217                            Entry->end(), DebugLoc(), true /*AlwaysUseISBDSB*/);
218 }
219 
220 MachineBasicBlock &ARMSLSHardening::ConvertIndirectCallToIndirectJump(
221     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
222   // Transform an indirect call to an indirect jump as follows:
223   // Before:
224   //   |-----------------------------|
225   //   |      ...                    |
226   //   |  instI                      |
227   //   |  BLX rN                     |
228   //   |  instJ                      |
229   //   |      ...                    |
230   //   |-----------------------------|
231   //
232   // After:
233   //   |----------   -------------------------|
234   //   |      ...                             |
235   //   |  instI                               |
236   //   |  *call* __llvm_slsblr_thunk_mode_xN  |
237   //   |  instJ                               |
238   //   |      ...                             |
239   //   |--------------------------------------|
240   //
241   //   __llvm_slsblr_thunk_mode_xN:
242   //   |-----------------------------|
243   //   |  BX rN                      |
244   //   |  barrierInsts               |
245   //   |-----------------------------|
246   //
247   // The __llvm_slsblr_thunk_mode_xN thunks are created by the
248   // SLSBLRThunkInserter.
249   // This function merely needs to transform an indirect call to a direct call
250   // to __llvm_slsblr_thunk_xN.
251   MachineInstr &IndirectCall = *MBBI;
252   assert(isIndirectCall(IndirectCall) && !IndirectCall.isReturn());
253   int RegOpIdxOnIndirectCall = -1;
254   bool isThumb;
255   switch (IndirectCall.getOpcode()) {
256   case ARM::BLX:   // !isThumb2
257   case ARM::BLX_noip:   // !isThumb2
258     isThumb = false;
259     RegOpIdxOnIndirectCall = 0;
260     break;
261   case ARM::tBLXr:      // isThumb2
262   case ARM::tBLXr_noip: // isThumb2
263     isThumb = true;
264     RegOpIdxOnIndirectCall = 2;
265     break;
266   default:
267     llvm_unreachable("unhandled Indirect Call");
268   }
269 
270   Register Reg = IndirectCall.getOperand(RegOpIdxOnIndirectCall).getReg();
271   // Since linkers are allowed to clobber R12 on function calls, the above
272   // mitigation only works if the original indirect call instruction was not
273   // using R12. Code generation before must make sure that no indirect call
274   // using R12 was produced if the mitigation is enabled.
275   // Also, the transformation is incorrect if the indirect call uses LR, so
276   // also have to avoid that.
277   assert(Reg != ARM::R12 && Reg != ARM::LR);
278   bool RegIsKilled = IndirectCall.getOperand(RegOpIdxOnIndirectCall).isKill();
279 
280   DebugLoc DL = IndirectCall.getDebugLoc();
281 
282   MachineFunction &MF = *MBBI->getMF();
283   auto ThunkIt = llvm::find_if(SLSBLRThunks, [Reg, isThumb](auto T) {
284     return T.Reg == Reg && T.isThumb == isThumb;
285   });
286   assert(ThunkIt != std::end(SLSBLRThunks));
287   Module *M = MF.getFunction().getParent();
288   const GlobalValue *GV = cast<GlobalValue>(M->getNamedValue(ThunkIt->Name));
289 
290   MachineInstr *BL =
291       isThumb ? BuildMI(MBB, MBBI, DL, TII->get(ARM::tBL))
292                     .addImm(IndirectCall.getOperand(0).getImm())
293                     .addReg(IndirectCall.getOperand(1).getReg())
294                     .addGlobalAddress(GV)
295               : BuildMI(MBB, MBBI, DL, TII->get(ARM::BL)).addGlobalAddress(GV);
296 
297   // Now copy the implicit operands from IndirectCall to BL and copy other
298   // necessary info.
299   // However, both IndirectCall and BL instructions implictly use SP and
300   // implicitly define LR. Blindly copying implicit operands would result in SP
301   // and LR operands to be present multiple times. While this may not be too
302   // much of an issue, let's avoid that for cleanliness, by removing those
303   // implicit operands from the BL created above before we copy over all
304   // implicit operands from the IndirectCall.
305   int ImpLROpIdx = -1;
306   int ImpSPOpIdx = -1;
307   for (unsigned OpIdx = BL->getNumExplicitOperands();
308        OpIdx < BL->getNumOperands(); OpIdx++) {
309     MachineOperand Op = BL->getOperand(OpIdx);
310     if (!Op.isReg())
311       continue;
312     if (Op.getReg() == ARM::LR && Op.isDef())
313       ImpLROpIdx = OpIdx;
314     if (Op.getReg() == ARM::SP && !Op.isDef())
315       ImpSPOpIdx = OpIdx;
316   }
317   assert(ImpLROpIdx != -1);
318   assert(ImpSPOpIdx != -1);
319   int FirstOpIdxToRemove = std::max(ImpLROpIdx, ImpSPOpIdx);
320   int SecondOpIdxToRemove = std::min(ImpLROpIdx, ImpSPOpIdx);
321   BL->RemoveOperand(FirstOpIdxToRemove);
322   BL->RemoveOperand(SecondOpIdxToRemove);
323   // Now copy over the implicit operands from the original IndirectCall
324   BL->copyImplicitOps(MF, IndirectCall);
325   MF.moveCallSiteInfo(&IndirectCall, BL);
326   // Also add the register called in the IndirectCall as being used in the
327   // called thunk.
328   BL->addOperand(MachineOperand::CreateReg(Reg, false /*isDef*/, true /*isImp*/,
329                                            RegIsKilled /*isKill*/));
330   // Remove IndirectCallinstruction
331   MBB.erase(MBBI);
332   return MBB;
333 }
334 
335 bool ARMSLSHardening::hardenIndirectCalls(MachineBasicBlock &MBB) const {
336   if (!ST->hardenSlsBlr())
337     return false;
338   bool Modified = false;
339   MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
340   MachineBasicBlock::iterator NextMBBI;
341   for (; MBBI != E; MBBI = NextMBBI) {
342     MachineInstr &MI = *MBBI;
343     NextMBBI = std::next(MBBI);
344     // Tail calls are both indirect calls and "returns".
345     // They are also indirect jumps, so should be handled by sls-harden-retbr,
346     // rather than sls-harden-blr.
347     if (isIndirectCall(MI) && !MI.isReturn()) {
348       ConvertIndirectCallToIndirectJump(MBB, MBBI);
349       Modified = true;
350     }
351   }
352   return Modified;
353 }
354 
355 
356 
357 FunctionPass *llvm::createARMSLSHardeningPass() {
358   return new ARMSLSHardening();
359 }
360 
361 namespace {
362 class ARMIndirectThunks : public MachineFunctionPass {
363 public:
364   static char ID;
365 
366   ARMIndirectThunks() : MachineFunctionPass(ID) {}
367 
368   StringRef getPassName() const override { return "ARM Indirect Thunks"; }
369 
370   bool doInitialization(Module &M) override;
371   bool runOnMachineFunction(MachineFunction &MF) override;
372 
373   void getAnalysisUsage(AnalysisUsage &AU) const override {
374     MachineFunctionPass::getAnalysisUsage(AU);
375     AU.addRequired<MachineModuleInfoWrapperPass>();
376     AU.addPreserved<MachineModuleInfoWrapperPass>();
377   }
378 
379 private:
380   std::tuple<SLSBLRThunkInserter> TIs;
381 
382   // FIXME: When LLVM moves to C++17, these can become folds
383   template <typename... ThunkInserterT>
384   static void initTIs(Module &M,
385                       std::tuple<ThunkInserterT...> &ThunkInserters) {
386     (void)std::initializer_list<int>{
387         (std::get<ThunkInserterT>(ThunkInserters).init(M), 0)...};
388   }
389   template <typename... ThunkInserterT>
390   static bool runTIs(MachineModuleInfo &MMI, MachineFunction &MF,
391                      std::tuple<ThunkInserterT...> &ThunkInserters) {
392     bool Modified = false;
393     (void)std::initializer_list<int>{
394         Modified |= std::get<ThunkInserterT>(ThunkInserters).run(MMI, MF)...};
395     return Modified;
396   }
397 };
398 
399 } // end anonymous namespace
400 
401 char ARMIndirectThunks::ID = 0;
402 
403 FunctionPass *llvm::createARMIndirectThunks() {
404   return new ARMIndirectThunks();
405 }
406 
407 bool ARMIndirectThunks::doInitialization(Module &M) {
408   initTIs(M, TIs);
409   return false;
410 }
411 
412 bool ARMIndirectThunks::runOnMachineFunction(MachineFunction &MF) {
413   LLVM_DEBUG(dbgs() << getPassName() << '\n');
414   auto &MMI = getAnalysis<MachineModuleInfoWrapperPass>().getMMI();
415   return runTIs(MMI, MF, TIs);
416 }
417