1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "ARMTargetMachine.h"
13 #include "ARM.h"
14 #include "ARMMacroFusion.h"
15 #include "ARMSubtarget.h"
16 #include "ARMTargetObjectFile.h"
17 #include "ARMTargetTransformInfo.h"
18 #include "MCTargetDesc/ARMMCTargetDesc.h"
19 #include "TargetInfo/ARMTargetInfo.h"
20 #include "llvm/ADT/Optional.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/Analysis/TargetTransformInfo.h"
25 #include "llvm/CodeGen/ExecutionDomainFix.h"
26 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
27 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
28 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
29 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
30 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
31 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
32 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
33 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineScheduler.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/TargetPassConfig.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/Pass.h"
42 #include "llvm/Support/CodeGen.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/ErrorHandling.h"
45 #include "llvm/Support/TargetParser.h"
46 #include "llvm/Support/TargetRegistry.h"
47 #include "llvm/Target/TargetLoweringObjectFile.h"
48 #include "llvm/Target/TargetOptions.h"
49 #include "llvm/Transforms/CFGuard.h"
50 #include "llvm/Transforms/IPO.h"
51 #include "llvm/Transforms/Scalar.h"
52 #include <cassert>
53 #include <memory>
54 #include <string>
55 
56 using namespace llvm;
57 
58 static cl::opt<bool>
59 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
60                    cl::desc("Inhibit optimization of S->D register accesses on A15"),
61                    cl::init(false));
62 
63 static cl::opt<bool>
64 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
65                  cl::desc("Run SimplifyCFG after expanding atomic operations"
66                           " to make use of cmpxchg flow-based information"),
67                  cl::init(true));
68 
69 static cl::opt<bool>
70 EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
71                       cl::desc("Enable ARM load/store optimization pass"),
72                       cl::init(true));
73 
74 // FIXME: Unify control over GlobalMerge.
75 static cl::opt<cl::boolOrDefault>
76 EnableGlobalMerge("arm-global-merge", cl::Hidden,
77                   cl::desc("Enable the global merge pass"));
78 
79 namespace llvm {
80   void initializeARMExecutionDomainFixPass(PassRegistry&);
81 }
82 
83 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTarget() {
84   // Register the target.
85   RegisterTargetMachine<ARMLETargetMachine> X(getTheARMLETarget());
86   RegisterTargetMachine<ARMLETargetMachine> A(getTheThumbLETarget());
87   RegisterTargetMachine<ARMBETargetMachine> Y(getTheARMBETarget());
88   RegisterTargetMachine<ARMBETargetMachine> B(getTheThumbBETarget());
89 
90   PassRegistry &Registry = *PassRegistry::getPassRegistry();
91   initializeGlobalISel(Registry);
92   initializeARMLoadStoreOptPass(Registry);
93   initializeARMPreAllocLoadStoreOptPass(Registry);
94   initializeARMParallelDSPPass(Registry);
95   initializeARMConstantIslandsPass(Registry);
96   initializeARMExecutionDomainFixPass(Registry);
97   initializeARMExpandPseudoPass(Registry);
98   initializeThumb2SizeReducePass(Registry);
99   initializeMVEVPTBlockPass(Registry);
100   initializeMVETPAndVPTOptimisationsPass(Registry);
101   initializeMVETailPredicationPass(Registry);
102   initializeARMLowOverheadLoopsPass(Registry);
103   initializeARMBlockPlacementPass(Registry);
104   initializeMVEGatherScatterLoweringPass(Registry);
105   initializeARMSLSHardeningPass(Registry);
106   initializeMVELaneInterleavingPass(Registry);
107 }
108 
109 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
110   if (TT.isOSBinFormatMachO())
111     return std::make_unique<TargetLoweringObjectFileMachO>();
112   if (TT.isOSWindows())
113     return std::make_unique<TargetLoweringObjectFileCOFF>();
114   return std::make_unique<ARMElfTargetObjectFile>();
115 }
116 
117 static ARMBaseTargetMachine::ARMABI
118 computeTargetABI(const Triple &TT, StringRef CPU,
119                  const TargetOptions &Options) {
120   StringRef ABIName = Options.MCOptions.getABIName();
121 
122   if (ABIName.empty())
123     ABIName = ARM::computeDefaultTargetABI(TT, CPU);
124 
125   if (ABIName == "aapcs16")
126     return ARMBaseTargetMachine::ARM_ABI_AAPCS16;
127   else if (ABIName.startswith("aapcs"))
128     return ARMBaseTargetMachine::ARM_ABI_AAPCS;
129   else if (ABIName.startswith("apcs"))
130     return ARMBaseTargetMachine::ARM_ABI_APCS;
131 
132   llvm_unreachable("Unhandled/unknown ABI Name!");
133   return ARMBaseTargetMachine::ARM_ABI_UNKNOWN;
134 }
135 
136 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
137                                      const TargetOptions &Options,
138                                      bool isLittle) {
139   auto ABI = computeTargetABI(TT, CPU, Options);
140   std::string Ret;
141 
142   if (isLittle)
143     // Little endian.
144     Ret += "e";
145   else
146     // Big endian.
147     Ret += "E";
148 
149   Ret += DataLayout::getManglingComponent(TT);
150 
151   // Pointers are 32 bits and aligned to 32 bits.
152   Ret += "-p:32:32";
153 
154   // Function pointers are aligned to 8 bits (because the LSB stores the
155   // ARM/Thumb state).
156   Ret += "-Fi8";
157 
158   // ABIs other than APCS have 64 bit integers with natural alignment.
159   if (ABI != ARMBaseTargetMachine::ARM_ABI_APCS)
160     Ret += "-i64:64";
161 
162   // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
163   // bits, others to 64 bits. We always try to align to 64 bits.
164   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
165     Ret += "-f64:32:64";
166 
167   // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
168   // to 64. We always ty to give them natural alignment.
169   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
170     Ret += "-v64:32:64-v128:32:128";
171   else if (ABI != ARMBaseTargetMachine::ARM_ABI_AAPCS16)
172     Ret += "-v128:64:128";
173 
174   // Try to align aggregates to 32 bits (the default is 64 bits, which has no
175   // particular hardware support on 32-bit ARM).
176   Ret += "-a:0:32";
177 
178   // Integer registers are 32 bits.
179   Ret += "-n32";
180 
181   // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
182   // aligned everywhere else.
183   if (TT.isOSNaCl() || ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
184     Ret += "-S128";
185   else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
186     Ret += "-S64";
187   else
188     Ret += "-S32";
189 
190   return Ret;
191 }
192 
193 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
194                                            Optional<Reloc::Model> RM) {
195   if (!RM.hasValue())
196     // Default relocation model on Darwin is PIC.
197     return TT.isOSBinFormatMachO() ? Reloc::PIC_ : Reloc::Static;
198 
199   if (*RM == Reloc::ROPI || *RM == Reloc::RWPI || *RM == Reloc::ROPI_RWPI)
200     assert(TT.isOSBinFormatELF() &&
201            "ROPI/RWPI currently only supported for ELF");
202 
203   // DynamicNoPIC is only used on darwin.
204   if (*RM == Reloc::DynamicNoPIC && !TT.isOSDarwin())
205     return Reloc::Static;
206 
207   return *RM;
208 }
209 
210 /// Create an ARM architecture model.
211 ///
212 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
213                                            StringRef CPU, StringRef FS,
214                                            const TargetOptions &Options,
215                                            Optional<Reloc::Model> RM,
216                                            Optional<CodeModel::Model> CM,
217                                            CodeGenOpt::Level OL, bool isLittle)
218     : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
219                         CPU, FS, Options, getEffectiveRelocModel(TT, RM),
220                         getEffectiveCodeModel(CM, CodeModel::Small), OL),
221       TargetABI(computeTargetABI(TT, CPU, Options)),
222       TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {
223 
224   // Default to triple-appropriate float ABI
225   if (Options.FloatABIType == FloatABI::Default) {
226     if (isTargetHardFloat())
227       this->Options.FloatABIType = FloatABI::Hard;
228     else
229       this->Options.FloatABIType = FloatABI::Soft;
230   }
231 
232   // Default to triple-appropriate EABI
233   if (Options.EABIVersion == EABI::Default ||
234       Options.EABIVersion == EABI::Unknown) {
235     // musl is compatible with glibc with regard to EABI version
236     if ((TargetTriple.getEnvironment() == Triple::GNUEABI ||
237          TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
238          TargetTriple.getEnvironment() == Triple::MuslEABI ||
239          TargetTriple.getEnvironment() == Triple::MuslEABIHF) &&
240         !(TargetTriple.isOSWindows() || TargetTriple.isOSDarwin()))
241       this->Options.EABIVersion = EABI::GNU;
242     else
243       this->Options.EABIVersion = EABI::EABI5;
244   }
245 
246   if (TT.isOSBinFormatMachO()) {
247     this->Options.TrapUnreachable = true;
248     this->Options.NoTrapAfterNoreturn = true;
249   }
250 
251   // ARM supports the debug entry values.
252   setSupportsDebugEntryValues(true);
253 
254   initAsmInfo();
255 
256   // ARM supports the MachineOutliner.
257   setMachineOutliner(true);
258   setSupportsDefaultOutlining(true);
259 }
260 
261 ARMBaseTargetMachine::~ARMBaseTargetMachine() = default;
262 
263 const ARMSubtarget *
264 ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
265   Attribute CPUAttr = F.getFnAttribute("target-cpu");
266   Attribute FSAttr = F.getFnAttribute("target-features");
267 
268   std::string CPU =
269       CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
270   std::string FS =
271       FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
272 
273   // FIXME: This is related to the code below to reset the target options,
274   // we need to know whether or not the soft float flag is set on the
275   // function before we can generate a subtarget. We also need to use
276   // it as a key for the subtarget since that can be the only difference
277   // between two functions.
278   bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
279   // If the soft float attribute is set on the function turn on the soft float
280   // subtarget feature.
281   if (SoftFloat)
282     FS += FS.empty() ? "+soft-float" : ",+soft-float";
283 
284   // Use the optminsize to identify the subtarget, but don't use it in the
285   // feature string.
286   std::string Key = CPU + FS;
287   if (F.hasMinSize())
288     Key += "+minsize";
289 
290   auto &I = SubtargetMap[Key];
291   if (!I) {
292     // This needs to be done before we create a new subtarget since any
293     // creation will depend on the TM and the code generation flags on the
294     // function that reside in TargetOptions.
295     resetTargetOptions(F);
296     I = std::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle,
297                                         F.hasMinSize());
298 
299     if (!I->isThumb() && !I->hasARMOps())
300       F.getContext().emitError("Function '" + F.getName() + "' uses ARM "
301           "instructions, but the target does not support ARM mode execution.");
302   }
303 
304   return I.get();
305 }
306 
307 TargetTransformInfo
308 ARMBaseTargetMachine::getTargetTransformInfo(const Function &F) {
309   return TargetTransformInfo(ARMTTIImpl(this, F));
310 }
311 
312 ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT,
313                                        StringRef CPU, StringRef FS,
314                                        const TargetOptions &Options,
315                                        Optional<Reloc::Model> RM,
316                                        Optional<CodeModel::Model> CM,
317                                        CodeGenOpt::Level OL, bool JIT)
318     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
319 
320 ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT,
321                                        StringRef CPU, StringRef FS,
322                                        const TargetOptions &Options,
323                                        Optional<Reloc::Model> RM,
324                                        Optional<CodeModel::Model> CM,
325                                        CodeGenOpt::Level OL, bool JIT)
326     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
327 
328 namespace {
329 
330 /// ARM Code Generator Pass Configuration Options.
331 class ARMPassConfig : public TargetPassConfig {
332 public:
333   ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
334       : TargetPassConfig(TM, PM) {}
335 
336   ARMBaseTargetMachine &getARMTargetMachine() const {
337     return getTM<ARMBaseTargetMachine>();
338   }
339 
340   ScheduleDAGInstrs *
341   createMachineScheduler(MachineSchedContext *C) const override {
342     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
343     // add DAG Mutations here.
344     const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
345     if (ST.hasFusion())
346       DAG->addMutation(createARMMacroFusionDAGMutation());
347     return DAG;
348   }
349 
350   ScheduleDAGInstrs *
351   createPostMachineScheduler(MachineSchedContext *C) const override {
352     ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
353     // add DAG Mutations here.
354     const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
355     if (ST.hasFusion())
356       DAG->addMutation(createARMMacroFusionDAGMutation());
357     return DAG;
358   }
359 
360   void addIRPasses() override;
361   void addCodeGenPrepare() override;
362   bool addPreISel() override;
363   bool addInstSelector() override;
364   bool addIRTranslator() override;
365   bool addLegalizeMachineIR() override;
366   bool addRegBankSelect() override;
367   bool addGlobalInstructionSelect() override;
368   void addPreRegAlloc() override;
369   void addPreSched2() override;
370   void addPreEmitPass() override;
371   void addPreEmitPass2() override;
372 
373   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
374 };
375 
376 class ARMExecutionDomainFix : public ExecutionDomainFix {
377 public:
378   static char ID;
379   ARMExecutionDomainFix() : ExecutionDomainFix(ID, ARM::DPRRegClass) {}
380   StringRef getPassName() const override {
381     return "ARM Execution Domain Fix";
382   }
383 };
384 char ARMExecutionDomainFix::ID;
385 
386 } // end anonymous namespace
387 
388 INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix",
389   "ARM Execution Domain Fix", false, false)
390 INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
391 INITIALIZE_PASS_END(ARMExecutionDomainFix, "arm-execution-domain-fix",
392   "ARM Execution Domain Fix", false, false)
393 
394 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
395   return new ARMPassConfig(*this, PM);
396 }
397 
398 std::unique_ptr<CSEConfigBase> ARMPassConfig::getCSEConfig() const {
399   return getStandardCSEConfigForOpt(TM->getOptLevel());
400 }
401 
402 void ARMPassConfig::addIRPasses() {
403   if (TM->Options.ThreadModel == ThreadModel::Single)
404     addPass(createLowerAtomicPass());
405   else
406     addPass(createAtomicExpandPass());
407 
408   // Cmpxchg instructions are often used with a subsequent comparison to
409   // determine whether it succeeded. We can exploit existing control-flow in
410   // ldrex/strex loops to simplify this, but it needs tidying up.
411   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
412     addPass(createCFGSimplificationPass(
413         SimplifyCFGOptions().hoistCommonInsts(true).sinkCommonInsts(true),
414         [this](const Function &F) {
415           const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
416           return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
417         }));
418 
419   addPass(createMVEGatherScatterLoweringPass());
420   addPass(createMVELaneInterleavingPass());
421 
422   TargetPassConfig::addIRPasses();
423 
424   // Run the parallel DSP pass.
425   if (getOptLevel() == CodeGenOpt::Aggressive)
426     addPass(createARMParallelDSPPass());
427 
428   // Match interleaved memory accesses to ldN/stN intrinsics.
429   if (TM->getOptLevel() != CodeGenOpt::None)
430     addPass(createInterleavedAccessPass());
431 
432   // Add Control Flow Guard checks.
433   if (TM->getTargetTriple().isOSWindows())
434     addPass(createCFGuardCheckPass());
435 }
436 
437 void ARMPassConfig::addCodeGenPrepare() {
438   if (getOptLevel() != CodeGenOpt::None)
439     addPass(createTypePromotionPass());
440   TargetPassConfig::addCodeGenPrepare();
441 }
442 
443 bool ARMPassConfig::addPreISel() {
444   if ((TM->getOptLevel() != CodeGenOpt::None &&
445        EnableGlobalMerge == cl::BOU_UNSET) ||
446       EnableGlobalMerge == cl::BOU_TRUE) {
447     // FIXME: This is using the thumb1 only constant value for
448     // maximal global offset for merging globals. We may want
449     // to look into using the old value for non-thumb1 code of
450     // 4095 based on the TargetMachine, but this starts to become
451     // tricky when doing code gen per function.
452     bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
453                                (EnableGlobalMerge == cl::BOU_UNSET);
454     // Merging of extern globals is enabled by default on non-Mach-O as we
455     // expect it to be generally either beneficial or harmless. On Mach-O it
456     // is disabled as we emit the .subsections_via_symbols directive which
457     // means that merging extern globals is not safe.
458     bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
459     addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize,
460                                   MergeExternalByDefault));
461   }
462 
463   if (TM->getOptLevel() != CodeGenOpt::None) {
464     addPass(createHardwareLoopsPass());
465     addPass(createMVETailPredicationPass());
466     // FIXME: IR passes can delete address-taken basic blocks, deleting
467     // corresponding blockaddresses. ARMConstantPoolConstant holds references to
468     // address-taken basic blocks which can be invalidated if the function
469     // containing the blockaddress has already been codegen'd and the basic
470     // block is removed. Work around this by forcing all IR passes to run before
471     // any ISel takes place. We should have a more principled way of handling
472     // this. See D99707 for more details.
473     addPass(createBarrierNoopPass());
474   }
475 
476   return false;
477 }
478 
479 bool ARMPassConfig::addInstSelector() {
480   addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
481   return false;
482 }
483 
484 bool ARMPassConfig::addIRTranslator() {
485   addPass(new IRTranslator(getOptLevel()));
486   return false;
487 }
488 
489 bool ARMPassConfig::addLegalizeMachineIR() {
490   addPass(new Legalizer());
491   return false;
492 }
493 
494 bool ARMPassConfig::addRegBankSelect() {
495   addPass(new RegBankSelect());
496   return false;
497 }
498 
499 bool ARMPassConfig::addGlobalInstructionSelect() {
500   addPass(new InstructionSelect(getOptLevel()));
501   return false;
502 }
503 
504 void ARMPassConfig::addPreRegAlloc() {
505   if (getOptLevel() != CodeGenOpt::None) {
506     addPass(createMVETPAndVPTOptimisationsPass());
507 
508     addPass(createMLxExpansionPass());
509 
510     if (EnableARMLoadStoreOpt)
511       addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
512 
513     if (!DisableA15SDOptimization)
514       addPass(createA15SDOptimizerPass());
515   }
516 }
517 
518 void ARMPassConfig::addPreSched2() {
519   if (getOptLevel() != CodeGenOpt::None) {
520     if (EnableARMLoadStoreOpt)
521       addPass(createARMLoadStoreOptimizationPass());
522 
523     addPass(new ARMExecutionDomainFix());
524     addPass(createBreakFalseDeps());
525   }
526 
527   // Expand some pseudo instructions into multiple instructions to allow
528   // proper scheduling.
529   addPass(createARMExpandPseudoPass());
530 
531   if (getOptLevel() != CodeGenOpt::None) {
532     // When optimising for size, always run the Thumb2SizeReduction pass before
533     // IfConversion. Otherwise, check whether IT blocks are restricted
534     // (e.g. in v8, IfConversion depends on Thumb instruction widths)
535     addPass(createThumb2SizeReductionPass([this](const Function &F) {
536       return this->TM->getSubtarget<ARMSubtarget>(F).hasMinSize() ||
537              this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
538     }));
539 
540     addPass(createIfConverter([](const MachineFunction &MF) {
541       return !MF.getSubtarget<ARMSubtarget>().isThumb1Only();
542     }));
543   }
544   addPass(createMVEVPTBlockPass());
545   addPass(createThumb2ITBlockPass());
546 
547   // Add both scheduling passes to give the subtarget an opportunity to pick
548   // between them.
549   if (getOptLevel() != CodeGenOpt::None) {
550     addPass(&PostMachineSchedulerID);
551     addPass(&PostRASchedulerID);
552   }
553 
554   addPass(createARMIndirectThunks());
555   addPass(createARMSLSHardeningPass());
556 }
557 
558 void ARMPassConfig::addPreEmitPass() {
559   addPass(createThumb2SizeReductionPass());
560 
561   // Constant island pass work on unbundled instructions.
562   addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
563     return MF.getSubtarget<ARMSubtarget>().isThumb2();
564   }));
565 
566   // Don't optimize barriers or block placement at -O0.
567   if (getOptLevel() != CodeGenOpt::None) {
568     addPass(createARMBlockPlacementPass());
569     addPass(createARMOptimizeBarriersPass());
570   }
571 }
572 
573 void ARMPassConfig::addPreEmitPass2() {
574   addPass(createARMConstantIslandPass());
575   addPass(createARMLowOverheadLoopsPass());
576 
577   if (TM->getTargetTriple().isOSWindows()) {
578     // Identify valid longjmp targets for Windows Control Flow Guard.
579     addPass(createCFGuardLongjmpPass());
580     // Identify valid eh continuation targets for Windows EHCont Guard.
581     addPass(createEHContGuardCatchretPass());
582   }
583 }
584