1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "ARMTargetMachine.h"
13 #include "ARM.h"
14 #include "ARMMacroFusion.h"
15 #include "ARMSubtarget.h"
16 #include "ARMTargetObjectFile.h"
17 #include "ARMTargetTransformInfo.h"
18 #include "MCTargetDesc/ARMMCTargetDesc.h"
19 #include "TargetInfo/ARMTargetInfo.h"
20 #include "llvm/ADT/Optional.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/Analysis/TargetTransformInfo.h"
25 #include "llvm/CodeGen/ExecutionDomainFix.h"
26 #include "llvm/CodeGen/GlobalISel/CSEInfo.h"
27 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
28 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
29 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
31 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
32 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
33 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineScheduler.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/RegisterBankInfo.h"
38 #include "llvm/CodeGen/TargetPassConfig.h"
39 #include "llvm/IR/Attributes.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/MC/TargetRegistry.h"
43 #include "llvm/Pass.h"
44 #include "llvm/Support/ARMTargetParser.h"
45 #include "llvm/Support/CodeGen.h"
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/ErrorHandling.h"
48 #include "llvm/Support/TargetParser.h"
49 #include "llvm/Target/TargetLoweringObjectFile.h"
50 #include "llvm/Target/TargetOptions.h"
51 #include "llvm/Transforms/CFGuard.h"
52 #include "llvm/Transforms/IPO.h"
53 #include "llvm/Transforms/Scalar.h"
54 #include <cassert>
55 #include <memory>
56 #include <string>
57 
58 using namespace llvm;
59 
60 static cl::opt<bool>
61 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
62                    cl::desc("Inhibit optimization of S->D register accesses on A15"),
63                    cl::init(false));
64 
65 static cl::opt<bool>
66 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
67                  cl::desc("Run SimplifyCFG after expanding atomic operations"
68                           " to make use of cmpxchg flow-based information"),
69                  cl::init(true));
70 
71 static cl::opt<bool>
72 EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
73                       cl::desc("Enable ARM load/store optimization pass"),
74                       cl::init(true));
75 
76 // FIXME: Unify control over GlobalMerge.
77 static cl::opt<cl::boolOrDefault>
78 EnableGlobalMerge("arm-global-merge", cl::Hidden,
79                   cl::desc("Enable the global merge pass"));
80 
81 namespace llvm {
82   void initializeARMExecutionDomainFixPass(PassRegistry&);
83 }
84 
85 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTarget() {
86   // Register the target.
87   RegisterTargetMachine<ARMLETargetMachine> X(getTheARMLETarget());
88   RegisterTargetMachine<ARMLETargetMachine> A(getTheThumbLETarget());
89   RegisterTargetMachine<ARMBETargetMachine> Y(getTheARMBETarget());
90   RegisterTargetMachine<ARMBETargetMachine> B(getTheThumbBETarget());
91 
92   PassRegistry &Registry = *PassRegistry::getPassRegistry();
93   initializeGlobalISel(Registry);
94   initializeARMLoadStoreOptPass(Registry);
95   initializeARMPreAllocLoadStoreOptPass(Registry);
96   initializeARMParallelDSPPass(Registry);
97   initializeARMBranchTargetsPass(Registry);
98   initializeARMConstantIslandsPass(Registry);
99   initializeARMExecutionDomainFixPass(Registry);
100   initializeARMExpandPseudoPass(Registry);
101   initializeThumb2SizeReducePass(Registry);
102   initializeMVEVPTBlockPass(Registry);
103   initializeMVETPAndVPTOptimisationsPass(Registry);
104   initializeMVETailPredicationPass(Registry);
105   initializeARMLowOverheadLoopsPass(Registry);
106   initializeARMBlockPlacementPass(Registry);
107   initializeMVEGatherScatterLoweringPass(Registry);
108   initializeARMSLSHardeningPass(Registry);
109   initializeMVELaneInterleavingPass(Registry);
110   initializeARMFixCortexA57AES1742098Pass(Registry);
111 }
112 
113 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
114   if (TT.isOSBinFormatMachO())
115     return std::make_unique<TargetLoweringObjectFileMachO>();
116   if (TT.isOSWindows())
117     return std::make_unique<TargetLoweringObjectFileCOFF>();
118   return std::make_unique<ARMElfTargetObjectFile>();
119 }
120 
121 static ARMBaseTargetMachine::ARMABI
122 computeTargetABI(const Triple &TT, StringRef CPU,
123                  const TargetOptions &Options) {
124   StringRef ABIName = Options.MCOptions.getABIName();
125 
126   if (ABIName.empty())
127     ABIName = ARM::computeDefaultTargetABI(TT, CPU);
128 
129   if (ABIName == "aapcs16")
130     return ARMBaseTargetMachine::ARM_ABI_AAPCS16;
131   else if (ABIName.startswith("aapcs"))
132     return ARMBaseTargetMachine::ARM_ABI_AAPCS;
133   else if (ABIName.startswith("apcs"))
134     return ARMBaseTargetMachine::ARM_ABI_APCS;
135 
136   llvm_unreachable("Unhandled/unknown ABI Name!");
137   return ARMBaseTargetMachine::ARM_ABI_UNKNOWN;
138 }
139 
140 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
141                                      const TargetOptions &Options,
142                                      bool isLittle) {
143   auto ABI = computeTargetABI(TT, CPU, Options);
144   std::string Ret;
145 
146   if (isLittle)
147     // Little endian.
148     Ret += "e";
149   else
150     // Big endian.
151     Ret += "E";
152 
153   Ret += DataLayout::getManglingComponent(TT);
154 
155   // Pointers are 32 bits and aligned to 32 bits.
156   Ret += "-p:32:32";
157 
158   // Function pointers are aligned to 8 bits (because the LSB stores the
159   // ARM/Thumb state).
160   Ret += "-Fi8";
161 
162   // ABIs other than APCS have 64 bit integers with natural alignment.
163   if (ABI != ARMBaseTargetMachine::ARM_ABI_APCS)
164     Ret += "-i64:64";
165 
166   // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
167   // bits, others to 64 bits. We always try to align to 64 bits.
168   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
169     Ret += "-f64:32:64";
170 
171   // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
172   // to 64. We always ty to give them natural alignment.
173   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
174     Ret += "-v64:32:64-v128:32:128";
175   else if (ABI != ARMBaseTargetMachine::ARM_ABI_AAPCS16)
176     Ret += "-v128:64:128";
177 
178   // Try to align aggregates to 32 bits (the default is 64 bits, which has no
179   // particular hardware support on 32-bit ARM).
180   Ret += "-a:0:32";
181 
182   // Integer registers are 32 bits.
183   Ret += "-n32";
184 
185   // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
186   // aligned everywhere else.
187   if (TT.isOSNaCl() || ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
188     Ret += "-S128";
189   else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
190     Ret += "-S64";
191   else
192     Ret += "-S32";
193 
194   return Ret;
195 }
196 
197 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
198                                            Optional<Reloc::Model> RM) {
199   if (!RM)
200     // Default relocation model on Darwin is PIC.
201     return TT.isOSBinFormatMachO() ? Reloc::PIC_ : Reloc::Static;
202 
203   if (*RM == Reloc::ROPI || *RM == Reloc::RWPI || *RM == Reloc::ROPI_RWPI)
204     assert(TT.isOSBinFormatELF() &&
205            "ROPI/RWPI currently only supported for ELF");
206 
207   // DynamicNoPIC is only used on darwin.
208   if (*RM == Reloc::DynamicNoPIC && !TT.isOSDarwin())
209     return Reloc::Static;
210 
211   return *RM;
212 }
213 
214 /// Create an ARM architecture model.
215 ///
216 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
217                                            StringRef CPU, StringRef FS,
218                                            const TargetOptions &Options,
219                                            Optional<Reloc::Model> RM,
220                                            Optional<CodeModel::Model> CM,
221                                            CodeGenOpt::Level OL, bool isLittle)
222     : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
223                         CPU, FS, Options, getEffectiveRelocModel(TT, RM),
224                         getEffectiveCodeModel(CM, CodeModel::Small), OL),
225       TargetABI(computeTargetABI(TT, CPU, Options)),
226       TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {
227 
228   // Default to triple-appropriate float ABI
229   if (Options.FloatABIType == FloatABI::Default) {
230     if (isTargetHardFloat())
231       this->Options.FloatABIType = FloatABI::Hard;
232     else
233       this->Options.FloatABIType = FloatABI::Soft;
234   }
235 
236   // Default to triple-appropriate EABI
237   if (Options.EABIVersion == EABI::Default ||
238       Options.EABIVersion == EABI::Unknown) {
239     // musl is compatible with glibc with regard to EABI version
240     if ((TargetTriple.getEnvironment() == Triple::GNUEABI ||
241          TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
242          TargetTriple.getEnvironment() == Triple::MuslEABI ||
243          TargetTriple.getEnvironment() == Triple::MuslEABIHF) &&
244         !(TargetTriple.isOSWindows() || TargetTriple.isOSDarwin()))
245       this->Options.EABIVersion = EABI::GNU;
246     else
247       this->Options.EABIVersion = EABI::EABI5;
248   }
249 
250   if (TT.isOSBinFormatMachO()) {
251     this->Options.TrapUnreachable = true;
252     this->Options.NoTrapAfterNoreturn = true;
253   }
254 
255   // ARM supports the debug entry values.
256   setSupportsDebugEntryValues(true);
257 
258   initAsmInfo();
259 
260   // ARM supports the MachineOutliner.
261   setMachineOutliner(true);
262   setSupportsDefaultOutlining(true);
263 }
264 
265 ARMBaseTargetMachine::~ARMBaseTargetMachine() = default;
266 
267 const ARMSubtarget *
268 ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
269   Attribute CPUAttr = F.getFnAttribute("target-cpu");
270   Attribute FSAttr = F.getFnAttribute("target-features");
271 
272   std::string CPU =
273       CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
274   std::string FS =
275       FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
276 
277   // FIXME: This is related to the code below to reset the target options,
278   // we need to know whether or not the soft float flag is set on the
279   // function before we can generate a subtarget. We also need to use
280   // it as a key for the subtarget since that can be the only difference
281   // between two functions.
282   bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
283   // If the soft float attribute is set on the function turn on the soft float
284   // subtarget feature.
285   if (SoftFloat)
286     FS += FS.empty() ? "+soft-float" : ",+soft-float";
287 
288   // Use the optminsize to identify the subtarget, but don't use it in the
289   // feature string.
290   std::string Key = CPU + FS;
291   if (F.hasMinSize())
292     Key += "+minsize";
293 
294   auto &I = SubtargetMap[Key];
295   if (!I) {
296     // This needs to be done before we create a new subtarget since any
297     // creation will depend on the TM and the code generation flags on the
298     // function that reside in TargetOptions.
299     resetTargetOptions(F);
300     I = std::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle,
301                                         F.hasMinSize());
302 
303     if (!I->isThumb() && !I->hasARMOps())
304       F.getContext().emitError("Function '" + F.getName() + "' uses ARM "
305           "instructions, but the target does not support ARM mode execution.");
306   }
307 
308   return I.get();
309 }
310 
311 TargetTransformInfo
312 ARMBaseTargetMachine::getTargetTransformInfo(const Function &F) const {
313   return TargetTransformInfo(ARMTTIImpl(this, F));
314 }
315 
316 ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT,
317                                        StringRef CPU, StringRef FS,
318                                        const TargetOptions &Options,
319                                        Optional<Reloc::Model> RM,
320                                        Optional<CodeModel::Model> CM,
321                                        CodeGenOpt::Level OL, bool JIT)
322     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
323 
324 ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT,
325                                        StringRef CPU, StringRef FS,
326                                        const TargetOptions &Options,
327                                        Optional<Reloc::Model> RM,
328                                        Optional<CodeModel::Model> CM,
329                                        CodeGenOpt::Level OL, bool JIT)
330     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
331 
332 namespace {
333 
334 /// ARM Code Generator Pass Configuration Options.
335 class ARMPassConfig : public TargetPassConfig {
336 public:
337   ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
338       : TargetPassConfig(TM, PM) {}
339 
340   ARMBaseTargetMachine &getARMTargetMachine() const {
341     return getTM<ARMBaseTargetMachine>();
342   }
343 
344   ScheduleDAGInstrs *
345   createMachineScheduler(MachineSchedContext *C) const override {
346     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
347     // add DAG Mutations here.
348     const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
349     if (ST.hasFusion())
350       DAG->addMutation(createARMMacroFusionDAGMutation());
351     return DAG;
352   }
353 
354   ScheduleDAGInstrs *
355   createPostMachineScheduler(MachineSchedContext *C) const override {
356     ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
357     // add DAG Mutations here.
358     const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
359     if (ST.hasFusion())
360       DAG->addMutation(createARMMacroFusionDAGMutation());
361     return DAG;
362   }
363 
364   void addIRPasses() override;
365   void addCodeGenPrepare() override;
366   bool addPreISel() override;
367   bool addInstSelector() override;
368   bool addIRTranslator() override;
369   bool addLegalizeMachineIR() override;
370   bool addRegBankSelect() override;
371   bool addGlobalInstructionSelect() override;
372   void addPreRegAlloc() override;
373   void addPreSched2() override;
374   void addPreEmitPass() override;
375   void addPreEmitPass2() override;
376 
377   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
378 };
379 
380 class ARMExecutionDomainFix : public ExecutionDomainFix {
381 public:
382   static char ID;
383   ARMExecutionDomainFix() : ExecutionDomainFix(ID, ARM::DPRRegClass) {}
384   StringRef getPassName() const override {
385     return "ARM Execution Domain Fix";
386   }
387 };
388 char ARMExecutionDomainFix::ID;
389 
390 } // end anonymous namespace
391 
392 INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix",
393   "ARM Execution Domain Fix", false, false)
394 INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
395 INITIALIZE_PASS_END(ARMExecutionDomainFix, "arm-execution-domain-fix",
396   "ARM Execution Domain Fix", false, false)
397 
398 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
399   return new ARMPassConfig(*this, PM);
400 }
401 
402 std::unique_ptr<CSEConfigBase> ARMPassConfig::getCSEConfig() const {
403   return getStandardCSEConfigForOpt(TM->getOptLevel());
404 }
405 
406 void ARMPassConfig::addIRPasses() {
407   if (TM->Options.ThreadModel == ThreadModel::Single)
408     addPass(createLowerAtomicPass());
409   else
410     addPass(createAtomicExpandPass());
411 
412   // Cmpxchg instructions are often used with a subsequent comparison to
413   // determine whether it succeeded. We can exploit existing control-flow in
414   // ldrex/strex loops to simplify this, but it needs tidying up.
415   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
416     addPass(createCFGSimplificationPass(
417         SimplifyCFGOptions().hoistCommonInsts(true).sinkCommonInsts(true),
418         [this](const Function &F) {
419           const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
420           return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
421         }));
422 
423   addPass(createMVEGatherScatterLoweringPass());
424   addPass(createMVELaneInterleavingPass());
425 
426   TargetPassConfig::addIRPasses();
427 
428   // Run the parallel DSP pass.
429   if (getOptLevel() == CodeGenOpt::Aggressive)
430     addPass(createARMParallelDSPPass());
431 
432   // Match interleaved memory accesses to ldN/stN intrinsics.
433   if (TM->getOptLevel() != CodeGenOpt::None)
434     addPass(createInterleavedAccessPass());
435 
436   // Add Control Flow Guard checks.
437   if (TM->getTargetTriple().isOSWindows())
438     addPass(createCFGuardCheckPass());
439 
440   if (TM->Options.JMCInstrument)
441     addPass(createJMCInstrumenterPass());
442 }
443 
444 void ARMPassConfig::addCodeGenPrepare() {
445   if (getOptLevel() != CodeGenOpt::None)
446     addPass(createTypePromotionPass());
447   TargetPassConfig::addCodeGenPrepare();
448 }
449 
450 bool ARMPassConfig::addPreISel() {
451   if ((TM->getOptLevel() != CodeGenOpt::None &&
452        EnableGlobalMerge == cl::BOU_UNSET) ||
453       EnableGlobalMerge == cl::BOU_TRUE) {
454     // FIXME: This is using the thumb1 only constant value for
455     // maximal global offset for merging globals. We may want
456     // to look into using the old value for non-thumb1 code of
457     // 4095 based on the TargetMachine, but this starts to become
458     // tricky when doing code gen per function.
459     bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
460                                (EnableGlobalMerge == cl::BOU_UNSET);
461     // Merging of extern globals is enabled by default on non-Mach-O as we
462     // expect it to be generally either beneficial or harmless. On Mach-O it
463     // is disabled as we emit the .subsections_via_symbols directive which
464     // means that merging extern globals is not safe.
465     bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
466     addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize,
467                                   MergeExternalByDefault));
468   }
469 
470   if (TM->getOptLevel() != CodeGenOpt::None) {
471     addPass(createHardwareLoopsPass());
472     addPass(createMVETailPredicationPass());
473     // FIXME: IR passes can delete address-taken basic blocks, deleting
474     // corresponding blockaddresses. ARMConstantPoolConstant holds references to
475     // address-taken basic blocks which can be invalidated if the function
476     // containing the blockaddress has already been codegen'd and the basic
477     // block is removed. Work around this by forcing all IR passes to run before
478     // any ISel takes place. We should have a more principled way of handling
479     // this. See D99707 for more details.
480     addPass(createBarrierNoopPass());
481   }
482 
483   return false;
484 }
485 
486 bool ARMPassConfig::addInstSelector() {
487   addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
488   return false;
489 }
490 
491 bool ARMPassConfig::addIRTranslator() {
492   addPass(new IRTranslator(getOptLevel()));
493   return false;
494 }
495 
496 bool ARMPassConfig::addLegalizeMachineIR() {
497   addPass(new Legalizer());
498   return false;
499 }
500 
501 bool ARMPassConfig::addRegBankSelect() {
502   addPass(new RegBankSelect());
503   return false;
504 }
505 
506 bool ARMPassConfig::addGlobalInstructionSelect() {
507   addPass(new InstructionSelect(getOptLevel()));
508   return false;
509 }
510 
511 void ARMPassConfig::addPreRegAlloc() {
512   if (getOptLevel() != CodeGenOpt::None) {
513     if (getOptLevel() == CodeGenOpt::Aggressive)
514       addPass(&MachinePipelinerID);
515 
516     addPass(createMVETPAndVPTOptimisationsPass());
517 
518     addPass(createMLxExpansionPass());
519 
520     if (EnableARMLoadStoreOpt)
521       addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
522 
523     if (!DisableA15SDOptimization)
524       addPass(createA15SDOptimizerPass());
525   }
526 }
527 
528 void ARMPassConfig::addPreSched2() {
529   if (getOptLevel() != CodeGenOpt::None) {
530     if (EnableARMLoadStoreOpt)
531       addPass(createARMLoadStoreOptimizationPass());
532 
533     addPass(new ARMExecutionDomainFix());
534     addPass(createBreakFalseDeps());
535   }
536 
537   // Expand some pseudo instructions into multiple instructions to allow
538   // proper scheduling.
539   addPass(createARMExpandPseudoPass());
540 
541   if (getOptLevel() != CodeGenOpt::None) {
542     // When optimising for size, always run the Thumb2SizeReduction pass before
543     // IfConversion. Otherwise, check whether IT blocks are restricted
544     // (e.g. in v8, IfConversion depends on Thumb instruction widths)
545     addPass(createThumb2SizeReductionPass([this](const Function &F) {
546       return this->TM->getSubtarget<ARMSubtarget>(F).hasMinSize() ||
547              this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
548     }));
549 
550     addPass(createIfConverter([](const MachineFunction &MF) {
551       return !MF.getSubtarget<ARMSubtarget>().isThumb1Only();
552     }));
553   }
554   addPass(createThumb2ITBlockPass());
555 
556   // Add both scheduling passes to give the subtarget an opportunity to pick
557   // between them.
558   if (getOptLevel() != CodeGenOpt::None) {
559     addPass(&PostMachineSchedulerID);
560     addPass(&PostRASchedulerID);
561   }
562 
563   addPass(createMVEVPTBlockPass());
564   addPass(createARMIndirectThunks());
565   addPass(createARMSLSHardeningPass());
566 }
567 
568 void ARMPassConfig::addPreEmitPass() {
569   addPass(createThumb2SizeReductionPass());
570 
571   // Constant island pass work on unbundled instructions.
572   addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
573     return MF.getSubtarget<ARMSubtarget>().isThumb2();
574   }));
575 
576   // Don't optimize barriers or block placement at -O0.
577   if (getOptLevel() != CodeGenOpt::None) {
578     addPass(createARMBlockPlacementPass());
579     addPass(createARMOptimizeBarriersPass());
580   }
581 }
582 
583 void ARMPassConfig::addPreEmitPass2() {
584   // Inserts fixup instructions before unsafe AES operations. Instructions may
585   // be inserted at the start of blocks and at within blocks so this pass has to
586   // come before those below.
587   addPass(createARMFixCortexA57AES1742098Pass());
588   // Inserts BTIs at the start of functions and indirectly-called basic blocks,
589   // so passes cannot add to the start of basic blocks once this has run.
590   addPass(createARMBranchTargetsPass());
591   // Inserts Constant Islands. Block sizes cannot be increased after this point,
592   // as this may push the branch ranges and load offsets of accessing constant
593   // pools out of range..
594   addPass(createARMConstantIslandPass());
595   // Finalises Low-Overhead Loops. This replaces pseudo instructions with real
596   // instructions, but the pseudos all have conservative sizes so that block
597   // sizes will only be decreased by this pass.
598   addPass(createARMLowOverheadLoopsPass());
599 
600   if (TM->getTargetTriple().isOSWindows()) {
601     // Identify valid longjmp targets for Windows Control Flow Guard.
602     addPass(createCFGuardLongjmpPass());
603     // Identify valid eh continuation targets for Windows EHCont Guard.
604     addPass(createEHContGuardCatchretPass());
605   }
606 }
607