1 //===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides ARM specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H
14 #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H
15 
16 #include "llvm/Support/DataTypes.h"
17 #include "llvm/MC/MCInstrDesc.h"
18 #include <memory>
19 #include <string>
20 
21 namespace llvm {
22 class formatted_raw_ostream;
23 class MCAsmBackend;
24 class MCCodeEmitter;
25 class MCContext;
26 class MCInstrInfo;
27 class MCInstPrinter;
28 class MCObjectTargetWriter;
29 class MCObjectWriter;
30 class MCRegisterInfo;
31 class MCSubtargetInfo;
32 class MCStreamer;
33 class MCTargetOptions;
34 class MCRelocationInfo;
35 class MCTargetStreamer;
36 class StringRef;
37 class Target;
38 class Triple;
39 class raw_ostream;
40 class raw_pwrite_stream;
41 
42 namespace ARM_MC {
43 std::string ParseARMTriple(const Triple &TT, StringRef CPU);
44 void initLLVMToCVRegMapping(MCRegisterInfo *MRI);
45 
46 bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII);
47 bool isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII);
48 
49 template<class Inst>
50 bool isLDMBaseRegInList(const Inst &MI) {
51   auto BaseReg = MI.getOperand(0).getReg();
52   for (unsigned I = 1, E = MI.getNumOperands(); I < E; ++I) {
53     const auto &Op = MI.getOperand(I);
54     if (Op.isReg() && Op.getReg() == BaseReg)
55       return true;
56   }
57   return false;
58 }
59 
60 uint64_t evaluateBranchTarget(const MCInstrDesc &InstDesc, uint64_t Addr,
61                               int64_t Imm);
62 
63 /// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc.
64 /// do not need to go through TargetRegistry.
65 MCSubtargetInfo *createARMMCSubtargetInfo(const Triple &TT, StringRef CPU,
66                                           StringRef FS);
67 }
68 
69 MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S);
70 MCTargetStreamer *createARMTargetAsmStreamer(MCStreamer &S,
71                                              formatted_raw_ostream &OS,
72                                              MCInstPrinter *InstPrint,
73                                              bool isVerboseAsm);
74 MCTargetStreamer *createARMObjectTargetStreamer(MCStreamer &S,
75                                                 const MCSubtargetInfo &STI);
76 
77 MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
78                                         const MCRegisterInfo &MRI,
79                                         MCContext &Ctx);
80 
81 MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
82                                         const MCRegisterInfo &MRI,
83                                         MCContext &Ctx);
84 
85 MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI,
86                                     const MCRegisterInfo &MRI,
87                                     const MCTargetOptions &Options);
88 
89 MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI,
90                                     const MCRegisterInfo &MRI,
91                                     const MCTargetOptions &Options);
92 
93 // Construct a PE/COFF machine code streamer which will generate a PE/COFF
94 // object file.
95 MCStreamer *createARMWinCOFFStreamer(MCContext &Context,
96                                      std::unique_ptr<MCAsmBackend> &&MAB,
97                                      std::unique_ptr<MCObjectWriter> &&OW,
98                                      std::unique_ptr<MCCodeEmitter> &&Emitter,
99                                      bool RelaxAll,
100                                      bool IncrementalLinkerCompatible);
101 
102 /// Construct an ELF Mach-O object writer.
103 std::unique_ptr<MCObjectTargetWriter> createARMELFObjectWriter(uint8_t OSABI);
104 
105 /// Construct an ARM Mach-O object writer.
106 std::unique_ptr<MCObjectTargetWriter>
107 createARMMachObjectWriter(bool Is64Bit, uint32_t CPUType,
108                           uint32_t CPUSubtype);
109 
110 /// Construct an ARM PE/COFF object writer.
111 std::unique_ptr<MCObjectTargetWriter>
112 createARMWinCOFFObjectWriter();
113 
114 /// Construct ARM Mach-O relocation info.
115 MCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx);
116 
117 namespace ARM {
118 enum OperandType {
119   OPERAND_VPRED_R = MCOI::OPERAND_FIRST_TARGET,
120   OPERAND_VPRED_N,
121 };
122 inline bool isVpred(OperandType op) {
123   return op == OPERAND_VPRED_R || op == OPERAND_VPRED_N;
124 }
125 inline bool isVpred(uint8_t op) {
126   return isVpred(static_cast<OperandType>(op));
127 }
128 
129 bool isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI);
130 
131 } // end namespace ARM
132 
133 } // End llvm namespace
134 
135 // Defines symbolic names for ARM registers.  This defines a mapping from
136 // register name to register number.
137 //
138 #define GET_REGINFO_ENUM
139 #include "ARMGenRegisterInfo.inc"
140 
141 // Defines symbolic names for the ARM instructions.
142 //
143 #define GET_INSTRINFO_ENUM
144 #include "ARMGenInstrInfo.inc"
145 
146 #define GET_SUBTARGETINFO_ENUM
147 #include "ARMGenSubtargetInfo.inc"
148 
149 #endif
150