1 //===-- Thumb2ITBlockPass.cpp - Insert Thumb-2 IT blocks ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "ARM.h"
10 #include "ARMMachineFunctionInfo.h"
11 #include "ARMSubtarget.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
13 #include "Thumb2InstrInfo.h"
14 #include "llvm/ADT/SmallSet.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/Statistic.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineInstrBundle.h"
24 #include "llvm/CodeGen/MachineOperand.h"
25 #include "llvm/IR/DebugLoc.h"
26 #include "llvm/MC/MCInstrDesc.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include <cassert>
29 #include <new>
30 
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "thumb2-it"
34 #define PASS_NAME "Thumb IT blocks insertion pass"
35 
36 STATISTIC(NumITs,        "Number of IT blocks inserted");
37 STATISTIC(NumMovedInsts, "Number of predicated instructions moved");
38 
39 using RegisterSet = SmallSet<unsigned, 4>;
40 
41 namespace {
42 
43   class Thumb2ITBlock : public MachineFunctionPass {
44   public:
45     static char ID;
46 
47     bool restrictIT;
48     const Thumb2InstrInfo *TII;
49     const TargetRegisterInfo *TRI;
50     ARMFunctionInfo *AFI;
51 
52     Thumb2ITBlock() : MachineFunctionPass(ID) {}
53 
54     bool runOnMachineFunction(MachineFunction &Fn) override;
55 
56     MachineFunctionProperties getRequiredProperties() const override {
57       return MachineFunctionProperties().set(
58           MachineFunctionProperties::Property::NoVRegs);
59     }
60 
61     StringRef getPassName() const override {
62       return PASS_NAME;
63     }
64 
65   private:
66     bool MoveCopyOutOfITBlock(MachineInstr *MI,
67                               ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
68                               RegisterSet &Defs, RegisterSet &Uses);
69     bool InsertITInstructions(MachineBasicBlock &Block);
70   };
71 
72   char Thumb2ITBlock::ID = 0;
73 
74 } // end anonymous namespace
75 
76 INITIALIZE_PASS(Thumb2ITBlock, DEBUG_TYPE, PASS_NAME, false, false)
77 
78 /// TrackDefUses - Tracking what registers are being defined and used by
79 /// instructions in the IT block. This also tracks "dependencies", i.e. uses
80 /// in the IT block that are defined before the IT instruction.
81 static void TrackDefUses(MachineInstr *MI, RegisterSet &Defs, RegisterSet &Uses,
82                          const TargetRegisterInfo *TRI) {
83   using RegList = SmallVector<unsigned, 4>;
84   RegList LocalDefs;
85   RegList LocalUses;
86 
87   for (auto &MO : MI->operands()) {
88     if (!MO.isReg())
89       continue;
90     Register Reg = MO.getReg();
91     if (!Reg || Reg == ARM::ITSTATE || Reg == ARM::SP)
92       continue;
93     if (MO.isUse())
94       LocalUses.push_back(Reg);
95     else
96       LocalDefs.push_back(Reg);
97   }
98 
99   auto InsertUsesDefs = [&](RegList &Regs, RegisterSet &UsesDefs) {
100     for (unsigned Reg : Regs)
101       for (MCPhysReg Subreg : TRI->subregs_inclusive(Reg))
102         UsesDefs.insert(Subreg);
103   };
104 
105   InsertUsesDefs(LocalDefs, Defs);
106   InsertUsesDefs(LocalUses, Uses);
107 }
108 
109 /// Clear kill flags for any uses in the given set.  This will likely
110 /// conservatively remove more kill flags than are necessary, but removing them
111 /// is safer than incorrect kill flags remaining on instructions.
112 static void ClearKillFlags(MachineInstr *MI, RegisterSet &Uses) {
113   for (MachineOperand &MO : MI->operands()) {
114     if (!MO.isReg() || MO.isDef() || !MO.isKill())
115       continue;
116     if (!Uses.count(MO.getReg()))
117       continue;
118     MO.setIsKill(false);
119   }
120 }
121 
122 static bool isCopy(MachineInstr *MI) {
123   switch (MI->getOpcode()) {
124   default:
125     return false;
126   case ARM::MOVr:
127   case ARM::MOVr_TC:
128   case ARM::tMOVr:
129   case ARM::t2MOVr:
130     return true;
131   }
132 }
133 
134 bool
135 Thumb2ITBlock::MoveCopyOutOfITBlock(MachineInstr *MI,
136                                     ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
137                                     RegisterSet &Defs, RegisterSet &Uses) {
138   if (!isCopy(MI))
139     return false;
140   // llvm models select's as two-address instructions. That means a copy
141   // is inserted before a t2MOVccr, etc. If the copy is scheduled in
142   // between selects we would end up creating multiple IT blocks.
143   assert(MI->getOperand(0).getSubReg() == 0 &&
144          MI->getOperand(1).getSubReg() == 0 &&
145          "Sub-register indices still around?");
146 
147   Register DstReg = MI->getOperand(0).getReg();
148   Register SrcReg = MI->getOperand(1).getReg();
149 
150   // First check if it's safe to move it.
151   if (Uses.count(DstReg) || Defs.count(SrcReg))
152     return false;
153 
154   // If the CPSR is defined by this copy, then we don't want to move it. E.g.,
155   // if we have:
156   //
157   //   movs  r1, r1
158   //   rsb   r1, 0
159   //   movs  r2, r2
160   //   rsb   r2, 0
161   //
162   // we don't want this to be converted to:
163   //
164   //   movs  r1, r1
165   //   movs  r2, r2
166   //   itt   mi
167   //   rsb   r1, 0
168   //   rsb   r2, 0
169   //
170   const MCInstrDesc &MCID = MI->getDesc();
171   if (MI->hasOptionalDef() &&
172       MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
173     return false;
174 
175   // Then peek at the next instruction to see if it's predicated on CC or OCC.
176   // If not, then there is nothing to be gained by moving the copy.
177   MachineBasicBlock::iterator I = MI;
178   ++I;
179   MachineBasicBlock::iterator E = MI->getParent()->end();
180 
181   while (I != E && I->isDebugInstr())
182     ++I;
183 
184   if (I != E) {
185     Register NPredReg;
186     ARMCC::CondCodes NCC = getITInstrPredicate(*I, NPredReg);
187     if (NCC == CC || NCC == OCC)
188       return true;
189   }
190   return false;
191 }
192 
193 bool Thumb2ITBlock::InsertITInstructions(MachineBasicBlock &MBB) {
194   bool Modified = false;
195   RegisterSet Defs, Uses;
196   MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
197 
198   while (MBBI != E) {
199     MachineInstr *MI = &*MBBI;
200     DebugLoc dl = MI->getDebugLoc();
201     Register PredReg;
202     ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg);
203     if (CC == ARMCC::AL) {
204       ++MBBI;
205       continue;
206     }
207 
208     Defs.clear();
209     Uses.clear();
210     TrackDefUses(MI, Defs, Uses, TRI);
211 
212     // Insert an IT instruction.
213     MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
214       .addImm(CC);
215 
216     // Add implicit use of ITSTATE to IT block instructions.
217     MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
218                                              true/*isImp*/, false/*isKill*/));
219 
220     MachineInstr *LastITMI = MI;
221     MachineBasicBlock::iterator InsertPos = MIB.getInstr();
222     ++MBBI;
223 
224     // Form IT block.
225     ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
226     unsigned Mask = 0, Pos = 3;
227 
228     // IT blocks are limited to one conditional op if -arm-restrict-it
229     // is set: skip the loop
230     if (!restrictIT) {
231       LLVM_DEBUG(dbgs() << "Allowing complex IT block\n";);
232       // Branches, including tricky ones like LDM_RET, need to end an IT
233       // block so check the instruction we just put in the block.
234       for (; MBBI != E && Pos &&
235              (!MI->isBranch() && !MI->isReturn()) ; ++MBBI) {
236         if (MBBI->isDebugInstr())
237           continue;
238 
239         MachineInstr *NMI = &*MBBI;
240         MI = NMI;
241 
242         Register NPredReg;
243         ARMCC::CondCodes NCC = getITInstrPredicate(*NMI, NPredReg);
244         if (NCC == CC || NCC == OCC) {
245           Mask |= ((NCC ^ CC) & 1) << Pos;
246           // Add implicit use of ITSTATE.
247           NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
248                                                  true/*isImp*/, false/*isKill*/));
249           LastITMI = NMI;
250         } else {
251           if (NCC == ARMCC::AL &&
252               MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) {
253             --MBBI;
254             MBB.remove(NMI);
255             MBB.insert(InsertPos, NMI);
256             ClearKillFlags(MI, Uses);
257             ++NumMovedInsts;
258             continue;
259           }
260           break;
261         }
262         TrackDefUses(NMI, Defs, Uses, TRI);
263         --Pos;
264       }
265     }
266 
267     // Finalize IT mask.
268     Mask |= (1 << Pos);
269     MIB.addImm(Mask);
270 
271     // Last instruction in IT block kills ITSTATE.
272     LastITMI->findRegisterUseOperand(ARM::ITSTATE)->setIsKill();
273 
274     // Finalize the bundle.
275     finalizeBundle(MBB, InsertPos.getInstrIterator(),
276                    ++LastITMI->getIterator());
277 
278     Modified = true;
279     ++NumITs;
280   }
281 
282   return Modified;
283 }
284 
285 bool Thumb2ITBlock::runOnMachineFunction(MachineFunction &Fn) {
286   const ARMSubtarget &STI = Fn.getSubtarget<ARMSubtarget>();
287   if (!STI.isThumb2())
288     return false;
289   AFI = Fn.getInfo<ARMFunctionInfo>();
290   TII = static_cast<const Thumb2InstrInfo *>(STI.getInstrInfo());
291   TRI = STI.getRegisterInfo();
292   restrictIT = STI.restrictIT();
293 
294   if (!AFI->isThumbFunction())
295     return false;
296 
297   bool Modified = false;
298   for (auto &MBB : Fn )
299     Modified |= InsertITInstructions(MBB);
300 
301   if (Modified)
302     AFI->setHasITBlocks(true);
303 
304   return Modified;
305 }
306 
307 /// createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks
308 /// insertion pass.
309 FunctionPass *llvm::createThumb2ITBlockPass() { return new Thumb2ITBlock(); }
310