1 //===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information --------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "Thumb2InstrInfo.h"
14 #include "ARMMachineFunctionInfo.h"
15 #include "ARMSubtarget.h"
16 #include "MCTargetDesc/ARMAddressingModes.h"
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstr.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineMemOperand.h"
23 #include "llvm/CodeGen/MachineOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/TargetRegisterInfo.h"
26 #include "llvm/IR/DebugLoc.h"
27 #include "llvm/MC/MCInst.h"
28 #include "llvm/MC/MCInstBuilder.h"
29 #include "llvm/MC/MCInstrDesc.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include <cassert>
35 
36 using namespace llvm;
37 
38 static cl::opt<bool>
39 OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden,
40            cl::desc("Use old-style Thumb2 if-conversion heuristics"),
41            cl::init(false));
42 
43 static cl::opt<bool>
44 PreferNoCSEL("prefer-no-csel", cl::Hidden,
45              cl::desc("Prefer predicated Move to CSEL"),
46              cl::init(false));
47 
48 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
49     : ARMBaseInstrInfo(STI) {}
50 
51 /// Return the noop instruction to use for a noop.
52 MCInst Thumb2InstrInfo::getNop() const {
53   return MCInstBuilder(ARM::tHINT).addImm(0).addImm(ARMCC::AL).addReg(0);
54 }
55 
56 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
57   // FIXME
58   return 0;
59 }
60 
61 void
62 Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
63                                          MachineBasicBlock *NewDest) const {
64   MachineBasicBlock *MBB = Tail->getParent();
65   ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
66   if (!AFI->hasITBlocks() || Tail->isBranch()) {
67     TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest);
68     return;
69   }
70 
71   // If the first instruction of Tail is predicated, we may have to update
72   // the IT instruction.
73   Register PredReg;
74   ARMCC::CondCodes CC = getInstrPredicate(*Tail, PredReg);
75   MachineBasicBlock::iterator MBBI = Tail;
76   if (CC != ARMCC::AL)
77     // Expecting at least the t2IT instruction before it.
78     --MBBI;
79 
80   // Actually replace the tail.
81   TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest);
82 
83   // Fix up IT.
84   if (CC != ARMCC::AL) {
85     MachineBasicBlock::iterator E = MBB->begin();
86     unsigned Count = 4; // At most 4 instructions in an IT block.
87     while (Count && MBBI != E) {
88       if (MBBI->isDebugInstr()) {
89         --MBBI;
90         continue;
91       }
92       if (MBBI->getOpcode() == ARM::t2IT) {
93         unsigned Mask = MBBI->getOperand(1).getImm();
94         if (Count == 4)
95           MBBI->eraseFromParent();
96         else {
97           unsigned MaskOn = 1 << Count;
98           unsigned MaskOff = ~(MaskOn - 1);
99           MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
100         }
101         return;
102       }
103       --MBBI;
104       --Count;
105     }
106 
107     // Ctrl flow can reach here if branch folding is run before IT block
108     // formation pass.
109   }
110 }
111 
112 bool
113 Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
114                                      MachineBasicBlock::iterator MBBI) const {
115   while (MBBI->isDebugInstr()) {
116     ++MBBI;
117     if (MBBI == MBB.end())
118       return false;
119   }
120 
121   Register PredReg;
122   return getITInstrPredicate(*MBBI, PredReg) == ARMCC::AL;
123 }
124 
125 MachineInstr *
126 Thumb2InstrInfo::optimizeSelect(MachineInstr &MI,
127                                 SmallPtrSetImpl<MachineInstr *> &SeenMIs,
128                                 bool PreferFalse) const {
129   // Try to use the base optimizeSelect, which uses canFoldIntoMOVCC to fold the
130   // MOVCC into another instruction. If that fails on 8.1-M fall back to using a
131   // CSEL.
132   MachineInstr *RV = ARMBaseInstrInfo::optimizeSelect(MI, SeenMIs, PreferFalse);
133   if (!RV && getSubtarget().hasV8_1MMainlineOps() && !PreferNoCSEL) {
134     Register DestReg = MI.getOperand(0).getReg();
135 
136     if (!DestReg.isVirtual())
137       return nullptr;
138 
139     MachineInstrBuilder NewMI = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
140                                         get(ARM::t2CSEL), DestReg)
141                                     .add(MI.getOperand(2))
142                                     .add(MI.getOperand(1))
143                                     .add(MI.getOperand(3));
144     SeenMIs.insert(NewMI);
145     return NewMI;
146   }
147   return RV;
148 }
149 
150 void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
151                                   MachineBasicBlock::iterator I,
152                                   const DebugLoc &DL, MCRegister DestReg,
153                                   MCRegister SrcReg, bool KillSrc) const {
154   // Handle SPR, DPR, and QPR copies.
155   if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
156     return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
157 
158   BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
159       .addReg(SrcReg, getKillRegState(KillSrc))
160       .add(predOps(ARMCC::AL));
161 }
162 
163 void Thumb2InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
164                                           MachineBasicBlock::iterator I,
165                                           Register SrcReg, bool isKill, int FI,
166                                           const TargetRegisterClass *RC,
167                                           const TargetRegisterInfo *TRI,
168                                           Register VReg) const {
169   DebugLoc DL;
170   if (I != MBB.end()) DL = I->getDebugLoc();
171 
172   MachineFunction &MF = *MBB.getParent();
173   MachineFrameInfo &MFI = MF.getFrameInfo();
174   MachineMemOperand *MMO = MF.getMachineMemOperand(
175       MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
176       MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
177 
178   if (ARM::GPRRegClass.hasSubClassEq(RC)) {
179     BuildMI(MBB, I, DL, get(ARM::t2STRi12))
180         .addReg(SrcReg, getKillRegState(isKill))
181         .addFrameIndex(FI)
182         .addImm(0)
183         .addMemOperand(MMO)
184         .add(predOps(ARMCC::AL));
185     return;
186   }
187 
188   if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
189     // Thumb2 STRD expects its dest-registers to be in rGPR. Not a problem for
190     // gsub_0, but needs an extra constraint for gsub_1 (which could be sp
191     // otherwise).
192     if (SrcReg.isVirtual()) {
193       MachineRegisterInfo *MRI = &MF.getRegInfo();
194       MRI->constrainRegClass(SrcReg, &ARM::GPRPairnospRegClass);
195     }
196 
197     MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
198     AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
199     AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
200     MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO).add(predOps(ARMCC::AL));
201     return;
202   }
203 
204   ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI,
205                                         Register());
206 }
207 
208 void Thumb2InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
209                                            MachineBasicBlock::iterator I,
210                                            Register DestReg, int FI,
211                                            const TargetRegisterClass *RC,
212                                            const TargetRegisterInfo *TRI,
213                                            Register VReg) const {
214   MachineFunction &MF = *MBB.getParent();
215   MachineFrameInfo &MFI = MF.getFrameInfo();
216   MachineMemOperand *MMO = MF.getMachineMemOperand(
217       MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
218       MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
219   DebugLoc DL;
220   if (I != MBB.end()) DL = I->getDebugLoc();
221 
222   if (ARM::GPRRegClass.hasSubClassEq(RC)) {
223     BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
224         .addFrameIndex(FI)
225         .addImm(0)
226         .addMemOperand(MMO)
227         .add(predOps(ARMCC::AL));
228     return;
229   }
230 
231   if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
232     // Thumb2 LDRD expects its dest-registers to be in rGPR. Not a problem for
233     // gsub_0, but needs an extra constraint for gsub_1 (which could be sp
234     // otherwise).
235     if (DestReg.isVirtual()) {
236       MachineRegisterInfo *MRI = &MF.getRegInfo();
237       MRI->constrainRegClass(DestReg, &ARM::GPRPairnospRegClass);
238     }
239 
240     MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
241     AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
242     AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
243     MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO).add(predOps(ARMCC::AL));
244 
245     if (DestReg.isPhysical())
246       MIB.addReg(DestReg, RegState::ImplicitDefine);
247     return;
248   }
249 
250   ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI,
251                                          Register());
252 }
253 
254 void Thumb2InstrInfo::expandLoadStackGuard(
255     MachineBasicBlock::iterator MI) const {
256   MachineFunction &MF = *MI->getParent()->getParent();
257   Module &M = *MF.getFunction().getParent();
258 
259   if (M.getStackProtectorGuard() == "tls") {
260     expandLoadStackGuardBase(MI, ARM::t2MRC, ARM::t2LDRi12);
261     return;
262   }
263 
264   const auto *GV = cast<GlobalValue>((*MI->memoperands_begin())->getValue());
265   if (MF.getSubtarget<ARMSubtarget>().isTargetELF() && !GV->isDSOLocal())
266     expandLoadStackGuardBase(MI, ARM::t2LDRLIT_ga_pcrel, ARM::t2LDRi12);
267   else if (MF.getTarget().isPositionIndependent())
268     expandLoadStackGuardBase(MI, ARM::t2MOV_ga_pcrel, ARM::t2LDRi12);
269   else
270     expandLoadStackGuardBase(MI, ARM::t2MOVi32imm, ARM::t2LDRi12);
271 }
272 
273 MachineInstr *Thumb2InstrInfo::commuteInstructionImpl(MachineInstr &MI,
274                                                       bool NewMI,
275                                                       unsigned OpIdx1,
276                                                       unsigned OpIdx2) const {
277   switch (MI.getOpcode()) {
278   case ARM::MVE_VMAXNMAf16:
279   case ARM::MVE_VMAXNMAf32:
280   case ARM::MVE_VMINNMAf16:
281   case ARM::MVE_VMINNMAf32:
282     // Don't allow predicated instructions to be commuted.
283     if (getVPTInstrPredicate(MI) != ARMVCC::None)
284       return nullptr;
285   }
286   return ARMBaseInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
287 }
288 
289 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
290                                   MachineBasicBlock::iterator &MBBI,
291                                   const DebugLoc &dl, Register DestReg,
292                                   Register BaseReg, int NumBytes,
293                                   ARMCC::CondCodes Pred, Register PredReg,
294                                   const ARMBaseInstrInfo &TII,
295                                   unsigned MIFlags) {
296   if (NumBytes == 0 && DestReg != BaseReg) {
297     BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
298       .addReg(BaseReg, RegState::Kill)
299       .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
300     return;
301   }
302 
303   bool isSub = NumBytes < 0;
304   if (isSub) NumBytes = -NumBytes;
305 
306   // If profitable, use a movw or movt to materialize the offset.
307   // FIXME: Use the scavenger to grab a scratch register.
308   if (DestReg != ARM::SP && DestReg != BaseReg &&
309       NumBytes >= 4096 &&
310       ARM_AM::getT2SOImmVal(NumBytes) == -1) {
311     bool Fits = false;
312     if (NumBytes < 65536) {
313       // Use a movw to materialize the 16-bit constant.
314       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
315         .addImm(NumBytes)
316         .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
317       Fits = true;
318     } else if ((NumBytes & 0xffff) == 0) {
319       // Use a movt to materialize the 32-bit constant.
320       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
321         .addReg(DestReg)
322         .addImm(NumBytes >> 16)
323         .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
324       Fits = true;
325     }
326 
327     if (Fits) {
328       if (isSub) {
329         BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
330             .addReg(BaseReg)
331             .addReg(DestReg, RegState::Kill)
332             .add(predOps(Pred, PredReg))
333             .add(condCodeOp())
334             .setMIFlags(MIFlags);
335       } else {
336         // Here we know that DestReg is not SP but we do not
337         // know anything about BaseReg. t2ADDrr is an invalid
338         // instruction is SP is used as the second argument, but
339         // is fine if SP is the first argument. To be sure we
340         // do not generate invalid encoding, put BaseReg first.
341         BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
342             .addReg(BaseReg)
343             .addReg(DestReg, RegState::Kill)
344             .add(predOps(Pred, PredReg))
345             .add(condCodeOp())
346             .setMIFlags(MIFlags);
347       }
348       return;
349     }
350   }
351 
352   while (NumBytes) {
353     unsigned ThisVal = NumBytes;
354     unsigned Opc = 0;
355     if (DestReg == ARM::SP && BaseReg != ARM::SP) {
356       // mov sp, rn. Note t2MOVr cannot be used.
357       BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
358           .addReg(BaseReg)
359           .setMIFlags(MIFlags)
360           .add(predOps(ARMCC::AL));
361       BaseReg = ARM::SP;
362       continue;
363     }
364 
365     assert((DestReg != ARM::SP || BaseReg == ARM::SP) &&
366            "Writing to SP, from other register.");
367 
368     // Try to use T1, as it smaller
369     if ((DestReg == ARM::SP) && (ThisVal < ((1 << 7) - 1) * 4)) {
370       assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
371       Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
372       BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
373           .addReg(BaseReg)
374           .addImm(ThisVal / 4)
375           .setMIFlags(MIFlags)
376           .add(predOps(ARMCC::AL));
377       break;
378     }
379     bool HasCCOut = true;
380     int ImmIsT2SO = ARM_AM::getT2SOImmVal(ThisVal);
381     bool ToSP = DestReg == ARM::SP;
382     unsigned t2SUB = ToSP ? ARM::t2SUBspImm : ARM::t2SUBri;
383     unsigned t2ADD = ToSP ? ARM::t2ADDspImm : ARM::t2ADDri;
384     unsigned t2SUBi12 = ToSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12;
385     unsigned t2ADDi12 = ToSP ? ARM::t2ADDspImm12 : ARM::t2ADDri12;
386     Opc = isSub ? t2SUB : t2ADD;
387     // Prefer T2: sub rd, rn, so_imm | sub sp, sp, so_imm
388     if (ImmIsT2SO != -1) {
389       NumBytes = 0;
390     } else if (ThisVal < 4096) {
391       // Prefer T3 if can make it in a single go: subw rd, rn, imm12 | subw sp,
392       // sp, imm12
393       Opc = isSub ? t2SUBi12 : t2ADDi12;
394       HasCCOut = false;
395       NumBytes = 0;
396     } else {
397       // Use one T2 instruction to reduce NumBytes
398       // FIXME: Move this to ARMAddressingModes.h?
399       unsigned RotAmt = llvm::countl_zero(ThisVal);
400       ThisVal = ThisVal & llvm::rotr<uint32_t>(0xff000000U, RotAmt);
401       NumBytes &= ~ThisVal;
402       assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
403              "Bit extraction didn't work?");
404     }
405 
406     // Build the new ADD / SUB.
407     MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
408                                   .addReg(BaseReg, RegState::Kill)
409                                   .addImm(ThisVal)
410                                   .add(predOps(ARMCC::AL))
411                                   .setMIFlags(MIFlags);
412     if (HasCCOut)
413       MIB.add(condCodeOp());
414 
415     BaseReg = DestReg;
416   }
417 }
418 
419 static unsigned
420 negativeOffsetOpcode(unsigned opcode)
421 {
422   switch (opcode) {
423   case ARM::t2LDRi12:   return ARM::t2LDRi8;
424   case ARM::t2LDRHi12:  return ARM::t2LDRHi8;
425   case ARM::t2LDRBi12:  return ARM::t2LDRBi8;
426   case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
427   case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
428   case ARM::t2STRi12:   return ARM::t2STRi8;
429   case ARM::t2STRBi12:  return ARM::t2STRBi8;
430   case ARM::t2STRHi12:  return ARM::t2STRHi8;
431   case ARM::t2PLDi12:   return ARM::t2PLDi8;
432   case ARM::t2PLDWi12:  return ARM::t2PLDWi8;
433   case ARM::t2PLIi12:   return ARM::t2PLIi8;
434 
435   case ARM::t2LDRi8:
436   case ARM::t2LDRHi8:
437   case ARM::t2LDRBi8:
438   case ARM::t2LDRSHi8:
439   case ARM::t2LDRSBi8:
440   case ARM::t2STRi8:
441   case ARM::t2STRBi8:
442   case ARM::t2STRHi8:
443   case ARM::t2PLDi8:
444   case ARM::t2PLDWi8:
445   case ARM::t2PLIi8:
446     return opcode;
447 
448   default:
449     llvm_unreachable("unknown thumb2 opcode.");
450   }
451 }
452 
453 static unsigned
454 positiveOffsetOpcode(unsigned opcode)
455 {
456   switch (opcode) {
457   case ARM::t2LDRi8:   return ARM::t2LDRi12;
458   case ARM::t2LDRHi8:  return ARM::t2LDRHi12;
459   case ARM::t2LDRBi8:  return ARM::t2LDRBi12;
460   case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
461   case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
462   case ARM::t2STRi8:   return ARM::t2STRi12;
463   case ARM::t2STRBi8:  return ARM::t2STRBi12;
464   case ARM::t2STRHi8:  return ARM::t2STRHi12;
465   case ARM::t2PLDi8:   return ARM::t2PLDi12;
466   case ARM::t2PLDWi8:  return ARM::t2PLDWi12;
467   case ARM::t2PLIi8:   return ARM::t2PLIi12;
468 
469   case ARM::t2LDRi12:
470   case ARM::t2LDRHi12:
471   case ARM::t2LDRBi12:
472   case ARM::t2LDRSHi12:
473   case ARM::t2LDRSBi12:
474   case ARM::t2STRi12:
475   case ARM::t2STRBi12:
476   case ARM::t2STRHi12:
477   case ARM::t2PLDi12:
478   case ARM::t2PLDWi12:
479   case ARM::t2PLIi12:
480     return opcode;
481 
482   default:
483     llvm_unreachable("unknown thumb2 opcode.");
484   }
485 }
486 
487 static unsigned
488 immediateOffsetOpcode(unsigned opcode)
489 {
490   switch (opcode) {
491   case ARM::t2LDRs:   return ARM::t2LDRi12;
492   case ARM::t2LDRHs:  return ARM::t2LDRHi12;
493   case ARM::t2LDRBs:  return ARM::t2LDRBi12;
494   case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
495   case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
496   case ARM::t2STRs:   return ARM::t2STRi12;
497   case ARM::t2STRBs:  return ARM::t2STRBi12;
498   case ARM::t2STRHs:  return ARM::t2STRHi12;
499   case ARM::t2PLDs:   return ARM::t2PLDi12;
500   case ARM::t2PLDWs:  return ARM::t2PLDWi12;
501   case ARM::t2PLIs:   return ARM::t2PLIi12;
502 
503   case ARM::t2LDRi12:
504   case ARM::t2LDRHi12:
505   case ARM::t2LDRBi12:
506   case ARM::t2LDRSHi12:
507   case ARM::t2LDRSBi12:
508   case ARM::t2STRi12:
509   case ARM::t2STRBi12:
510   case ARM::t2STRHi12:
511   case ARM::t2PLDi12:
512   case ARM::t2PLDWi12:
513   case ARM::t2PLIi12:
514   case ARM::t2LDRi8:
515   case ARM::t2LDRHi8:
516   case ARM::t2LDRBi8:
517   case ARM::t2LDRSHi8:
518   case ARM::t2LDRSBi8:
519   case ARM::t2STRi8:
520   case ARM::t2STRBi8:
521   case ARM::t2STRHi8:
522   case ARM::t2PLDi8:
523   case ARM::t2PLDWi8:
524   case ARM::t2PLIi8:
525     return opcode;
526 
527   default:
528     llvm_unreachable("unknown thumb2 opcode.");
529   }
530 }
531 
532 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
533                                Register FrameReg, int &Offset,
534                                const ARMBaseInstrInfo &TII,
535                                const TargetRegisterInfo *TRI) {
536   unsigned Opcode = MI.getOpcode();
537   const MCInstrDesc &Desc = MI.getDesc();
538   unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
539   bool isSub = false;
540 
541   MachineFunction &MF = *MI.getParent()->getParent();
542   const TargetRegisterClass *RegClass =
543       TII.getRegClass(Desc, FrameRegIdx, TRI, MF);
544 
545   // Memory operands in inline assembly always use AddrModeT2_i12.
546   if (Opcode == ARM::INLINEASM || Opcode == ARM::INLINEASM_BR)
547     AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
548 
549   const bool IsSP = Opcode == ARM::t2ADDspImm12 || Opcode == ARM::t2ADDspImm;
550   if (IsSP || Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
551     Offset += MI.getOperand(FrameRegIdx+1).getImm();
552 
553     Register PredReg;
554     if (Offset == 0 && getInstrPredicate(MI, PredReg) == ARMCC::AL &&
555         !MI.definesRegister(ARM::CPSR)) {
556       // Turn it into a move.
557       MI.setDesc(TII.get(ARM::tMOVr));
558       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
559       // Remove offset and remaining explicit predicate operands.
560       do MI.removeOperand(FrameRegIdx+1);
561       while (MI.getNumOperands() > FrameRegIdx+1);
562       MachineInstrBuilder MIB(*MI.getParent()->getParent(), &MI);
563       MIB.add(predOps(ARMCC::AL));
564       return true;
565     }
566 
567     bool HasCCOut = (Opcode != ARM::t2ADDspImm12 && Opcode != ARM::t2ADDri12);
568 
569     if (Offset < 0) {
570       Offset = -Offset;
571       isSub = true;
572       MI.setDesc(IsSP ? TII.get(ARM::t2SUBspImm) : TII.get(ARM::t2SUBri));
573     } else {
574       MI.setDesc(IsSP ? TII.get(ARM::t2ADDspImm) : TII.get(ARM::t2ADDri));
575     }
576 
577     // Common case: small offset, fits into instruction.
578     if (ARM_AM::getT2SOImmVal(Offset) != -1) {
579       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
580       MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
581       // Add cc_out operand if the original instruction did not have one.
582       if (!HasCCOut)
583         MI.addOperand(MachineOperand::CreateReg(0, false));
584       Offset = 0;
585       return true;
586     }
587     // Another common case: imm12.
588     if (Offset < 4096 &&
589         (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
590       unsigned NewOpc = isSub ? IsSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12
591                               : IsSP ? ARM::t2ADDspImm12 : ARM::t2ADDri12;
592       MI.setDesc(TII.get(NewOpc));
593       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
594       MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
595       // Remove the cc_out operand.
596       if (HasCCOut)
597         MI.removeOperand(MI.getNumOperands()-1);
598       Offset = 0;
599       return true;
600     }
601 
602     // Otherwise, extract 8 adjacent bits from the immediate into this
603     // t2ADDri/t2SUBri.
604     unsigned RotAmt = llvm::countl_zero<unsigned>(Offset);
605     unsigned ThisImmVal = Offset & llvm::rotr<uint32_t>(0xff000000U, RotAmt);
606 
607     // We will handle these bits from offset, clear them.
608     Offset &= ~ThisImmVal;
609 
610     assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
611            "Bit extraction didn't work?");
612     MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
613     // Add cc_out operand if the original instruction did not have one.
614     if (!HasCCOut)
615       MI.addOperand(MachineOperand::CreateReg(0, false));
616   } else {
617     // AddrMode4 and AddrMode6 cannot handle any offset.
618     if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
619       return false;
620 
621     // AddrModeT2_so cannot handle any offset. If there is no offset
622     // register then we change to an immediate version.
623     unsigned NewOpc = Opcode;
624     if (AddrMode == ARMII::AddrModeT2_so) {
625       Register OffsetReg = MI.getOperand(FrameRegIdx + 1).getReg();
626       if (OffsetReg != 0) {
627         MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
628         return Offset == 0;
629       }
630 
631       MI.removeOperand(FrameRegIdx+1);
632       MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
633       NewOpc = immediateOffsetOpcode(Opcode);
634       AddrMode = ARMII::AddrModeT2_i12;
635     }
636 
637     unsigned NumBits = 0;
638     unsigned Scale = 1;
639     if (AddrMode == ARMII::AddrModeT2_i8neg ||
640         AddrMode == ARMII::AddrModeT2_i12) {
641       // i8 supports only negative, and i12 supports only positive, so
642       // based on Offset sign convert Opcode to the appropriate
643       // instruction
644       Offset += MI.getOperand(FrameRegIdx+1).getImm();
645       if (Offset < 0) {
646         NewOpc = negativeOffsetOpcode(Opcode);
647         NumBits = 8;
648         isSub = true;
649         Offset = -Offset;
650       } else {
651         NewOpc = positiveOffsetOpcode(Opcode);
652         NumBits = 12;
653       }
654     } else if (AddrMode == ARMII::AddrMode5) {
655       // VFP address mode.
656       const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
657       int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
658       if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
659         InstrOffs *= -1;
660       NumBits = 8;
661       Scale = 4;
662       Offset += InstrOffs * 4;
663       assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
664       if (Offset < 0) {
665         Offset = -Offset;
666         isSub = true;
667       }
668     } else if (AddrMode == ARMII::AddrMode5FP16) {
669       // VFP address mode.
670       const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
671       int InstrOffs = ARM_AM::getAM5FP16Offset(OffOp.getImm());
672       if (ARM_AM::getAM5FP16Op(OffOp.getImm()) == ARM_AM::sub)
673         InstrOffs *= -1;
674       NumBits = 8;
675       Scale = 2;
676       Offset += InstrOffs * 2;
677       assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
678       if (Offset < 0) {
679         Offset = -Offset;
680         isSub = true;
681       }
682     } else if (AddrMode == ARMII::AddrModeT2_i7s4 ||
683                AddrMode == ARMII::AddrModeT2_i7s2 ||
684                AddrMode == ARMII::AddrModeT2_i7) {
685       Offset += MI.getOperand(FrameRegIdx + 1).getImm();
686       unsigned OffsetMask;
687       switch (AddrMode) {
688       case ARMII::AddrModeT2_i7s4: NumBits = 9; OffsetMask = 0x3; break;
689       case ARMII::AddrModeT2_i7s2: NumBits = 8; OffsetMask = 0x1; break;
690       default:                     NumBits = 7; OffsetMask = 0x0; break;
691       }
692       // MCInst operand expects already scaled value.
693       Scale = 1;
694       assert((Offset & OffsetMask) == 0 && "Can't encode this offset!");
695       (void)OffsetMask; // squash unused-variable warning at -NDEBUG
696     } else if (AddrMode == ARMII::AddrModeT2_i8s4) {
697       Offset += MI.getOperand(FrameRegIdx + 1).getImm();
698       NumBits = 8 + 2;
699       // MCInst operand expects already scaled value.
700       Scale = 1;
701       assert((Offset & 3) == 0 && "Can't encode this offset!");
702     } else if (AddrMode == ARMII::AddrModeT2_ldrex) {
703       Offset += MI.getOperand(FrameRegIdx + 1).getImm() * 4;
704       NumBits = 8; // 8 bits scaled by 4
705       Scale = 4;
706       assert((Offset & 3) == 0 && "Can't encode this offset!");
707     } else {
708       llvm_unreachable("Unsupported addressing mode!");
709     }
710 
711     if (NewOpc != Opcode)
712       MI.setDesc(TII.get(NewOpc));
713 
714     MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
715 
716     // Attempt to fold address computation
717     // Common case: small offset, fits into instruction. We need to make sure
718     // the register class is correct too, for instructions like the MVE
719     // VLDRH.32, which only accepts low tGPR registers.
720     int ImmedOffset = Offset / Scale;
721     unsigned Mask = (1 << NumBits) - 1;
722     if ((unsigned)Offset <= Mask * Scale &&
723         (FrameReg.isVirtual() || RegClass->contains(FrameReg))) {
724       if (FrameReg.isVirtual()) {
725         // Make sure the register class for the virtual register is correct
726         MachineRegisterInfo *MRI = &MF.getRegInfo();
727         if (!MRI->constrainRegClass(FrameReg, RegClass))
728           llvm_unreachable("Unable to constrain virtual register class.");
729       }
730 
731       // Replace the FrameIndex with fp/sp
732       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
733       if (isSub) {
734         if (AddrMode == ARMII::AddrMode5 || AddrMode == ARMII::AddrMode5FP16)
735           // FIXME: Not consistent.
736           ImmedOffset |= 1 << NumBits;
737         else
738           ImmedOffset = -ImmedOffset;
739       }
740       ImmOp.ChangeToImmediate(ImmedOffset);
741       Offset = 0;
742       return true;
743     }
744 
745     // Otherwise, offset doesn't fit. Pull in what we can to simplify
746     ImmedOffset = ImmedOffset & Mask;
747     if (isSub) {
748       if (AddrMode == ARMII::AddrMode5 || AddrMode == ARMII::AddrMode5FP16)
749         // FIXME: Not consistent.
750         ImmedOffset |= 1 << NumBits;
751       else {
752         ImmedOffset = -ImmedOffset;
753         if (ImmedOffset == 0)
754           // Change the opcode back if the encoded offset is zero.
755           MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
756       }
757     }
758     ImmOp.ChangeToImmediate(ImmedOffset);
759     Offset &= ~(Mask*Scale);
760   }
761 
762   Offset = (isSub) ? -Offset : Offset;
763   return Offset == 0 && (FrameReg.isVirtual() || RegClass->contains(FrameReg));
764 }
765 
766 ARMCC::CondCodes llvm::getITInstrPredicate(const MachineInstr &MI,
767                                            Register &PredReg) {
768   unsigned Opc = MI.getOpcode();
769   if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
770     return ARMCC::AL;
771   return getInstrPredicate(MI, PredReg);
772 }
773 
774 int llvm::findFirstVPTPredOperandIdx(const MachineInstr &MI) {
775   const MCInstrDesc &MCID = MI.getDesc();
776 
777   for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
778     if (ARM::isVpred(MCID.operands()[i].OperandType))
779       return i;
780 
781   return -1;
782 }
783 
784 ARMVCC::VPTCodes llvm::getVPTInstrPredicate(const MachineInstr &MI,
785                                             Register &PredReg) {
786   int PIdx = findFirstVPTPredOperandIdx(MI);
787   if (PIdx == -1) {
788     PredReg = 0;
789     return ARMVCC::None;
790   }
791 
792   PredReg = MI.getOperand(PIdx+1).getReg();
793   return (ARMVCC::VPTCodes)MI.getOperand(PIdx).getImm();
794 }
795 
796 void llvm::recomputeVPTBlockMask(MachineInstr &Instr) {
797   assert(isVPTOpcode(Instr.getOpcode()) && "Not a VPST or VPT Instruction!");
798 
799   MachineOperand &MaskOp = Instr.getOperand(0);
800   assert(MaskOp.isImm() && "Operand 0 is not the block mask of the VPT/VPST?!");
801 
802   MachineBasicBlock::iterator Iter = ++Instr.getIterator(),
803                               End = Instr.getParent()->end();
804 
805   while (Iter != End && Iter->isDebugInstr())
806     ++Iter;
807 
808   // Verify that the instruction after the VPT/VPST is predicated (it should
809   // be), and skip it.
810   assert(Iter != End && "Expected some instructions in any VPT block");
811   assert(
812       getVPTInstrPredicate(*Iter) == ARMVCC::Then &&
813       "VPT/VPST should be followed by an instruction with a 'then' predicate!");
814   ++Iter;
815 
816   // Iterate over the predicated instructions, updating the BlockMask as we go.
817   ARM::PredBlockMask BlockMask = ARM::PredBlockMask::T;
818   while (Iter != End) {
819     if (Iter->isDebugInstr()) {
820       ++Iter;
821       continue;
822     }
823     ARMVCC::VPTCodes Pred = getVPTInstrPredicate(*Iter);
824     if (Pred == ARMVCC::None)
825       break;
826     BlockMask = expandPredBlockMask(BlockMask, Pred);
827     ++Iter;
828   }
829 
830   // Rewrite the BlockMask.
831   MaskOp.setImm((int64_t)(BlockMask));
832 }
833