1 //===-- AVRISelLowering.cpp - AVR DAG Lowering Implementation -------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that AVR uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "AVRISelLowering.h" 15 16 #include "llvm/ADT/StringSwitch.h" 17 #include "llvm/ADT/STLExtras.h" 18 #include "llvm/CodeGen/CallingConvLower.h" 19 #include "llvm/CodeGen/MachineFrameInfo.h" 20 #include "llvm/CodeGen/MachineInstrBuilder.h" 21 #include "llvm/CodeGen/MachineRegisterInfo.h" 22 #include "llvm/CodeGen/SelectionDAG.h" 23 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 24 #include "llvm/IR/Function.h" 25 #include "llvm/Support/ErrorHandling.h" 26 27 #include "AVR.h" 28 #include "AVRMachineFunctionInfo.h" 29 #include "AVRSubtarget.h" 30 #include "AVRTargetMachine.h" 31 #include "MCTargetDesc/AVRMCTargetDesc.h" 32 33 namespace llvm { 34 35 AVRTargetLowering::AVRTargetLowering(const AVRTargetMachine &TM, 36 const AVRSubtarget &STI) 37 : TargetLowering(TM), Subtarget(STI) { 38 // Set up the register classes. 39 addRegisterClass(MVT::i8, &AVR::GPR8RegClass); 40 addRegisterClass(MVT::i16, &AVR::DREGSRegClass); 41 42 // Compute derived properties from the register classes. 43 computeRegisterProperties(Subtarget.getRegisterInfo()); 44 45 setBooleanContents(ZeroOrOneBooleanContent); 46 setBooleanVectorContents(ZeroOrOneBooleanContent); 47 setSchedulingPreference(Sched::RegPressure); 48 setStackPointerRegisterToSaveRestore(AVR::SP); 49 setSupportsUnalignedAtomics(true); 50 51 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom); 52 setOperationAction(ISD::BlockAddress, MVT::i16, Custom); 53 54 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 55 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 56 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand); 57 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand); 58 59 for (MVT VT : MVT::integer_valuetypes()) { 60 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) { 61 setLoadExtAction(N, VT, MVT::i1, Promote); 62 setLoadExtAction(N, VT, MVT::i8, Expand); 63 } 64 } 65 66 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 67 68 for (MVT VT : MVT::integer_valuetypes()) { 69 setOperationAction(ISD::ADDC, VT, Legal); 70 setOperationAction(ISD::SUBC, VT, Legal); 71 setOperationAction(ISD::ADDE, VT, Legal); 72 setOperationAction(ISD::SUBE, VT, Legal); 73 } 74 75 // sub (x, imm) gets canonicalized to add (x, -imm), so for illegal types 76 // revert into a sub since we don't have an add with immediate instruction. 77 setOperationAction(ISD::ADD, MVT::i32, Custom); 78 setOperationAction(ISD::ADD, MVT::i64, Custom); 79 80 // our shift instructions are only able to shift 1 bit at a time, so handle 81 // this in a custom way. 82 setOperationAction(ISD::SRA, MVT::i8, Custom); 83 setOperationAction(ISD::SHL, MVT::i8, Custom); 84 setOperationAction(ISD::SRL, MVT::i8, Custom); 85 setOperationAction(ISD::SRA, MVT::i16, Custom); 86 setOperationAction(ISD::SHL, MVT::i16, Custom); 87 setOperationAction(ISD::SRL, MVT::i16, Custom); 88 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand); 89 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand); 90 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand); 91 92 setOperationAction(ISD::ROTL, MVT::i8, Custom); 93 setOperationAction(ISD::ROTL, MVT::i16, Expand); 94 setOperationAction(ISD::ROTR, MVT::i8, Custom); 95 setOperationAction(ISD::ROTR, MVT::i16, Expand); 96 97 setOperationAction(ISD::BR_CC, MVT::i8, Custom); 98 setOperationAction(ISD::BR_CC, MVT::i16, Custom); 99 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 100 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 101 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 102 103 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); 104 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); 105 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 106 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); 107 setOperationAction(ISD::SETCC, MVT::i8, Custom); 108 setOperationAction(ISD::SETCC, MVT::i16, Custom); 109 setOperationAction(ISD::SETCC, MVT::i32, Custom); 110 setOperationAction(ISD::SETCC, MVT::i64, Custom); 111 setOperationAction(ISD::SELECT, MVT::i8, Expand); 112 setOperationAction(ISD::SELECT, MVT::i16, Expand); 113 114 setOperationAction(ISD::BSWAP, MVT::i16, Expand); 115 116 // Add support for postincrement and predecrement load/stores. 117 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); 118 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); 119 setIndexedLoadAction(ISD::PRE_DEC, MVT::i8, Legal); 120 setIndexedLoadAction(ISD::PRE_DEC, MVT::i16, Legal); 121 setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal); 122 setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal); 123 setIndexedStoreAction(ISD::PRE_DEC, MVT::i8, Legal); 124 setIndexedStoreAction(ISD::PRE_DEC, MVT::i16, Legal); 125 126 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 127 128 setOperationAction(ISD::VASTART, MVT::Other, Custom); 129 setOperationAction(ISD::VAEND, MVT::Other, Expand); 130 setOperationAction(ISD::VAARG, MVT::Other, Expand); 131 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 132 133 // Atomic operations which must be lowered to rtlib calls 134 for (MVT VT : MVT::integer_valuetypes()) { 135 setOperationAction(ISD::ATOMIC_SWAP, VT, Expand); 136 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Expand); 137 setOperationAction(ISD::ATOMIC_LOAD_NAND, VT, Expand); 138 setOperationAction(ISD::ATOMIC_LOAD_MAX, VT, Expand); 139 setOperationAction(ISD::ATOMIC_LOAD_MIN, VT, Expand); 140 setOperationAction(ISD::ATOMIC_LOAD_UMAX, VT, Expand); 141 setOperationAction(ISD::ATOMIC_LOAD_UMIN, VT, Expand); 142 } 143 144 // Division/remainder 145 setOperationAction(ISD::UDIV, MVT::i8, Expand); 146 setOperationAction(ISD::UDIV, MVT::i16, Expand); 147 setOperationAction(ISD::UREM, MVT::i8, Expand); 148 setOperationAction(ISD::UREM, MVT::i16, Expand); 149 setOperationAction(ISD::SDIV, MVT::i8, Expand); 150 setOperationAction(ISD::SDIV, MVT::i16, Expand); 151 setOperationAction(ISD::SREM, MVT::i8, Expand); 152 setOperationAction(ISD::SREM, MVT::i16, Expand); 153 154 // Make division and modulus custom 155 setOperationAction(ISD::UDIVREM, MVT::i8, Custom); 156 setOperationAction(ISD::UDIVREM, MVT::i16, Custom); 157 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); 158 setOperationAction(ISD::SDIVREM, MVT::i8, Custom); 159 setOperationAction(ISD::SDIVREM, MVT::i16, Custom); 160 setOperationAction(ISD::SDIVREM, MVT::i32, Custom); 161 162 // Do not use MUL. The AVR instructions are closer to SMUL_LOHI &co. 163 setOperationAction(ISD::MUL, MVT::i8, Expand); 164 setOperationAction(ISD::MUL, MVT::i16, Expand); 165 166 // Expand 16 bit multiplications. 167 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand); 168 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand); 169 170 // Expand multiplications to libcalls when there is 171 // no hardware MUL. 172 if (!Subtarget.supportsMultiplication()) { 173 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand); 174 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand); 175 } 176 177 for (MVT VT : MVT::integer_valuetypes()) { 178 setOperationAction(ISD::MULHS, VT, Expand); 179 setOperationAction(ISD::MULHU, VT, Expand); 180 } 181 182 for (MVT VT : MVT::integer_valuetypes()) { 183 setOperationAction(ISD::CTPOP, VT, Expand); 184 setOperationAction(ISD::CTLZ, VT, Expand); 185 setOperationAction(ISD::CTTZ, VT, Expand); 186 } 187 188 for (MVT VT : MVT::integer_valuetypes()) { 189 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); 190 // TODO: The generated code is pretty poor. Investigate using the 191 // same "shift and subtract with carry" trick that we do for 192 // extending 8-bit to 16-bit. This may require infrastructure 193 // improvements in how we treat 16-bit "registers" to be feasible. 194 } 195 196 // Division rtlib functions (not supported), use divmod functions instead 197 setLibcallName(RTLIB::SDIV_I8, nullptr); 198 setLibcallName(RTLIB::SDIV_I16, nullptr); 199 setLibcallName(RTLIB::SDIV_I32, nullptr); 200 setLibcallName(RTLIB::UDIV_I8, nullptr); 201 setLibcallName(RTLIB::UDIV_I16, nullptr); 202 setLibcallName(RTLIB::UDIV_I32, nullptr); 203 204 // Modulus rtlib functions (not supported), use divmod functions instead 205 setLibcallName(RTLIB::SREM_I8, nullptr); 206 setLibcallName(RTLIB::SREM_I16, nullptr); 207 setLibcallName(RTLIB::SREM_I32, nullptr); 208 setLibcallName(RTLIB::UREM_I8, nullptr); 209 setLibcallName(RTLIB::UREM_I16, nullptr); 210 setLibcallName(RTLIB::UREM_I32, nullptr); 211 212 // Division and modulus rtlib functions 213 setLibcallName(RTLIB::SDIVREM_I8, "__divmodqi4"); 214 setLibcallName(RTLIB::SDIVREM_I16, "__divmodhi4"); 215 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4"); 216 setLibcallName(RTLIB::UDIVREM_I8, "__udivmodqi4"); 217 setLibcallName(RTLIB::UDIVREM_I16, "__udivmodhi4"); 218 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4"); 219 220 // Several of the runtime library functions use a special calling conv 221 setLibcallCallingConv(RTLIB::SDIVREM_I8, CallingConv::AVR_BUILTIN); 222 setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::AVR_BUILTIN); 223 setLibcallCallingConv(RTLIB::UDIVREM_I8, CallingConv::AVR_BUILTIN); 224 setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::AVR_BUILTIN); 225 226 // Trigonometric rtlib functions 227 setLibcallName(RTLIB::SIN_F32, "sin"); 228 setLibcallName(RTLIB::COS_F32, "cos"); 229 230 setMinFunctionAlignment(Align(2)); 231 setMinimumJumpTableEntries(UINT_MAX); 232 } 233 234 const char *AVRTargetLowering::getTargetNodeName(unsigned Opcode) const { 235 #define NODE(name) \ 236 case AVRISD::name: \ 237 return #name 238 239 switch (Opcode) { 240 default: 241 return nullptr; 242 NODE(RET_FLAG); 243 NODE(RETI_FLAG); 244 NODE(CALL); 245 NODE(WRAPPER); 246 NODE(LSL); 247 NODE(LSR); 248 NODE(ROL); 249 NODE(ROR); 250 NODE(ASR); 251 NODE(LSLLOOP); 252 NODE(LSRLOOP); 253 NODE(ROLLOOP); 254 NODE(RORLOOP); 255 NODE(ASRLOOP); 256 NODE(BRCOND); 257 NODE(CMP); 258 NODE(CMPC); 259 NODE(TST); 260 NODE(SELECT_CC); 261 #undef NODE 262 } 263 } 264 265 EVT AVRTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &, 266 EVT VT) const { 267 assert(!VT.isVector() && "No AVR SetCC type for vectors!"); 268 return MVT::i8; 269 } 270 271 SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const { 272 //:TODO: this function has to be completely rewritten to produce optimal 273 // code, for now it's producing very long but correct code. 274 unsigned Opc8; 275 const SDNode *N = Op.getNode(); 276 EVT VT = Op.getValueType(); 277 SDLoc dl(N); 278 assert(isPowerOf2_32(VT.getSizeInBits()) && 279 "Expected power-of-2 shift amount"); 280 281 // Expand non-constant shifts to loops. 282 if (!isa<ConstantSDNode>(N->getOperand(1))) { 283 switch (Op.getOpcode()) { 284 default: 285 llvm_unreachable("Invalid shift opcode!"); 286 case ISD::SHL: 287 return DAG.getNode(AVRISD::LSLLOOP, dl, VT, N->getOperand(0), 288 N->getOperand(1)); 289 case ISD::SRL: 290 return DAG.getNode(AVRISD::LSRLOOP, dl, VT, N->getOperand(0), 291 N->getOperand(1)); 292 case ISD::ROTL: { 293 SDValue Amt = N->getOperand(1); 294 EVT AmtVT = Amt.getValueType(); 295 Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt, 296 DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT)); 297 return DAG.getNode(AVRISD::ROLLOOP, dl, VT, N->getOperand(0), Amt); 298 } 299 case ISD::ROTR: { 300 SDValue Amt = N->getOperand(1); 301 EVT AmtVT = Amt.getValueType(); 302 Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt, 303 DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT)); 304 return DAG.getNode(AVRISD::RORLOOP, dl, VT, N->getOperand(0), Amt); 305 } 306 case ISD::SRA: 307 return DAG.getNode(AVRISD::ASRLOOP, dl, VT, N->getOperand(0), 308 N->getOperand(1)); 309 } 310 } 311 312 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 313 SDValue Victim = N->getOperand(0); 314 315 switch (Op.getOpcode()) { 316 case ISD::SRA: 317 Opc8 = AVRISD::ASR; 318 break; 319 case ISD::ROTL: 320 Opc8 = AVRISD::ROL; 321 ShiftAmount = ShiftAmount % VT.getSizeInBits(); 322 break; 323 case ISD::ROTR: 324 Opc8 = AVRISD::ROR; 325 ShiftAmount = ShiftAmount % VT.getSizeInBits(); 326 break; 327 case ISD::SRL: 328 Opc8 = AVRISD::LSR; 329 break; 330 case ISD::SHL: 331 Opc8 = AVRISD::LSL; 332 break; 333 default: 334 llvm_unreachable("Invalid shift opcode"); 335 } 336 337 // Optimize int8 shifts. 338 if (VT.getSizeInBits() == 8) { 339 if (Op.getOpcode() == ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) { 340 // Optimize LSL when 4 <= ShiftAmount <= 6. 341 Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim); 342 Victim = 343 DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0xf0, dl, VT)); 344 ShiftAmount -= 4; 345 } else if (Op.getOpcode() == ISD::SRL && 4 <= ShiftAmount && 346 ShiftAmount < 7) { 347 // Optimize LSR when 4 <= ShiftAmount <= 6. 348 Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim); 349 Victim = 350 DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0x0f, dl, VT)); 351 ShiftAmount -= 4; 352 } else if (Op.getOpcode() == ISD::SHL && ShiftAmount == 7) { 353 // Optimize LSL when ShiftAmount == 7. 354 Victim = DAG.getNode(AVRISD::LSL7, dl, VT, Victim); 355 ShiftAmount = 0; 356 } else if (Op.getOpcode() == ISD::SRL && ShiftAmount == 7) { 357 // Optimize LSR when ShiftAmount == 7. 358 Victim = DAG.getNode(AVRISD::LSR7, dl, VT, Victim); 359 ShiftAmount = 0; 360 } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 7) { 361 // Optimize ASR when ShiftAmount == 7. 362 Victim = DAG.getNode(AVRISD::ASR7, dl, VT, Victim); 363 ShiftAmount = 0; 364 } 365 } 366 367 while (ShiftAmount--) { 368 Victim = DAG.getNode(Opc8, dl, VT, Victim); 369 } 370 371 return Victim; 372 } 373 374 SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const { 375 unsigned Opcode = Op->getOpcode(); 376 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && 377 "Invalid opcode for Div/Rem lowering"); 378 bool IsSigned = (Opcode == ISD::SDIVREM); 379 EVT VT = Op->getValueType(0); 380 Type *Ty = VT.getTypeForEVT(*DAG.getContext()); 381 382 RTLIB::Libcall LC; 383 switch (VT.getSimpleVT().SimpleTy) { 384 default: 385 llvm_unreachable("Unexpected request for libcall!"); 386 case MVT::i8: 387 LC = IsSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; 388 break; 389 case MVT::i16: 390 LC = IsSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; 391 break; 392 case MVT::i32: 393 LC = IsSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; 394 break; 395 } 396 397 SDValue InChain = DAG.getEntryNode(); 398 399 TargetLowering::ArgListTy Args; 400 TargetLowering::ArgListEntry Entry; 401 for (SDValue const &Value : Op->op_values()) { 402 Entry.Node = Value; 403 Entry.Ty = Value.getValueType().getTypeForEVT(*DAG.getContext()); 404 Entry.IsSExt = IsSigned; 405 Entry.IsZExt = !IsSigned; 406 Args.push_back(Entry); 407 } 408 409 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), 410 getPointerTy(DAG.getDataLayout())); 411 412 Type *RetTy = (Type *)StructType::get(Ty, Ty); 413 414 SDLoc dl(Op); 415 TargetLowering::CallLoweringInfo CLI(DAG); 416 CLI.setDebugLoc(dl) 417 .setChain(InChain) 418 .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args)) 419 .setInRegister() 420 .setSExtResult(IsSigned) 421 .setZExtResult(!IsSigned); 422 423 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI); 424 return CallInfo.first; 425 } 426 427 SDValue AVRTargetLowering::LowerGlobalAddress(SDValue Op, 428 SelectionDAG &DAG) const { 429 auto DL = DAG.getDataLayout(); 430 431 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 432 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 433 434 // Create the TargetGlobalAddress node, folding in the constant offset. 435 SDValue Result = 436 DAG.getTargetGlobalAddress(GV, SDLoc(Op), getPointerTy(DL), Offset); 437 return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result); 438 } 439 440 SDValue AVRTargetLowering::LowerBlockAddress(SDValue Op, 441 SelectionDAG &DAG) const { 442 auto DL = DAG.getDataLayout(); 443 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 444 445 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(DL)); 446 447 return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result); 448 } 449 450 /// IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC. 451 static AVRCC::CondCodes intCCToAVRCC(ISD::CondCode CC) { 452 switch (CC) { 453 default: 454 llvm_unreachable("Unknown condition code!"); 455 case ISD::SETEQ: 456 return AVRCC::COND_EQ; 457 case ISD::SETNE: 458 return AVRCC::COND_NE; 459 case ISD::SETGE: 460 return AVRCC::COND_GE; 461 case ISD::SETLT: 462 return AVRCC::COND_LT; 463 case ISD::SETUGE: 464 return AVRCC::COND_SH; 465 case ISD::SETULT: 466 return AVRCC::COND_LO; 467 } 468 } 469 470 /// Returns appropriate CP/CPI/CPC nodes code for the given 8/16-bit operands. 471 SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, 472 SelectionDAG &DAG, SDLoc DL) const { 473 assert((LHS.getSimpleValueType() == RHS.getSimpleValueType()) && 474 "LHS and RHS have different types"); 475 assert(((LHS.getSimpleValueType() == MVT::i16) || 476 (LHS.getSimpleValueType() == MVT::i8)) && "invalid comparison type"); 477 478 SDValue Cmp; 479 480 if (LHS.getSimpleValueType() == MVT::i16 && dyn_cast<ConstantSDNode>(RHS)) { 481 // Generate a CPI/CPC pair if RHS is a 16-bit constant. 482 SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS, 483 DAG.getIntPtrConstant(0, DL)); 484 SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS, 485 DAG.getIntPtrConstant(1, DL)); 486 SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS, 487 DAG.getIntPtrConstant(0, DL)); 488 SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS, 489 DAG.getIntPtrConstant(1, DL)); 490 Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHSlo, RHSlo); 491 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp); 492 } else { 493 // Generate ordinary 16-bit comparison. 494 Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS, RHS); 495 } 496 497 return Cmp; 498 } 499 500 /// Returns appropriate AVR CMP/CMPC nodes and corresponding condition code for 501 /// the given operands. 502 SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 503 SDValue &AVRcc, SelectionDAG &DAG, 504 SDLoc DL) const { 505 SDValue Cmp; 506 EVT VT = LHS.getValueType(); 507 bool UseTest = false; 508 509 switch (CC) { 510 default: 511 break; 512 case ISD::SETLE: { 513 // Swap operands and reverse the branching condition. 514 std::swap(LHS, RHS); 515 CC = ISD::SETGE; 516 break; 517 } 518 case ISD::SETGT: { 519 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) { 520 switch (C->getSExtValue()) { 521 case -1: { 522 // When doing lhs > -1 use a tst instruction on the top part of lhs 523 // and use brpl instead of using a chain of cp/cpc. 524 UseTest = true; 525 AVRcc = DAG.getConstant(AVRCC::COND_PL, DL, MVT::i8); 526 break; 527 } 528 case 0: { 529 // Turn lhs > 0 into 0 < lhs since 0 can be materialized with 530 // __zero_reg__ in lhs. 531 RHS = LHS; 532 LHS = DAG.getConstant(0, DL, VT); 533 CC = ISD::SETLT; 534 break; 535 } 536 default: { 537 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows 538 // us to fold the constant into the cmp instruction. 539 RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT); 540 CC = ISD::SETGE; 541 break; 542 } 543 } 544 break; 545 } 546 // Swap operands and reverse the branching condition. 547 std::swap(LHS, RHS); 548 CC = ISD::SETLT; 549 break; 550 } 551 case ISD::SETLT: { 552 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) { 553 switch (C->getSExtValue()) { 554 case 1: { 555 // Turn lhs < 1 into 0 >= lhs since 0 can be materialized with 556 // __zero_reg__ in lhs. 557 RHS = LHS; 558 LHS = DAG.getConstant(0, DL, VT); 559 CC = ISD::SETGE; 560 break; 561 } 562 case 0: { 563 // When doing lhs < 0 use a tst instruction on the top part of lhs 564 // and use brmi instead of using a chain of cp/cpc. 565 UseTest = true; 566 AVRcc = DAG.getConstant(AVRCC::COND_MI, DL, MVT::i8); 567 break; 568 } 569 } 570 } 571 break; 572 } 573 case ISD::SETULE: { 574 // Swap operands and reverse the branching condition. 575 std::swap(LHS, RHS); 576 CC = ISD::SETUGE; 577 break; 578 } 579 case ISD::SETUGT: { 580 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to 581 // fold the constant into the cmp instruction. 582 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) { 583 RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT); 584 CC = ISD::SETUGE; 585 break; 586 } 587 // Swap operands and reverse the branching condition. 588 std::swap(LHS, RHS); 589 CC = ISD::SETULT; 590 break; 591 } 592 } 593 594 // Expand 32 and 64 bit comparisons with custom CMP and CMPC nodes instead of 595 // using the default and/or/xor expansion code which is much longer. 596 if (VT == MVT::i32) { 597 SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS, 598 DAG.getIntPtrConstant(0, DL)); 599 SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS, 600 DAG.getIntPtrConstant(1, DL)); 601 SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS, 602 DAG.getIntPtrConstant(0, DL)); 603 SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS, 604 DAG.getIntPtrConstant(1, DL)); 605 606 if (UseTest) { 607 // When using tst we only care about the highest part. 608 SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHShi, 609 DAG.getIntPtrConstant(1, DL)); 610 Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top); 611 } else { 612 Cmp = getAVRCmp(LHSlo, RHSlo, DAG, DL); 613 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp); 614 } 615 } else if (VT == MVT::i64) { 616 SDValue LHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS, 617 DAG.getIntPtrConstant(0, DL)); 618 SDValue LHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS, 619 DAG.getIntPtrConstant(1, DL)); 620 621 SDValue LHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0, 622 DAG.getIntPtrConstant(0, DL)); 623 SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0, 624 DAG.getIntPtrConstant(1, DL)); 625 SDValue LHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1, 626 DAG.getIntPtrConstant(0, DL)); 627 SDValue LHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1, 628 DAG.getIntPtrConstant(1, DL)); 629 630 SDValue RHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS, 631 DAG.getIntPtrConstant(0, DL)); 632 SDValue RHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS, 633 DAG.getIntPtrConstant(1, DL)); 634 635 SDValue RHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0, 636 DAG.getIntPtrConstant(0, DL)); 637 SDValue RHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0, 638 DAG.getIntPtrConstant(1, DL)); 639 SDValue RHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1, 640 DAG.getIntPtrConstant(0, DL)); 641 SDValue RHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1, 642 DAG.getIntPtrConstant(1, DL)); 643 644 if (UseTest) { 645 // When using tst we only care about the highest part. 646 SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS3, 647 DAG.getIntPtrConstant(1, DL)); 648 Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top); 649 } else { 650 Cmp = getAVRCmp(LHS0, RHS0, DAG, DL); 651 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp); 652 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS2, RHS2, Cmp); 653 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS3, RHS3, Cmp); 654 } 655 } else if (VT == MVT::i8 || VT == MVT::i16) { 656 if (UseTest) { 657 // When using tst we only care about the highest part. 658 Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, 659 (VT == MVT::i8) 660 ? LHS 661 : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, 662 LHS, DAG.getIntPtrConstant(1, DL))); 663 } else { 664 Cmp = getAVRCmp(LHS, RHS, DAG, DL); 665 } 666 } else { 667 llvm_unreachable("Invalid comparison size"); 668 } 669 670 // When using a test instruction AVRcc is already set. 671 if (!UseTest) { 672 AVRcc = DAG.getConstant(intCCToAVRCC(CC), DL, MVT::i8); 673 } 674 675 return Cmp; 676 } 677 678 SDValue AVRTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 679 SDValue Chain = Op.getOperand(0); 680 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 681 SDValue LHS = Op.getOperand(2); 682 SDValue RHS = Op.getOperand(3); 683 SDValue Dest = Op.getOperand(4); 684 SDLoc dl(Op); 685 686 SDValue TargetCC; 687 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl); 688 689 return DAG.getNode(AVRISD::BRCOND, dl, MVT::Other, Chain, Dest, TargetCC, 690 Cmp); 691 } 692 693 SDValue AVRTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 694 SDValue LHS = Op.getOperand(0); 695 SDValue RHS = Op.getOperand(1); 696 SDValue TrueV = Op.getOperand(2); 697 SDValue FalseV = Op.getOperand(3); 698 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 699 SDLoc dl(Op); 700 701 SDValue TargetCC; 702 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl); 703 704 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 705 SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp}; 706 707 return DAG.getNode(AVRISD::SELECT_CC, dl, VTs, Ops); 708 } 709 710 SDValue AVRTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 711 SDValue LHS = Op.getOperand(0); 712 SDValue RHS = Op.getOperand(1); 713 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 714 SDLoc DL(Op); 715 716 SDValue TargetCC; 717 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, DL); 718 719 SDValue TrueV = DAG.getConstant(1, DL, Op.getValueType()); 720 SDValue FalseV = DAG.getConstant(0, DL, Op.getValueType()); 721 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 722 SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp}; 723 724 return DAG.getNode(AVRISD::SELECT_CC, DL, VTs, Ops); 725 } 726 727 SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 728 const MachineFunction &MF = DAG.getMachineFunction(); 729 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>(); 730 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 731 auto DL = DAG.getDataLayout(); 732 SDLoc dl(Op); 733 734 // Vastart just stores the address of the VarArgsFrameIndex slot into the 735 // memory location argument. 736 SDValue FI = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), getPointerTy(DL)); 737 738 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), 739 MachinePointerInfo(SV)); 740 } 741 742 SDValue AVRTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 743 switch (Op.getOpcode()) { 744 default: 745 llvm_unreachable("Don't know how to custom lower this!"); 746 case ISD::SHL: 747 case ISD::SRA: 748 case ISD::SRL: 749 case ISD::ROTL: 750 case ISD::ROTR: 751 return LowerShifts(Op, DAG); 752 case ISD::GlobalAddress: 753 return LowerGlobalAddress(Op, DAG); 754 case ISD::BlockAddress: 755 return LowerBlockAddress(Op, DAG); 756 case ISD::BR_CC: 757 return LowerBR_CC(Op, DAG); 758 case ISD::SELECT_CC: 759 return LowerSELECT_CC(Op, DAG); 760 case ISD::SETCC: 761 return LowerSETCC(Op, DAG); 762 case ISD::VASTART: 763 return LowerVASTART(Op, DAG); 764 case ISD::SDIVREM: 765 case ISD::UDIVREM: 766 return LowerDivRem(Op, DAG); 767 } 768 769 return SDValue(); 770 } 771 772 /// Replace a node with an illegal result type 773 /// with a new node built out of custom code. 774 void AVRTargetLowering::ReplaceNodeResults(SDNode *N, 775 SmallVectorImpl<SDValue> &Results, 776 SelectionDAG &DAG) const { 777 SDLoc DL(N); 778 779 switch (N->getOpcode()) { 780 case ISD::ADD: { 781 // Convert add (x, imm) into sub (x, -imm). 782 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) { 783 SDValue Sub = DAG.getNode( 784 ISD::SUB, DL, N->getValueType(0), N->getOperand(0), 785 DAG.getConstant(-C->getAPIntValue(), DL, C->getValueType(0))); 786 Results.push_back(Sub); 787 } 788 break; 789 } 790 default: { 791 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 792 793 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 794 Results.push_back(Res.getValue(I)); 795 796 break; 797 } 798 } 799 } 800 801 /// Return true if the addressing mode represented 802 /// by AM is legal for this target, for a load/store of the specified type. 803 bool AVRTargetLowering::isLegalAddressingMode(const DataLayout &DL, 804 const AddrMode &AM, Type *Ty, 805 unsigned AS, Instruction *I) const { 806 int64_t Offs = AM.BaseOffs; 807 808 // Allow absolute addresses. 809 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) { 810 return true; 811 } 812 813 // Flash memory instructions only allow zero offsets. 814 if (isa<PointerType>(Ty) && AS == AVR::ProgramMemory) { 815 return false; 816 } 817 818 // Allow reg+<6bit> offset. 819 if (Offs < 0) 820 Offs = -Offs; 821 if (AM.BaseGV == 0 && AM.HasBaseReg && AM.Scale == 0 && isUInt<6>(Offs)) { 822 return true; 823 } 824 825 return false; 826 } 827 828 /// Returns true by value, base pointer and 829 /// offset pointer and addressing mode by reference if the node's address 830 /// can be legally represented as pre-indexed load / store address. 831 bool AVRTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 832 SDValue &Offset, 833 ISD::MemIndexedMode &AM, 834 SelectionDAG &DAG) const { 835 EVT VT; 836 const SDNode *Op; 837 SDLoc DL(N); 838 839 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 840 VT = LD->getMemoryVT(); 841 Op = LD->getBasePtr().getNode(); 842 if (LD->getExtensionType() != ISD::NON_EXTLOAD) 843 return false; 844 if (AVR::isProgramMemoryAccess(LD)) { 845 return false; 846 } 847 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 848 VT = ST->getMemoryVT(); 849 Op = ST->getBasePtr().getNode(); 850 if (AVR::isProgramMemoryAccess(ST)) { 851 return false; 852 } 853 } else { 854 return false; 855 } 856 857 if (VT != MVT::i8 && VT != MVT::i16) { 858 return false; 859 } 860 861 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) { 862 return false; 863 } 864 865 if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) { 866 int RHSC = RHS->getSExtValue(); 867 if (Op->getOpcode() == ISD::SUB) 868 RHSC = -RHSC; 869 870 if ((VT == MVT::i16 && RHSC != -2) || (VT == MVT::i8 && RHSC != -1)) { 871 return false; 872 } 873 874 Base = Op->getOperand(0); 875 Offset = DAG.getConstant(RHSC, DL, MVT::i8); 876 AM = ISD::PRE_DEC; 877 878 return true; 879 } 880 881 return false; 882 } 883 884 /// Returns true by value, base pointer and 885 /// offset pointer and addressing mode by reference if this node can be 886 /// combined with a load / store to form a post-indexed load / store. 887 bool AVRTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 888 SDValue &Base, 889 SDValue &Offset, 890 ISD::MemIndexedMode &AM, 891 SelectionDAG &DAG) const { 892 EVT VT; 893 SDLoc DL(N); 894 895 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 896 VT = LD->getMemoryVT(); 897 if (LD->getExtensionType() != ISD::NON_EXTLOAD) 898 return false; 899 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 900 VT = ST->getMemoryVT(); 901 if (AVR::isProgramMemoryAccess(ST)) { 902 return false; 903 } 904 } else { 905 return false; 906 } 907 908 if (VT != MVT::i8 && VT != MVT::i16) { 909 return false; 910 } 911 912 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) { 913 return false; 914 } 915 916 if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) { 917 int RHSC = RHS->getSExtValue(); 918 if (Op->getOpcode() == ISD::SUB) 919 RHSC = -RHSC; 920 if ((VT == MVT::i16 && RHSC != 2) || (VT == MVT::i8 && RHSC != 1)) { 921 return false; 922 } 923 924 Base = Op->getOperand(0); 925 Offset = DAG.getConstant(RHSC, DL, MVT::i8); 926 AM = ISD::POST_INC; 927 928 return true; 929 } 930 931 return false; 932 } 933 934 bool AVRTargetLowering::isOffsetFoldingLegal( 935 const GlobalAddressSDNode *GA) const { 936 return true; 937 } 938 939 //===----------------------------------------------------------------------===// 940 // Formal Arguments Calling Convention Implementation 941 //===----------------------------------------------------------------------===// 942 943 #include "AVRGenCallingConv.inc" 944 945 /// Registers for calling conventions, ordered in reverse as required by ABI. 946 /// Both arrays must be of the same length. 947 static const MCPhysReg RegList8[] = { 948 AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20, 949 AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14, 950 AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8}; 951 static const MCPhysReg RegList16[] = { 952 AVR::R26R25, AVR::R25R24, AVR::R24R23, AVR::R23R22, 953 AVR::R22R21, AVR::R21R20, AVR::R20R19, AVR::R19R18, 954 AVR::R18R17, AVR::R17R16, AVR::R16R15, AVR::R15R14, 955 AVR::R14R13, AVR::R13R12, AVR::R12R11, AVR::R11R10, 956 AVR::R10R9, AVR::R9R8}; 957 958 static_assert(array_lengthof(RegList8) == array_lengthof(RegList16), 959 "8-bit and 16-bit register arrays must be of equal length"); 960 961 /// Analyze incoming and outgoing function arguments. We need custom C++ code 962 /// to handle special constraints in the ABI. 963 /// In addition, all pieces of a certain argument have to be passed either 964 /// using registers or the stack but never mixing both. 965 template <typename ArgT> 966 static void 967 analyzeArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F, 968 const DataLayout *TD, const SmallVectorImpl<ArgT> &Args, 969 SmallVectorImpl<CCValAssign> &ArgLocs, CCState &CCInfo) { 970 unsigned NumArgs = Args.size(); 971 // This is the index of the last used register, in RegList*. 972 // -1 means R26 (R26 is never actually used in CC). 973 int RegLastIdx = -1; 974 // Once a value is passed to the stack it will always be used 975 bool UseStack = false; 976 for (unsigned i = 0; i != NumArgs;) { 977 MVT VT = Args[i].VT; 978 // We have to count the number of bytes for each function argument, that is 979 // those Args with the same OrigArgIndex. This is important in case the 980 // function takes an aggregate type. 981 // Current argument will be between [i..j). 982 unsigned ArgIndex = Args[i].OrigArgIndex; 983 unsigned TotalBytes = VT.getStoreSize(); 984 unsigned j = i + 1; 985 for (; j != NumArgs; ++j) { 986 if (Args[j].OrigArgIndex != ArgIndex) 987 break; 988 TotalBytes += Args[j].VT.getStoreSize(); 989 } 990 // Round up to even number of bytes. 991 TotalBytes = alignTo(TotalBytes, 2); 992 // Skip zero sized arguments 993 if (TotalBytes == 0) 994 continue; 995 // The index of the first register to be used 996 unsigned RegIdx = RegLastIdx + TotalBytes; 997 RegLastIdx = RegIdx; 998 // If there are not enough registers, use the stack 999 if (RegIdx >= array_lengthof(RegList8)) { 1000 UseStack = true; 1001 } 1002 for (; i != j; ++i) { 1003 MVT VT = Args[i].VT; 1004 1005 if (UseStack) { 1006 auto evt = EVT(VT).getTypeForEVT(CCInfo.getContext()); 1007 unsigned Offset = CCInfo.AllocateStack(TD->getTypeAllocSize(evt), 1008 TD->getABITypeAlign(evt)); 1009 CCInfo.addLoc( 1010 CCValAssign::getMem(i, VT, Offset, VT, CCValAssign::Full)); 1011 } else { 1012 unsigned Reg; 1013 if (VT == MVT::i8) { 1014 Reg = CCInfo.AllocateReg(RegList8[RegIdx]); 1015 } else if (VT == MVT::i16) { 1016 Reg = CCInfo.AllocateReg(RegList16[RegIdx]); 1017 } else { 1018 llvm_unreachable( 1019 "calling convention can only manage i8 and i16 types"); 1020 } 1021 assert(Reg && "register not available in calling convention"); 1022 CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full)); 1023 // Registers inside a particular argument are sorted in increasing order 1024 // (remember the array is reversed). 1025 RegIdx -= VT.getStoreSize(); 1026 } 1027 } 1028 } 1029 } 1030 1031 /// Count the total number of bytes needed to pass or return these arguments. 1032 template <typename ArgT> 1033 static unsigned getTotalArgumentsSizeInBytes(const SmallVectorImpl<ArgT> &Args) { 1034 unsigned TotalBytes = 0; 1035 1036 for (const ArgT& Arg : Args) { 1037 TotalBytes += Arg.VT.getStoreSize(); 1038 } 1039 return TotalBytes; 1040 } 1041 1042 /// Analyze incoming and outgoing value of returning from a function. 1043 /// The algorithm is similar to analyzeArguments, but there can only be 1044 /// one value, possibly an aggregate, and it is limited to 8 bytes. 1045 template <typename ArgT> 1046 static void analyzeReturnValues(const SmallVectorImpl<ArgT> &Args, 1047 CCState &CCInfo) { 1048 unsigned NumArgs = Args.size(); 1049 unsigned TotalBytes = getTotalArgumentsSizeInBytes(Args); 1050 // CanLowerReturn() guarantees this assertion. 1051 assert(TotalBytes <= 8 && "return values greater than 8 bytes cannot be lowered"); 1052 1053 // GCC-ABI says that the size is rounded up to the next even number, 1054 // but actually once it is more than 4 it will always round up to 8. 1055 if (TotalBytes > 4) { 1056 TotalBytes = 8; 1057 } else { 1058 TotalBytes = alignTo(TotalBytes, 2); 1059 } 1060 1061 // The index of the first register to use. 1062 int RegIdx = TotalBytes - 1; 1063 for (unsigned i = 0; i != NumArgs; ++i) { 1064 MVT VT = Args[i].VT; 1065 unsigned Reg; 1066 if (VT == MVT::i8) { 1067 Reg = CCInfo.AllocateReg(RegList8[RegIdx]); 1068 } else if (VT == MVT::i16) { 1069 Reg = CCInfo.AllocateReg(RegList16[RegIdx]); 1070 } else { 1071 llvm_unreachable("calling convention can only manage i8 and i16 types"); 1072 } 1073 assert(Reg && "register not available in calling convention"); 1074 CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full)); 1075 // Registers sort in increasing order 1076 RegIdx -= VT.getStoreSize(); 1077 } 1078 } 1079 1080 SDValue AVRTargetLowering::LowerFormalArguments( 1081 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1082 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 1083 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 1084 MachineFunction &MF = DAG.getMachineFunction(); 1085 MachineFrameInfo &MFI = MF.getFrameInfo(); 1086 auto DL = DAG.getDataLayout(); 1087 1088 // Assign locations to all of the incoming arguments. 1089 SmallVector<CCValAssign, 16> ArgLocs; 1090 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 1091 *DAG.getContext()); 1092 1093 // Variadic functions do not need all the analysis below. 1094 if (isVarArg) { 1095 CCInfo.AnalyzeFormalArguments(Ins, ArgCC_AVR_Vararg); 1096 } else { 1097 analyzeArguments(nullptr, &MF.getFunction(), &DL, Ins, ArgLocs, CCInfo); 1098 } 1099 1100 SDValue ArgValue; 1101 for (CCValAssign &VA : ArgLocs) { 1102 1103 // Arguments stored on registers. 1104 if (VA.isRegLoc()) { 1105 EVT RegVT = VA.getLocVT(); 1106 const TargetRegisterClass *RC; 1107 if (RegVT == MVT::i8) { 1108 RC = &AVR::GPR8RegClass; 1109 } else if (RegVT == MVT::i16) { 1110 RC = &AVR::DREGSRegClass; 1111 } else { 1112 llvm_unreachable("Unknown argument type!"); 1113 } 1114 1115 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1116 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1117 1118 // :NOTE: Clang should not promote any i8 into i16 but for safety the 1119 // following code will handle zexts or sexts generated by other 1120 // front ends. Otherwise: 1121 // If this is an 8 bit value, it is really passed promoted 1122 // to 16 bits. Insert an assert[sz]ext to capture this, then 1123 // truncate to the right size. 1124 switch (VA.getLocInfo()) { 1125 default: 1126 llvm_unreachable("Unknown loc info!"); 1127 case CCValAssign::Full: 1128 break; 1129 case CCValAssign::BCvt: 1130 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 1131 break; 1132 case CCValAssign::SExt: 1133 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1134 DAG.getValueType(VA.getValVT())); 1135 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1136 break; 1137 case CCValAssign::ZExt: 1138 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1139 DAG.getValueType(VA.getValVT())); 1140 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1141 break; 1142 } 1143 1144 InVals.push_back(ArgValue); 1145 } else { 1146 // Sanity check. 1147 assert(VA.isMemLoc()); 1148 1149 EVT LocVT = VA.getLocVT(); 1150 1151 // Create the frame index object for this incoming parameter. 1152 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8, 1153 VA.getLocMemOffset(), true); 1154 1155 // Create the SelectionDAG nodes corresponding to a load 1156 // from this parameter. 1157 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DL)); 1158 InVals.push_back(DAG.getLoad(LocVT, dl, Chain, FIN, 1159 MachinePointerInfo::getFixedStack(MF, FI))); 1160 } 1161 } 1162 1163 // If the function takes variable number of arguments, make a frame index for 1164 // the start of the first vararg value... for expansion of llvm.va_start. 1165 if (isVarArg) { 1166 unsigned StackSize = CCInfo.getNextStackOffset(); 1167 AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>(); 1168 1169 AFI->setVarArgsFrameIndex(MFI.CreateFixedObject(2, StackSize, true)); 1170 } 1171 1172 return Chain; 1173 } 1174 1175 //===----------------------------------------------------------------------===// 1176 // Call Calling Convention Implementation 1177 //===----------------------------------------------------------------------===// 1178 1179 SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 1180 SmallVectorImpl<SDValue> &InVals) const { 1181 SelectionDAG &DAG = CLI.DAG; 1182 SDLoc &DL = CLI.DL; 1183 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 1184 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 1185 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 1186 SDValue Chain = CLI.Chain; 1187 SDValue Callee = CLI.Callee; 1188 bool &isTailCall = CLI.IsTailCall; 1189 CallingConv::ID CallConv = CLI.CallConv; 1190 bool isVarArg = CLI.IsVarArg; 1191 1192 MachineFunction &MF = DAG.getMachineFunction(); 1193 1194 // AVR does not yet support tail call optimization. 1195 isTailCall = false; 1196 1197 // Analyze operands of the call, assigning locations to each operand. 1198 SmallVector<CCValAssign, 16> ArgLocs; 1199 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 1200 *DAG.getContext()); 1201 1202 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 1203 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 1204 // node so that legalize doesn't hack it. 1205 const Function *F = nullptr; 1206 if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1207 const GlobalValue *GV = G->getGlobal(); 1208 1209 F = cast<Function>(GV); 1210 Callee = 1211 DAG.getTargetGlobalAddress(GV, DL, getPointerTy(DAG.getDataLayout())); 1212 } else if (const ExternalSymbolSDNode *ES = 1213 dyn_cast<ExternalSymbolSDNode>(Callee)) { 1214 Callee = DAG.getTargetExternalSymbol(ES->getSymbol(), 1215 getPointerTy(DAG.getDataLayout())); 1216 } 1217 1218 // Variadic functions do not need all the analysis below. 1219 if (isVarArg) { 1220 CCInfo.AnalyzeCallOperands(Outs, ArgCC_AVR_Vararg); 1221 } else { 1222 analyzeArguments(&CLI, F, &DAG.getDataLayout(), Outs, ArgLocs, CCInfo); 1223 } 1224 1225 // Get a count of how many bytes are to be pushed on the stack. 1226 unsigned NumBytes = CCInfo.getNextStackOffset(); 1227 1228 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL); 1229 1230 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 1231 1232 // First, walk the register assignments, inserting copies. 1233 unsigned AI, AE; 1234 bool HasStackArgs = false; 1235 for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) { 1236 CCValAssign &VA = ArgLocs[AI]; 1237 EVT RegVT = VA.getLocVT(); 1238 SDValue Arg = OutVals[AI]; 1239 1240 // Promote the value if needed. With Clang this should not happen. 1241 switch (VA.getLocInfo()) { 1242 default: 1243 llvm_unreachable("Unknown loc info!"); 1244 case CCValAssign::Full: 1245 break; 1246 case CCValAssign::SExt: 1247 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); 1248 break; 1249 case CCValAssign::ZExt: 1250 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); 1251 break; 1252 case CCValAssign::AExt: 1253 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); 1254 break; 1255 case CCValAssign::BCvt: 1256 Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg); 1257 break; 1258 } 1259 1260 // Stop when we encounter a stack argument, we need to process them 1261 // in reverse order in the loop below. 1262 if (VA.isMemLoc()) { 1263 HasStackArgs = true; 1264 break; 1265 } 1266 1267 // Arguments that can be passed on registers must be kept in the RegsToPass 1268 // vector. 1269 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1270 } 1271 1272 // Second, stack arguments have to walked in reverse order by inserting 1273 // chained stores, this ensures their order is not changed by the scheduler 1274 // and that the push instruction sequence generated is correct, otherwise they 1275 // can be freely intermixed. 1276 if (HasStackArgs) { 1277 for (AE = AI, AI = ArgLocs.size(); AI != AE; --AI) { 1278 unsigned Loc = AI - 1; 1279 CCValAssign &VA = ArgLocs[Loc]; 1280 SDValue Arg = OutVals[Loc]; 1281 1282 assert(VA.isMemLoc()); 1283 1284 // SP points to one stack slot further so add one to adjust it. 1285 SDValue PtrOff = DAG.getNode( 1286 ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), 1287 DAG.getRegister(AVR::SP, getPointerTy(DAG.getDataLayout())), 1288 DAG.getIntPtrConstant(VA.getLocMemOffset() + 1, DL)); 1289 1290 Chain = 1291 DAG.getStore(Chain, DL, Arg, PtrOff, 1292 MachinePointerInfo::getStack(MF, VA.getLocMemOffset())); 1293 } 1294 } 1295 1296 // Build a sequence of copy-to-reg nodes chained together with token chain and 1297 // flag operands which copy the outgoing args into registers. The InFlag in 1298 // necessary since all emited instructions must be stuck together. 1299 SDValue InFlag; 1300 for (auto Reg : RegsToPass) { 1301 Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, InFlag); 1302 InFlag = Chain.getValue(1); 1303 } 1304 1305 // Returns a chain & a flag for retval copy to use. 1306 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 1307 SmallVector<SDValue, 8> Ops; 1308 Ops.push_back(Chain); 1309 Ops.push_back(Callee); 1310 1311 // Add argument registers to the end of the list so that they are known live 1312 // into the call. 1313 for (auto Reg : RegsToPass) { 1314 Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType())); 1315 } 1316 1317 // Add a register mask operand representing the call-preserved registers. 1318 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 1319 const uint32_t *Mask = 1320 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv); 1321 assert(Mask && "Missing call preserved mask for calling convention"); 1322 Ops.push_back(DAG.getRegisterMask(Mask)); 1323 1324 if (InFlag.getNode()) { 1325 Ops.push_back(InFlag); 1326 } 1327 1328 Chain = DAG.getNode(AVRISD::CALL, DL, NodeTys, Ops); 1329 InFlag = Chain.getValue(1); 1330 1331 // Create the CALLSEQ_END node. 1332 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true), 1333 DAG.getIntPtrConstant(0, DL, true), InFlag, DL); 1334 1335 if (!Ins.empty()) { 1336 InFlag = Chain.getValue(1); 1337 } 1338 1339 // Handle result values, copying them out of physregs into vregs that we 1340 // return. 1341 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, DL, DAG, 1342 InVals); 1343 } 1344 1345 /// Lower the result values of a call into the 1346 /// appropriate copies out of appropriate physical registers. 1347 /// 1348 SDValue AVRTargetLowering::LowerCallResult( 1349 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, 1350 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, 1351 SmallVectorImpl<SDValue> &InVals) const { 1352 1353 // Assign locations to each value returned by this call. 1354 SmallVector<CCValAssign, 16> RVLocs; 1355 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 1356 *DAG.getContext()); 1357 1358 // Handle runtime calling convs. 1359 if (CallConv == CallingConv::AVR_BUILTIN) { 1360 CCInfo.AnalyzeCallResult(Ins, RetCC_AVR_BUILTIN); 1361 } else { 1362 analyzeReturnValues(Ins, CCInfo); 1363 } 1364 1365 // Copy all of the result registers out of their specified physreg. 1366 for (CCValAssign const &RVLoc : RVLocs) { 1367 Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(), 1368 InFlag) 1369 .getValue(1); 1370 InFlag = Chain.getValue(2); 1371 InVals.push_back(Chain.getValue(0)); 1372 } 1373 1374 return Chain; 1375 } 1376 1377 //===----------------------------------------------------------------------===// 1378 // Return Value Calling Convention Implementation 1379 //===----------------------------------------------------------------------===// 1380 1381 bool AVRTargetLowering::CanLowerReturn( 1382 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, 1383 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const { 1384 if (CallConv == CallingConv::AVR_BUILTIN) { 1385 SmallVector<CCValAssign, 16> RVLocs; 1386 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); 1387 return CCInfo.CheckReturn(Outs, RetCC_AVR_BUILTIN); 1388 } 1389 1390 unsigned TotalBytes = getTotalArgumentsSizeInBytes(Outs); 1391 return TotalBytes <= 8; 1392 } 1393 1394 SDValue 1395 AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 1396 bool isVarArg, 1397 const SmallVectorImpl<ISD::OutputArg> &Outs, 1398 const SmallVectorImpl<SDValue> &OutVals, 1399 const SDLoc &dl, SelectionDAG &DAG) const { 1400 // CCValAssign - represent the assignment of the return value to locations. 1401 SmallVector<CCValAssign, 16> RVLocs; 1402 1403 // CCState - Info about the registers and stack slot. 1404 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 1405 *DAG.getContext()); 1406 1407 MachineFunction &MF = DAG.getMachineFunction(); 1408 1409 // Analyze return values. 1410 if (CallConv == CallingConv::AVR_BUILTIN) { 1411 CCInfo.AnalyzeReturn(Outs, RetCC_AVR_BUILTIN); 1412 } else { 1413 analyzeReturnValues(Outs, CCInfo); 1414 } 1415 1416 SDValue Flag; 1417 SmallVector<SDValue, 4> RetOps(1, Chain); 1418 // Copy the result values into the output registers. 1419 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 1420 CCValAssign &VA = RVLocs[i]; 1421 assert(VA.isRegLoc() && "Can only return in registers!"); 1422 1423 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); 1424 1425 // Guarantee that all emitted copies are stuck together with flags. 1426 Flag = Chain.getValue(1); 1427 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 1428 } 1429 1430 // Don't emit the ret/reti instruction when the naked attribute is present in 1431 // the function being compiled. 1432 if (MF.getFunction().getAttributes().hasAttribute( 1433 AttributeList::FunctionIndex, Attribute::Naked)) { 1434 return Chain; 1435 } 1436 1437 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>(); 1438 1439 unsigned RetOpc = 1440 AFI->isInterruptOrSignalHandler() 1441 ? AVRISD::RETI_FLAG 1442 : AVRISD::RET_FLAG; 1443 1444 RetOps[0] = Chain; // Update chain. 1445 1446 if (Flag.getNode()) { 1447 RetOps.push_back(Flag); 1448 } 1449 1450 return DAG.getNode(RetOpc, dl, MVT::Other, RetOps); 1451 } 1452 1453 //===----------------------------------------------------------------------===// 1454 // Custom Inserters 1455 //===----------------------------------------------------------------------===// 1456 1457 MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI, 1458 MachineBasicBlock *BB) const { 1459 unsigned Opc; 1460 const TargetRegisterClass *RC; 1461 bool HasRepeatedOperand = false; 1462 MachineFunction *F = BB->getParent(); 1463 MachineRegisterInfo &RI = F->getRegInfo(); 1464 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 1465 DebugLoc dl = MI.getDebugLoc(); 1466 1467 switch (MI.getOpcode()) { 1468 default: 1469 llvm_unreachable("Invalid shift opcode!"); 1470 case AVR::Lsl8: 1471 Opc = AVR::ADDRdRr; // LSL is an alias of ADD Rd, Rd 1472 RC = &AVR::GPR8RegClass; 1473 HasRepeatedOperand = true; 1474 break; 1475 case AVR::Lsl16: 1476 Opc = AVR::LSLWRd; 1477 RC = &AVR::DREGSRegClass; 1478 break; 1479 case AVR::Asr8: 1480 Opc = AVR::ASRRd; 1481 RC = &AVR::GPR8RegClass; 1482 break; 1483 case AVR::Asr16: 1484 Opc = AVR::ASRWRd; 1485 RC = &AVR::DREGSRegClass; 1486 break; 1487 case AVR::Lsr8: 1488 Opc = AVR::LSRRd; 1489 RC = &AVR::GPR8RegClass; 1490 break; 1491 case AVR::Lsr16: 1492 Opc = AVR::LSRWRd; 1493 RC = &AVR::DREGSRegClass; 1494 break; 1495 case AVR::Rol8: 1496 Opc = AVR::ROLBRd; 1497 RC = &AVR::GPR8RegClass; 1498 break; 1499 case AVR::Rol16: 1500 Opc = AVR::ROLWRd; 1501 RC = &AVR::DREGSRegClass; 1502 break; 1503 case AVR::Ror8: 1504 Opc = AVR::RORBRd; 1505 RC = &AVR::GPR8RegClass; 1506 break; 1507 case AVR::Ror16: 1508 Opc = AVR::RORWRd; 1509 RC = &AVR::DREGSRegClass; 1510 break; 1511 } 1512 1513 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1514 1515 MachineFunction::iterator I; 1516 for (I = BB->getIterator(); I != F->end() && &(*I) != BB; ++I); 1517 if (I != F->end()) ++I; 1518 1519 // Create loop block. 1520 MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB); 1521 MachineBasicBlock *CheckBB = F->CreateMachineBasicBlock(LLVM_BB); 1522 MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB); 1523 1524 F->insert(I, LoopBB); 1525 F->insert(I, CheckBB); 1526 F->insert(I, RemBB); 1527 1528 // Update machine-CFG edges by transferring all successors of the current 1529 // block to the block containing instructions after shift. 1530 RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)), 1531 BB->end()); 1532 RemBB->transferSuccessorsAndUpdatePHIs(BB); 1533 1534 // Add edges BB => LoopBB => CheckBB => RemBB, CheckBB => LoopBB. 1535 BB->addSuccessor(CheckBB); 1536 LoopBB->addSuccessor(CheckBB); 1537 CheckBB->addSuccessor(LoopBB); 1538 CheckBB->addSuccessor(RemBB); 1539 1540 Register ShiftAmtReg = RI.createVirtualRegister(&AVR::GPR8RegClass); 1541 Register ShiftAmtReg2 = RI.createVirtualRegister(&AVR::GPR8RegClass); 1542 Register ShiftReg = RI.createVirtualRegister(RC); 1543 Register ShiftReg2 = RI.createVirtualRegister(RC); 1544 Register ShiftAmtSrcReg = MI.getOperand(2).getReg(); 1545 Register SrcReg = MI.getOperand(1).getReg(); 1546 Register DstReg = MI.getOperand(0).getReg(); 1547 1548 // BB: 1549 // rjmp CheckBB 1550 BuildMI(BB, dl, TII.get(AVR::RJMPk)).addMBB(CheckBB); 1551 1552 // LoopBB: 1553 // ShiftReg2 = shift ShiftReg 1554 auto ShiftMI = BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg); 1555 if (HasRepeatedOperand) 1556 ShiftMI.addReg(ShiftReg); 1557 1558 // CheckBB: 1559 // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB] 1560 // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB] 1561 // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB] 1562 // ShiftAmt2 = ShiftAmt - 1; 1563 // if (ShiftAmt2 >= 0) goto LoopBB; 1564 BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftReg) 1565 .addReg(SrcReg) 1566 .addMBB(BB) 1567 .addReg(ShiftReg2) 1568 .addMBB(LoopBB); 1569 BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftAmtReg) 1570 .addReg(ShiftAmtSrcReg) 1571 .addMBB(BB) 1572 .addReg(ShiftAmtReg2) 1573 .addMBB(LoopBB); 1574 BuildMI(CheckBB, dl, TII.get(AVR::PHI), DstReg) 1575 .addReg(SrcReg) 1576 .addMBB(BB) 1577 .addReg(ShiftReg2) 1578 .addMBB(LoopBB); 1579 1580 BuildMI(CheckBB, dl, TII.get(AVR::DECRd), ShiftAmtReg2) 1581 .addReg(ShiftAmtReg); 1582 BuildMI(CheckBB, dl, TII.get(AVR::BRPLk)).addMBB(LoopBB); 1583 1584 MI.eraseFromParent(); // The pseudo instruction is gone now. 1585 return RemBB; 1586 } 1587 1588 static bool isCopyMulResult(MachineBasicBlock::iterator const &I) { 1589 if (I->getOpcode() == AVR::COPY) { 1590 Register SrcReg = I->getOperand(1).getReg(); 1591 return (SrcReg == AVR::R0 || SrcReg == AVR::R1); 1592 } 1593 1594 return false; 1595 } 1596 1597 // The mul instructions wreak havock on our zero_reg R1. We need to clear it 1598 // after the result has been evacuated. This is probably not the best way to do 1599 // it, but it works for now. 1600 MachineBasicBlock *AVRTargetLowering::insertMul(MachineInstr &MI, 1601 MachineBasicBlock *BB) const { 1602 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 1603 MachineBasicBlock::iterator I(MI); 1604 ++I; // in any case insert *after* the mul instruction 1605 if (isCopyMulResult(I)) 1606 ++I; 1607 if (isCopyMulResult(I)) 1608 ++I; 1609 BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::EORRdRr), AVR::R1) 1610 .addReg(AVR::R1) 1611 .addReg(AVR::R1); 1612 return BB; 1613 } 1614 1615 MachineBasicBlock * 1616 AVRTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, 1617 MachineBasicBlock *MBB) const { 1618 int Opc = MI.getOpcode(); 1619 1620 // Pseudo shift instructions with a non constant shift amount are expanded 1621 // into a loop. 1622 switch (Opc) { 1623 case AVR::Lsl8: 1624 case AVR::Lsl16: 1625 case AVR::Lsr8: 1626 case AVR::Lsr16: 1627 case AVR::Rol8: 1628 case AVR::Rol16: 1629 case AVR::Ror8: 1630 case AVR::Ror16: 1631 case AVR::Asr8: 1632 case AVR::Asr16: 1633 return insertShift(MI, MBB); 1634 case AVR::MULRdRr: 1635 case AVR::MULSRdRr: 1636 return insertMul(MI, MBB); 1637 } 1638 1639 assert((Opc == AVR::Select16 || Opc == AVR::Select8) && 1640 "Unexpected instr type to insert"); 1641 1642 const AVRInstrInfo &TII = (const AVRInstrInfo &)*MI.getParent() 1643 ->getParent() 1644 ->getSubtarget() 1645 .getInstrInfo(); 1646 DebugLoc dl = MI.getDebugLoc(); 1647 1648 // To "insert" a SELECT instruction, we insert the diamond 1649 // control-flow pattern. The incoming instruction knows the 1650 // destination vreg to set, the condition code register to branch 1651 // on, the true/false values to select between, and a branch opcode 1652 // to use. 1653 1654 MachineFunction *MF = MBB->getParent(); 1655 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 1656 MachineBasicBlock *FallThrough = MBB->getFallThrough(); 1657 1658 // If the current basic block falls through to another basic block, 1659 // we must insert an unconditional branch to the fallthrough destination 1660 // if we are to insert basic blocks at the prior fallthrough point. 1661 if (FallThrough != nullptr) { 1662 BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(FallThrough); 1663 } 1664 1665 MachineBasicBlock *trueMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1666 MachineBasicBlock *falseMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1667 1668 MachineFunction::iterator I; 1669 for (I = MF->begin(); I != MF->end() && &(*I) != MBB; ++I); 1670 if (I != MF->end()) ++I; 1671 MF->insert(I, trueMBB); 1672 MF->insert(I, falseMBB); 1673 1674 // Transfer remaining instructions and all successors of the current 1675 // block to the block which will contain the Phi node for the 1676 // select. 1677 trueMBB->splice(trueMBB->begin(), MBB, 1678 std::next(MachineBasicBlock::iterator(MI)), MBB->end()); 1679 trueMBB->transferSuccessorsAndUpdatePHIs(MBB); 1680 1681 AVRCC::CondCodes CC = (AVRCC::CondCodes)MI.getOperand(3).getImm(); 1682 BuildMI(MBB, dl, TII.getBrCond(CC)).addMBB(trueMBB); 1683 BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(falseMBB); 1684 MBB->addSuccessor(falseMBB); 1685 MBB->addSuccessor(trueMBB); 1686 1687 // Unconditionally flow back to the true block 1688 BuildMI(falseMBB, dl, TII.get(AVR::RJMPk)).addMBB(trueMBB); 1689 falseMBB->addSuccessor(trueMBB); 1690 1691 // Set up the Phi node to determine where we came from 1692 BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI), MI.getOperand(0).getReg()) 1693 .addReg(MI.getOperand(1).getReg()) 1694 .addMBB(MBB) 1695 .addReg(MI.getOperand(2).getReg()) 1696 .addMBB(falseMBB) ; 1697 1698 MI.eraseFromParent(); // The pseudo instruction is gone now. 1699 return trueMBB; 1700 } 1701 1702 //===----------------------------------------------------------------------===// 1703 // Inline Asm Support 1704 //===----------------------------------------------------------------------===// 1705 1706 AVRTargetLowering::ConstraintType 1707 AVRTargetLowering::getConstraintType(StringRef Constraint) const { 1708 if (Constraint.size() == 1) { 1709 // See http://www.nongnu.org/avr-libc/user-manual/inline_asm.html 1710 switch (Constraint[0]) { 1711 default: 1712 break; 1713 case 'a': // Simple upper registers 1714 case 'b': // Base pointer registers pairs 1715 case 'd': // Upper register 1716 case 'l': // Lower registers 1717 case 'e': // Pointer register pairs 1718 case 'q': // Stack pointer register 1719 case 'r': // Any register 1720 case 'w': // Special upper register pairs 1721 return C_RegisterClass; 1722 case 't': // Temporary register 1723 case 'x': case 'X': // Pointer register pair X 1724 case 'y': case 'Y': // Pointer register pair Y 1725 case 'z': case 'Z': // Pointer register pair Z 1726 return C_Register; 1727 case 'Q': // A memory address based on Y or Z pointer with displacement. 1728 return C_Memory; 1729 case 'G': // Floating point constant 1730 case 'I': // 6-bit positive integer constant 1731 case 'J': // 6-bit negative integer constant 1732 case 'K': // Integer constant (Range: 2) 1733 case 'L': // Integer constant (Range: 0) 1734 case 'M': // 8-bit integer constant 1735 case 'N': // Integer constant (Range: -1) 1736 case 'O': // Integer constant (Range: 8, 16, 24) 1737 case 'P': // Integer constant (Range: 1) 1738 case 'R': // Integer constant (Range: -6 to 5)x 1739 return C_Immediate; 1740 } 1741 } 1742 1743 return TargetLowering::getConstraintType(Constraint); 1744 } 1745 1746 unsigned 1747 AVRTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const { 1748 // Not sure if this is actually the right thing to do, but we got to do 1749 // *something* [agnat] 1750 switch (ConstraintCode[0]) { 1751 case 'Q': 1752 return InlineAsm::Constraint_Q; 1753 } 1754 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 1755 } 1756 1757 AVRTargetLowering::ConstraintWeight 1758 AVRTargetLowering::getSingleConstraintMatchWeight( 1759 AsmOperandInfo &info, const char *constraint) const { 1760 ConstraintWeight weight = CW_Invalid; 1761 Value *CallOperandVal = info.CallOperandVal; 1762 1763 // If we don't have a value, we can't do a match, 1764 // but allow it at the lowest weight. 1765 // (this behaviour has been copied from the ARM backend) 1766 if (!CallOperandVal) { 1767 return CW_Default; 1768 } 1769 1770 // Look at the constraint type. 1771 switch (*constraint) { 1772 default: 1773 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 1774 break; 1775 case 'd': 1776 case 'r': 1777 case 'l': 1778 weight = CW_Register; 1779 break; 1780 case 'a': 1781 case 'b': 1782 case 'e': 1783 case 'q': 1784 case 't': 1785 case 'w': 1786 case 'x': case 'X': 1787 case 'y': case 'Y': 1788 case 'z': case 'Z': 1789 weight = CW_SpecificReg; 1790 break; 1791 case 'G': 1792 if (const ConstantFP *C = dyn_cast<ConstantFP>(CallOperandVal)) { 1793 if (C->isZero()) { 1794 weight = CW_Constant; 1795 } 1796 } 1797 break; 1798 case 'I': 1799 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 1800 if (isUInt<6>(C->getZExtValue())) { 1801 weight = CW_Constant; 1802 } 1803 } 1804 break; 1805 case 'J': 1806 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 1807 if ((C->getSExtValue() >= -63) && (C->getSExtValue() <= 0)) { 1808 weight = CW_Constant; 1809 } 1810 } 1811 break; 1812 case 'K': 1813 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 1814 if (C->getZExtValue() == 2) { 1815 weight = CW_Constant; 1816 } 1817 } 1818 break; 1819 case 'L': 1820 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 1821 if (C->getZExtValue() == 0) { 1822 weight = CW_Constant; 1823 } 1824 } 1825 break; 1826 case 'M': 1827 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 1828 if (isUInt<8>(C->getZExtValue())) { 1829 weight = CW_Constant; 1830 } 1831 } 1832 break; 1833 case 'N': 1834 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 1835 if (C->getSExtValue() == -1) { 1836 weight = CW_Constant; 1837 } 1838 } 1839 break; 1840 case 'O': 1841 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 1842 if ((C->getZExtValue() == 8) || (C->getZExtValue() == 16) || 1843 (C->getZExtValue() == 24)) { 1844 weight = CW_Constant; 1845 } 1846 } 1847 break; 1848 case 'P': 1849 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 1850 if (C->getZExtValue() == 1) { 1851 weight = CW_Constant; 1852 } 1853 } 1854 break; 1855 case 'R': 1856 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 1857 if ((C->getSExtValue() >= -6) && (C->getSExtValue() <= 5)) { 1858 weight = CW_Constant; 1859 } 1860 } 1861 break; 1862 case 'Q': 1863 weight = CW_Memory; 1864 break; 1865 } 1866 1867 return weight; 1868 } 1869 1870 std::pair<unsigned, const TargetRegisterClass *> 1871 AVRTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 1872 StringRef Constraint, 1873 MVT VT) const { 1874 // We only support i8 and i16. 1875 // 1876 //:FIXME: remove this assert for now since it gets sometimes executed 1877 // assert((VT == MVT::i16 || VT == MVT::i8) && "Wrong operand type."); 1878 1879 if (Constraint.size() == 1) { 1880 switch (Constraint[0]) { 1881 case 'a': // Simple upper registers r16..r23. 1882 return std::make_pair(0U, &AVR::LD8loRegClass); 1883 case 'b': // Base pointer registers: y, z. 1884 return std::make_pair(0U, &AVR::PTRDISPREGSRegClass); 1885 case 'd': // Upper registers r16..r31. 1886 return std::make_pair(0U, &AVR::LD8RegClass); 1887 case 'l': // Lower registers r0..r15. 1888 return std::make_pair(0U, &AVR::GPR8loRegClass); 1889 case 'e': // Pointer register pairs: x, y, z. 1890 return std::make_pair(0U, &AVR::PTRREGSRegClass); 1891 case 'q': // Stack pointer register: SPH:SPL. 1892 return std::make_pair(0U, &AVR::GPRSPRegClass); 1893 case 'r': // Any register: r0..r31. 1894 if (VT == MVT::i8) 1895 return std::make_pair(0U, &AVR::GPR8RegClass); 1896 1897 assert(VT == MVT::i16 && "inline asm constraint too large"); 1898 return std::make_pair(0U, &AVR::DREGSRegClass); 1899 case 't': // Temporary register: r0. 1900 return std::make_pair(unsigned(AVR::R0), &AVR::GPR8RegClass); 1901 case 'w': // Special upper register pairs: r24, r26, r28, r30. 1902 return std::make_pair(0U, &AVR::IWREGSRegClass); 1903 case 'x': // Pointer register pair X: r27:r26. 1904 case 'X': 1905 return std::make_pair(unsigned(AVR::R27R26), &AVR::PTRREGSRegClass); 1906 case 'y': // Pointer register pair Y: r29:r28. 1907 case 'Y': 1908 return std::make_pair(unsigned(AVR::R29R28), &AVR::PTRREGSRegClass); 1909 case 'z': // Pointer register pair Z: r31:r30. 1910 case 'Z': 1911 return std::make_pair(unsigned(AVR::R31R30), &AVR::PTRREGSRegClass); 1912 default: 1913 break; 1914 } 1915 } 1916 1917 return TargetLowering::getRegForInlineAsmConstraint( 1918 Subtarget.getRegisterInfo(), Constraint, VT); 1919 } 1920 1921 void AVRTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 1922 std::string &Constraint, 1923 std::vector<SDValue> &Ops, 1924 SelectionDAG &DAG) const { 1925 SDValue Result(0, 0); 1926 SDLoc DL(Op); 1927 EVT Ty = Op.getValueType(); 1928 1929 // Currently only support length 1 constraints. 1930 if (Constraint.length() != 1) { 1931 return; 1932 } 1933 1934 char ConstraintLetter = Constraint[0]; 1935 switch (ConstraintLetter) { 1936 default: 1937 break; 1938 // Deal with integers first: 1939 case 'I': 1940 case 'J': 1941 case 'K': 1942 case 'L': 1943 case 'M': 1944 case 'N': 1945 case 'O': 1946 case 'P': 1947 case 'R': { 1948 const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 1949 if (!C) { 1950 return; 1951 } 1952 1953 int64_t CVal64 = C->getSExtValue(); 1954 uint64_t CUVal64 = C->getZExtValue(); 1955 switch (ConstraintLetter) { 1956 case 'I': // 0..63 1957 if (!isUInt<6>(CUVal64)) 1958 return; 1959 Result = DAG.getTargetConstant(CUVal64, DL, Ty); 1960 break; 1961 case 'J': // -63..0 1962 if (CVal64 < -63 || CVal64 > 0) 1963 return; 1964 Result = DAG.getTargetConstant(CVal64, DL, Ty); 1965 break; 1966 case 'K': // 2 1967 if (CUVal64 != 2) 1968 return; 1969 Result = DAG.getTargetConstant(CUVal64, DL, Ty); 1970 break; 1971 case 'L': // 0 1972 if (CUVal64 != 0) 1973 return; 1974 Result = DAG.getTargetConstant(CUVal64, DL, Ty); 1975 break; 1976 case 'M': // 0..255 1977 if (!isUInt<8>(CUVal64)) 1978 return; 1979 // i8 type may be printed as a negative number, 1980 // e.g. 254 would be printed as -2, 1981 // so we force it to i16 at least. 1982 if (Ty.getSimpleVT() == MVT::i8) { 1983 Ty = MVT::i16; 1984 } 1985 Result = DAG.getTargetConstant(CUVal64, DL, Ty); 1986 break; 1987 case 'N': // -1 1988 if (CVal64 != -1) 1989 return; 1990 Result = DAG.getTargetConstant(CVal64, DL, Ty); 1991 break; 1992 case 'O': // 8, 16, 24 1993 if (CUVal64 != 8 && CUVal64 != 16 && CUVal64 != 24) 1994 return; 1995 Result = DAG.getTargetConstant(CUVal64, DL, Ty); 1996 break; 1997 case 'P': // 1 1998 if (CUVal64 != 1) 1999 return; 2000 Result = DAG.getTargetConstant(CUVal64, DL, Ty); 2001 break; 2002 case 'R': // -6..5 2003 if (CVal64 < -6 || CVal64 > 5) 2004 return; 2005 Result = DAG.getTargetConstant(CVal64, DL, Ty); 2006 break; 2007 } 2008 2009 break; 2010 } 2011 case 'G': 2012 const ConstantFPSDNode *FC = dyn_cast<ConstantFPSDNode>(Op); 2013 if (!FC || !FC->isZero()) 2014 return; 2015 // Soften float to i8 0 2016 Result = DAG.getTargetConstant(0, DL, MVT::i8); 2017 break; 2018 } 2019 2020 if (Result.getNode()) { 2021 Ops.push_back(Result); 2022 return; 2023 } 2024 2025 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 2026 } 2027 2028 Register AVRTargetLowering::getRegisterByName(const char *RegName, LLT VT, 2029 const MachineFunction &MF) const { 2030 Register Reg; 2031 2032 if (VT == LLT::scalar(8)) { 2033 Reg = StringSwitch<unsigned>(RegName) 2034 .Case("r0", AVR::R0).Case("r1", AVR::R1).Case("r2", AVR::R2) 2035 .Case("r3", AVR::R3).Case("r4", AVR::R4).Case("r5", AVR::R5) 2036 .Case("r6", AVR::R6).Case("r7", AVR::R7).Case("r8", AVR::R8) 2037 .Case("r9", AVR::R9).Case("r10", AVR::R10).Case("r11", AVR::R11) 2038 .Case("r12", AVR::R12).Case("r13", AVR::R13).Case("r14", AVR::R14) 2039 .Case("r15", AVR::R15).Case("r16", AVR::R16).Case("r17", AVR::R17) 2040 .Case("r18", AVR::R18).Case("r19", AVR::R19).Case("r20", AVR::R20) 2041 .Case("r21", AVR::R21).Case("r22", AVR::R22).Case("r23", AVR::R23) 2042 .Case("r24", AVR::R24).Case("r25", AVR::R25).Case("r26", AVR::R26) 2043 .Case("r27", AVR::R27).Case("r28", AVR::R28).Case("r29", AVR::R29) 2044 .Case("r30", AVR::R30).Case("r31", AVR::R31) 2045 .Case("X", AVR::R27R26).Case("Y", AVR::R29R28).Case("Z", AVR::R31R30) 2046 .Default(0); 2047 } else { 2048 Reg = StringSwitch<unsigned>(RegName) 2049 .Case("r0", AVR::R1R0).Case("r2", AVR::R3R2) 2050 .Case("r4", AVR::R5R4).Case("r6", AVR::R7R6) 2051 .Case("r8", AVR::R9R8).Case("r10", AVR::R11R10) 2052 .Case("r12", AVR::R13R12).Case("r14", AVR::R15R14) 2053 .Case("r16", AVR::R17R16).Case("r18", AVR::R19R18) 2054 .Case("r20", AVR::R21R20).Case("r22", AVR::R23R22) 2055 .Case("r24", AVR::R25R24).Case("r26", AVR::R27R26) 2056 .Case("r28", AVR::R29R28).Case("r30", AVR::R31R30) 2057 .Case("X", AVR::R27R26).Case("Y", AVR::R29R28).Case("Z", AVR::R31R30) 2058 .Default(0); 2059 } 2060 2061 if (Reg) 2062 return Reg; 2063 2064 report_fatal_error("Invalid register name global variable"); 2065 } 2066 2067 } // end of namespace llvm 2068