1 //===-- AVRISelLowering.h - AVR DAG Lowering Interface ----------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that AVR uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_AVR_ISEL_LOWERING_H 15 #define LLVM_AVR_ISEL_LOWERING_H 16 17 #include "llvm/CodeGen/CallingConvLower.h" 18 #include "llvm/CodeGen/TargetLowering.h" 19 20 namespace llvm { 21 22 namespace AVRISD { 23 24 /// AVR Specific DAG Nodes 25 enum NodeType { 26 /// Start the numbering where the builtin ops leave off. 27 FIRST_NUMBER = ISD::BUILTIN_OP_END, 28 /// Return from subroutine. 29 RET_FLAG, 30 /// Return from ISR. 31 RETI_FLAG, 32 /// Represents an abstract call instruction, 33 /// which includes a bunch of information. 34 CALL, 35 /// A wrapper node for TargetConstantPool, 36 /// TargetExternalSymbol, and TargetGlobalAddress. 37 WRAPPER, 38 LSL, ///< Logical shift left. 39 LSR, ///< Logical shift right. 40 ASR, ///< Arithmetic shift right. 41 ROR, ///< Bit rotate right. 42 ROL, ///< Bit rotate left. 43 LSLLOOP, ///< A loop of single logical shift left instructions. 44 LSRLOOP, ///< A loop of single logical shift right instructions. 45 ROLLOOP, ///< A loop of single left bit rotate instructions. 46 RORLOOP, ///< A loop of single right bit rotate instructions. 47 ASRLOOP, ///< A loop of single arithmetic shift right instructions. 48 /// AVR conditional branches. Operand 0 is the chain operand, operand 1 49 /// is the block to branch if condition is true, operand 2 is the 50 /// condition code, and operand 3 is the flag operand produced by a CMP 51 /// or TEST instruction. 52 BRCOND, 53 /// Compare instruction. 54 CMP, 55 /// Compare with carry instruction. 56 CMPC, 57 /// Test for zero or minus instruction. 58 TST, 59 /// Operand 0 and operand 1 are selection variable, operand 2 60 /// is condition code and operand 3 is flag operand. 61 SELECT_CC 62 }; 63 64 } // end of namespace AVRISD 65 66 class AVRSubtarget; 67 class AVRTargetMachine; 68 69 /// Performs target lowering for the AVR. 70 class AVRTargetLowering : public TargetLowering { 71 public: 72 explicit AVRTargetLowering(const AVRTargetMachine &TM, 73 const AVRSubtarget &STI); 74 75 public: 76 MVT getScalarShiftAmountTy(const DataLayout &, EVT LHSTy) const override { 77 return MVT::i8; 78 } 79 80 MVT::SimpleValueType getCmpLibcallReturnType() const override { 81 return MVT::i8; 82 } 83 84 const char *getTargetNodeName(unsigned Opcode) const override; 85 86 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 87 88 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 89 SelectionDAG &DAG) const override; 90 91 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 92 unsigned AS, 93 Instruction *I = nullptr) const override; 94 95 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, 96 ISD::MemIndexedMode &AM, 97 SelectionDAG &DAG) const override; 98 99 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, 100 SDValue &Offset, ISD::MemIndexedMode &AM, 101 SelectionDAG &DAG) const override; 102 103 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 104 105 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 106 EVT VT) const override; 107 108 MachineBasicBlock * 109 EmitInstrWithCustomInserter(MachineInstr &MI, 110 MachineBasicBlock *MBB) const override; 111 112 ConstraintType getConstraintType(StringRef Constraint) const override; 113 114 ConstraintWeight 115 getSingleConstraintMatchWeight(AsmOperandInfo &info, 116 const char *constraint) const override; 117 118 std::pair<unsigned, const TargetRegisterClass *> 119 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 120 StringRef Constraint, MVT VT) const override; 121 122 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override; 123 124 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 125 std::vector<SDValue> &Ops, 126 SelectionDAG &DAG) const override; 127 128 Register getRegisterByName(const char* RegName, LLT VT, 129 const MachineFunction &MF) const override; 130 131 bool shouldSplitFunctionArgumentsAsLittleEndian(const DataLayout &DL) 132 const override { 133 return false; 134 } 135 136 private: 137 SDValue getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AVRcc, 138 SelectionDAG &DAG, SDLoc dl) const; 139 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const; 140 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const; 141 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 142 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 143 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 144 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const; 145 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 146 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 147 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 148 149 CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC) const; 150 151 bool CanLowerReturn(CallingConv::ID CallConv, 152 MachineFunction &MF, bool isVarArg, 153 const SmallVectorImpl<ISD::OutputArg> &Outs, 154 LLVMContext &Context) const override; 155 156 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 157 const SmallVectorImpl<ISD::OutputArg> &Outs, 158 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl, 159 SelectionDAG &DAG) const override; 160 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 161 bool isVarArg, 162 const SmallVectorImpl<ISD::InputArg> &Ins, 163 const SDLoc &dl, SelectionDAG &DAG, 164 SmallVectorImpl<SDValue> &InVals) const override; 165 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 166 SmallVectorImpl<SDValue> &InVals) const override; 167 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 168 CallingConv::ID CallConv, bool isVarArg, 169 const SmallVectorImpl<ISD::InputArg> &Ins, 170 const SDLoc &dl, SelectionDAG &DAG, 171 SmallVectorImpl<SDValue> &InVals) const; 172 173 protected: 174 175 const AVRSubtarget &Subtarget; 176 177 private: 178 MachineBasicBlock *insertShift(MachineInstr &MI, MachineBasicBlock *BB) const; 179 MachineBasicBlock *insertMul(MachineInstr &MI, MachineBasicBlock *BB) const; 180 }; 181 182 } // end namespace llvm 183 184 #endif // LLVM_AVR_ISEL_LOWERING_H 185