1//===-- AVRInstrInfo.td - AVR Instruction Formats ----------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// AVR Instruction Format Definitions. 10// 11//===----------------------------------------------------------------------===// 12 13// A generic AVR instruction. 14class AVRInst<dag outs, dag ins, string asmstr, list<dag> pattern> 15 : Instruction { 16 let Namespace = "AVR"; 17 18 dag OutOperandList = outs; 19 dag InOperandList = ins; 20 let AsmString = asmstr; 21 let Pattern = pattern; 22 23 field bits<32> SoftFail = 0; 24} 25 26/// A 16-bit AVR instruction. 27class AVRInst16<dag outs, dag ins, string asmstr, list<dag> pattern> 28 : AVRInst<outs, ins, asmstr, pattern> { 29 field bits<16> Inst; 30 31 let Size = 2; 32} 33 34/// a 32-bit AVR instruction. 35class AVRInst32<dag outs, dag ins, string asmstr, list<dag> pattern> 36 : AVRInst<outs, ins, asmstr, pattern> { 37 field bits<32> Inst; 38 39 let Size = 4; 40} 41 42// A class for pseudo instructions. 43// Pseudo instructions are not real AVR instructions. The DAG stores 44// pseudo instructions which are replaced by real AVR instructions by 45// AVRExpandPseudoInsts.cpp. 46// 47// For example, the ADDW (add wide, as in add 16 bit values) instruction 48// is defined as a pseudo instruction. In AVRExpandPseudoInsts.cpp, 49// the instruction is then replaced by two add instructions - one for each byte. 50class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> 51 : AVRInst16<outs, ins, asmstr, pattern> { 52 let Pattern = pattern; 53 54 let isPseudo = 1; 55 let isCodeGenOnly = 1; 56} 57 58//===----------------------------------------------------------------------===// 59// Register / register instruction: <|opcode|ffrd|dddd|rrrr|> 60// opcode = 4 bits. 61// f = secondary opcode = 2 bits 62// d = destination = 5 bits 63// r = source = 5 bits 64// (Accepts all registers) 65//===----------------------------------------------------------------------===// 66class FRdRr<bits<4> opcode, bits<2> f, dag outs, dag ins, string asmstr, 67 list<dag> pattern> : AVRInst16<outs, ins, asmstr, pattern> { 68 bits<5> rd; 69 bits<5> rr; 70 71 let Inst{15 - 12} = opcode; 72 let Inst{11 - 10} = f; 73 let Inst{9} = rr{4}; 74 let Inst{8 - 4} = rd; 75 let Inst{3 - 0} = rr{3 - 0}; 76} 77 78class FTST<bits<4> opcode, bits<2> f, dag outs, dag ins, string asmstr, 79 list<dag> pattern> : AVRInst16<outs, ins, asmstr, pattern> { 80 bits<5> rd; 81 82 let Inst{15 - 12} = opcode; 83 let Inst{11 - 10} = f; 84 let Inst{9} = rd{4}; 85 let Inst{8 - 4} = rd; 86 let Inst{3 - 0} = rd{3 - 0}; 87} 88 89//===----------------------------------------------------------------------===// 90// Instruction of the format `<mnemonic> Z, Rd` 91// <|1001|001r|rrrr|0ttt> 92//===----------------------------------------------------------------------===// 93class FZRd<bits<3> t, dag outs, dag ins, string asmstr, list<dag> pattern> 94 : AVRInst16<outs, ins, asmstr, pattern> { 95 bits<5> rd; 96 97 let Inst{15 - 12} = 0b1001; 98 99 let Inst{11 - 9} = 0b001; 100 let Inst{8} = rd{4}; 101 102 let Inst{7 - 4} = rd{3 - 0}; 103 104 let Inst{3} = 0; 105 let Inst{2 - 0} = t; 106} 107 108//===----------------------------------------------------------------------===// 109// Register / immediate8 instruction: <|opcode|KKKK|dddd|KKKK|> 110// opcode = 4 bits. 111// K = constant data = 8 bits 112// d = destination = 4 bits 113// (Only accepts r16-r31) 114//===----------------------------------------------------------------------===// 115class FRdK<bits<4> opcode, dag outs, dag ins, string asmstr, list<dag> pattern> 116 : AVRInst16<outs, ins, asmstr, pattern> { 117 bits<4> rd; 118 bits<8> k; 119 120 let Inst{15 - 12} = opcode; 121 let Inst{11 - 8} = k{7 - 4}; 122 let Inst{7 - 4} = rd{3 - 0}; 123 let Inst{3 - 0} = k{3 - 0}; 124 125 let isAsCheapAsAMove = 1; 126} 127 128//===----------------------------------------------------------------------===// 129// Register instruction: <|opcode|fffd|dddd|ffff|> 130// opcode = 4 bits. 131// f = secondary opcode = 7 bits 132// d = destination = 5 bits 133// (Accepts all registers) 134//===----------------------------------------------------------------------===// 135class FRd<bits<4> opcode, bits<7> f, dag outs, dag ins, string asmstr, 136 list<dag> pattern> : AVRInst16<outs, ins, asmstr, pattern> { 137 bits<5> d; 138 139 let Inst{15 - 12} = opcode; 140 let Inst{11 - 9} = f{6 - 4}; 141 let Inst{8 - 4} = d; 142 let Inst{3 - 0} = f{3 - 0}; 143 144 let DecoderMethod = "decodeFRd"; 145} 146 147//===----------------------------------------------------------------------===// 148// [STD/LDD] P+q, Rr special encoding: <|10q0|qqtr|rrrr|pqqq> 149// t = type (1 for STD, 0 for LDD) 150// q = displacement (6 bits) 151// r = register (5 bits) 152// p = pointer register (1 bit) [1 for Y, 0 for Z] 153//===----------------------------------------------------------------------===// 154class FSTDLDD<bit type, dag outs, dag ins, string asmstr, list<dag> pattern> 155 : AVRInst16<outs, ins, asmstr, pattern> { 156 bits<7> memri; 157 bits<5> reg; // the GP register 158 159 let Inst{15 - 14} = 0b10; 160 let Inst{13} = memri{5}; 161 let Inst{12} = 0; 162 163 let Inst{11 - 10} = memri{4 - 3}; 164 let Inst{9} = type; 165 let Inst{8} = reg{4}; 166 167 let Inst{7 - 4} = reg{3 - 0}; 168 169 let Inst{3} = memri{6}; 170 let Inst{2 - 0} = memri{2 - 0}; 171} 172 173//===---------------------------------------------------------------------===// 174// An ST/LD instruction. 175// <|100i|00tr|rrrr|ppaa|> 176// t = type (1 for store, 0 for load) 177// a = regular/postinc/predec (reg = 0b00, postinc = 0b01, predec = 0b10) 178// p = pointer register 179// r = src/dst register 180// 181// Note that the bit labelled 'i' above does not follow a simple pattern, 182// so there exists a post encoder method to set it manually. 183//===---------------------------------------------------------------------===// 184class FSTLD<bit type, bits<2> mode, dag outs, dag ins, string asmstr, 185 list<dag> pattern> : AVRInst16<outs, ins, asmstr, pattern> { 186 bits<2> ptrreg; 187 bits<5> reg; 188 189 let Inst{15 - 13} = 0b100; 190 // This bit varies depending on the arguments and the mode. 191 // We have a post encoder method to set this bit manually. 192 let Inst{12} = 0; 193 194 let Inst{11 - 10} = 0b00; 195 let Inst{9} = type; 196 let Inst{8} = reg{4}; 197 198 let Inst{7 - 4} = reg{3 - 0}; 199 200 let Inst{3 - 2} = ptrreg{1 - 0}; 201 let Inst{1 - 0} = mode{1 - 0}; 202 203 let PostEncoderMethod = "loadStorePostEncoder"; 204} 205 206//===---------------------------------------------------------------------===// 207// Special format for the LPM/ELPM instructions 208// [E]LPM Rd, Z[+] 209// <|1001|000d|dddd|01ep> 210// d = destination register 211// e = is elpm 212// p = is postincrement 213//===---------------------------------------------------------------------===// 214class FLPMX<bit e, bit p, dag outs, dag ins, string asmstr, list<dag> pattern> 215 : AVRInst16<outs, ins, asmstr, pattern> { 216 bits<5> reg; 217 218 let Inst{15 - 12} = 0b1001; 219 220 let Inst{11 - 9} = 0b000; 221 let Inst{8} = reg{4}; 222 223 let Inst{7 - 4} = reg{3 - 0}; 224 225 let Inst{3 - 2} = 0b01; 226 let Inst{1} = e; 227 let Inst{0} = p; 228 229 let DecoderMethod = "decodeFLPMX"; 230} 231 232//===----------------------------------------------------------------------===// 233// MOVWRdRr special encoding: <|0000|0001|dddd|rrrr|> 234// d = destination = 4 bits 235// r = source = 4 bits 236// (Only accepts even registers) 237//===----------------------------------------------------------------------===// 238class FMOVWRdRr<dag outs, dag ins, string asmstr, list<dag> pattern> 239 : AVRInst16<outs, ins, asmstr, pattern> { 240 bits<5> d; 241 bits<5> r; 242 243 let Inst{15 - 8} = 0b00000001; 244 let Inst{7 - 4} = d{4 - 1}; 245 let Inst{3 - 0} = r{4 - 1}; 246 247 let DecoderMethod = "decodeFMOVWRdRr"; 248} 249 250//===----------------------------------------------------------------------===// 251// MULSrr special encoding: <|0000|0010|dddd|rrrr|> 252// d = multiplicand = 4 bits 253// r = multiplier = 4 bits 254// (Only accepts r16-r31) 255//===----------------------------------------------------------------------===// 256class FMUL2RdRr<bit f, dag outs, dag ins, string asmstr, list<dag> pattern> 257 : AVRInst16<outs, ins, asmstr, pattern> { 258 bits<5> rd; // accept 5 bits but only encode the lower 4 259 bits<5> rr; // accept 5 bits but only encode the lower 4 260 261 let Inst{15 - 9} = 0b0000001; 262 let Inst{8} = f; 263 let Inst{7 - 4} = rd{3 - 0}; 264 let Inst{3 - 0} = rr{3 - 0}; 265 266 let DecoderMethod = "decodeFMUL2RdRr"; 267} 268 269// Special encoding for the FMUL family of instructions. 270// 271// <0000|0011|fddd|frrr|> 272// 273// ff = 0b01 for FMUL 274// 0b10 for FMULS 275// 0b11 for FMULSU 276// 277// ddd = destination register 278// rrr = source register 279class FFMULRdRr<bits<2> f, dag outs, dag ins, string asmstr, list<dag> pattern> 280 : AVRInst16<outs, ins, asmstr, pattern> { 281 bits<3> rd; 282 bits<3> rr; 283 284 let Inst{15 - 8} = 0b00000011; 285 let Inst{7} = f{1}; 286 let Inst{6 - 4} = rd; 287 let Inst{3} = f{0}; 288 let Inst{2 - 0} = rr; 289 290 let DecoderMethod = "decodeFFMULRdRr"; 291} 292 293//===----------------------------------------------------------------------===// 294// Arithmetic word instructions (ADIW / SBIW): <|1001|011f|kkdd|kkkk|> 295// f = secondary opcode = 1 bit 296// k = constant data = 6 bits 297// d = destination = 4 bits 298// (Only accepts r25:24 r27:26 r29:28 r31:30) 299//===----------------------------------------------------------------------===// 300class FWRdK<bit f, dag outs, dag ins, string asmstr, list<dag> pattern> 301 : AVRInst16<outs, ins, asmstr, pattern> { 302 bits<5> dst; // accept 5 bits but only encode bits 1 and 2 303 bits<6> k; 304 305 let Inst{15 - 9} = 0b1001011; 306 let Inst{8} = f; 307 let Inst{7 - 6} = k{5 - 4}; 308 let Inst{5 - 4} = dst{2 - 1}; 309 let Inst{3 - 0} = k{3 - 0}; 310 311 let DecoderMethod = "decodeFWRdK"; 312} 313 314//===----------------------------------------------------------------------===// 315// In I/O instruction: <|1011|0AAd|dddd|AAAA|> 316// A = I/O location address = 6 bits 317// d = destination = 5 bits 318// (Accepts all registers) 319//===----------------------------------------------------------------------===// 320class FIORdA<dag outs, dag ins, string asmstr, list<dag> pattern> 321 : AVRInst16<outs, ins, asmstr, pattern> { 322 bits<5> d; 323 bits<6> A; 324 325 let Inst{15 - 11} = 0b10110; 326 let Inst{10 - 9} = A{5 - 4}; 327 let Inst{8 - 4} = d; 328 let Inst{3 - 0} = A{3 - 0}; 329 330 let DecoderMethod = "decodeFIORdA"; 331} 332 333//===----------------------------------------------------------------------===// 334// Out I/O instruction: <|1011|1AAr|rrrr|AAAA|> 335// A = I/O location address = 6 bits 336// d = destination = 5 bits 337// (Accepts all registers) 338//===----------------------------------------------------------------------===// 339class FIOARr<dag outs, dag ins, string asmstr, list<dag> pattern> 340 : AVRInst16<outs, ins, asmstr, pattern> { 341 bits<6> A; 342 bits<5> r; 343 344 let Inst{15 - 11} = 0b10111; 345 let Inst{10 - 9} = A{5 - 4}; 346 let Inst{8 - 4} = r; 347 let Inst{3 - 0} = A{3 - 0}; 348 349 let DecoderMethod = "decodeFIOARr"; 350} 351 352//===----------------------------------------------------------------------===// 353// I/O bit instruction. 354// <|1001|10tt|AAAA|Abbb> 355// t = type (1 for SBI, 0 for CBI) 356// A = I/O location address (5 bits) 357// b = bit number 358//===----------------------------------------------------------------------===// 359class FIOBIT<bits<2> t, dag outs, dag ins, string asmstr, list<dag> pattern> 360 : AVRInst16<outs, ins, asmstr, pattern> { 361 bits<5> A; 362 bits<3> b; 363 364 let Inst{15 - 12} = 0b1001; 365 366 let Inst{11 - 10} = 0b10; 367 let Inst{9 - 8} = t; 368 369 let Inst{7 - 4} = A{4 - 1}; 370 371 let Inst{3} = A{0}; 372 let Inst{2 - 0} = b{2 - 0}; 373 374 let DecoderMethod = "decodeFIOBIT"; 375} 376 377//===----------------------------------------------------------------------===// 378// BST/BLD instruction. 379// <|1111|1ttd|dddd|0bbb> 380// t = type (1 for BST, 0 for BLD) 381// d = destination register 382// b = bit 383//===----------------------------------------------------------------------===// 384class FRdB<bits<2> t, dag outs, dag ins, string asmstr, list<dag> pattern> 385 : AVRInst16<outs, ins, asmstr, pattern> { 386 bits<5> rd; 387 bits<3> b; 388 389 let Inst{15 - 12} = 0b1111; 390 391 let Inst{11} = 0b1; 392 let Inst{10 - 9} = t; 393 let Inst{8} = rd{4}; 394 395 let Inst{7 - 4} = rd{3 - 0}; 396 397 let Inst{3} = 0; 398 let Inst{2 - 0} = b; 399} 400 401// Special encoding for the `DES K` instruction. 402// 403// <|1001|0100|KKKK|1011> 404// 405// KKKK = 4 bit immediate 406class FDES<dag outs, dag ins, string asmstr, list<dag> pattern> 407 : AVRInst16<outs, ins, asmstr, pattern> { 408 bits<4> k; 409 410 let Inst{15 - 12} = 0b1001; 411 412 let Inst{11 - 8} = 0b0100; 413 414 let Inst{7 - 4} = k; 415 416 let Inst{3 - 0} = 0b1011; 417} 418 419//===----------------------------------------------------------------------===// 420// Conditional Branching instructions: <|1111|0fkk|kkkk|ksss|> 421// f = secondary opcode = 1 bit 422// k = constant address = 7 bits 423// s = bit in status register = 3 bits 424//===----------------------------------------------------------------------===// 425class FBRsk<bit f, bits<3> s, dag outs, dag ins, string asmstr, 426 list<dag> pattern> : AVRInst16<outs, ins, asmstr, pattern> { 427 bits<7> k; 428 429 let Inst{15 - 11} = 0b11110; 430 let Inst{10} = f; 431 let Inst{9 - 3} = k; 432 let Inst{2 - 0} = s; 433} 434 435//===----------------------------------------------------------------------===// 436// Special, opcode only instructions: <|opcode|> 437//===----------------------------------------------------------------------===// 438 439class F16<bits<16> opcode, dag outs, dag ins, string asmstr, list<dag> pattern> 440 : AVRInst16<outs, ins, asmstr, pattern> { 441 let Inst = opcode; 442} 443 444class F32<bits<32> opcode, dag outs, dag ins, string asmstr, list<dag> pattern> 445 : AVRInst32<outs, ins, asmstr, pattern> { 446 let Inst = opcode; 447} 448 449//===----------------------------------------------------------------------===// 450// Branching instructions with immediate12: <|110f|kkkk|kkkk|kkkk|> 451// f = secondary opcode = 1 bit 452// k = constant address = 12 bits 453//===----------------------------------------------------------------------===// 454class FBRk<bit f, dag outs, dag ins, string asmstr, list<dag> pattern> 455 : AVRInst16<outs, ins, asmstr, pattern> { 456 bits<12> k; 457 458 let Inst{15 - 13} = 0b110; 459 let Inst{12} = f; 460 let Inst{11 - 0} = k; 461} 462 463//===----------------------------------------------------------------------===// 464// 32 bits branching instructions: <|1001|010k|kkkk|fffk|kkkk|kkkk|kkkk|kkkk|> 465// f = secondary opcode = 3 bits 466// k = constant address = 22 bits 467//===----------------------------------------------------------------------===// 468class F32BRk<bits<3> f, dag outs, dag ins, string asmstr, list<dag> pattern> 469 : AVRInst32<outs, ins, asmstr, pattern> { 470 bits<22> k; 471 472 let Inst{31 - 25} = 0b1001010; 473 let Inst{24 - 20} = k{21 - 17}; 474 let Inst{19 - 17} = f; 475 let Inst{16 - 0} = k{16 - 0}; 476} 477 478//===----------------------------------------------------------------------===// 479// 32 bits direct mem instructions: <|1001|00fd|dddd|0000|kkkk|kkkk|kkkk|kkkk|> 480// f = secondary opcode = 1 bit 481// d = destination = 5 bits 482// k = constant address = 16 bits 483// (Accepts all registers) 484//===----------------------------------------------------------------------===// 485class F32DM<bit f, dag outs, dag ins, string asmstr, list<dag> pattern> 486 : AVRInst32<outs, ins, asmstr, pattern> { 487 bits<5> rd; 488 bits<16> k; 489 490 let Inst{31 - 28} = 0b1001; 491 492 let Inst{27 - 26} = 0b00; 493 let Inst{25} = f; 494 let Inst{24} = rd{4}; 495 496 let Inst{23 - 20} = rd{3 - 0}; 497 498 let Inst{19 - 16} = 0b0000; 499 500 let Inst{15 - 0} = k; 501} 502 503// <|1001|0100|bfff|1000> 504class FS<bit b, dag outs, dag ins, string asmstr, list<dag> pattern> 505 : AVRInst16<outs, ins, asmstr, pattern> { 506 bits<3> s; 507 508 let Inst{15 - 12} = 0b1001; 509 510 let Inst{11 - 8} = 0b0100; 511 512 let Inst{7} = b; 513 let Inst{6 - 4} = s; 514 515 let Inst{3 - 0} = 0b1000; 516} 517 518// Set/clr bit in status flag instructions/ 519// <BRBS|BRBC> s, k 520// --------------------- 521// <|1111|0fkk|kkkk|ksss> 522class FSK<bit f, dag outs, dag ins, string asmstr, list<dag> pattern> 523 : AVRInst16<outs, ins, asmstr, pattern> { 524 bits<7> k; 525 bits<3> s; 526 527 let Inst{15 - 12} = 0b1111; 528 529 let Inst{11} = 0; 530 let Inst{10} = f; 531 let Inst{9 - 8} = k{6 - 5}; 532 533 let Inst{7 - 4} = k{4 - 1}; 534 535 let Inst{3} = k{0}; 536 let Inst{2 - 0} = s; 537} 538 539class ExtensionPseudo<dag outs, dag ins, string asmstr, list<dag> pattern> 540 : Pseudo<outs, ins, asmstr, pattern> { 541 let Defs = [SREG]; 542} 543 544class StorePseudo<dag outs, dag ins, string asmstr, list<dag> pattern> 545 : Pseudo<outs, ins, asmstr, pattern> { 546 let Defs = [SP]; 547} 548 549class SelectPseudo<dag outs, dag ins, string asmstr, list<dag> pattern> 550 : Pseudo<outs, ins, asmstr, pattern> { 551 let usesCustomInserter = 1; 552 553 let Uses = [SREG]; 554} 555 556class ShiftPseudo<dag outs, dag ins, string asmstr, list<dag> pattern> 557 : Pseudo<outs, ins, asmstr, pattern> { 558 let usesCustomInserter = 1; 559 560 let Defs = [SREG]; 561} 562