1//===-- AVRInstrInfo.td - AVR Instruction defs -------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the AVR instructions in TableGen format. 10// 11//===----------------------------------------------------------------------===// 12 13include "AVRInstrFormats.td" 14 15//===----------------------------------------------------------------------===// 16// AVR Type Profiles 17//===----------------------------------------------------------------------===// 18 19def SDT_AVRCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>; 20def SDT_AVRCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>; 21def SDT_AVRCall : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; 22def SDT_AVRWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 23def SDT_AVRBrcond : SDTypeProfile<0, 2, 24 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i8>]>; 25def SDT_AVRCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 26def SDT_AVRTst : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 27def SDT_AVRSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 28 SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; 29 30//===----------------------------------------------------------------------===// 31// AVR Specific Node Definitions 32//===----------------------------------------------------------------------===// 33 34def AVRretflag : SDNode<"AVRISD::RET_FLAG", SDTNone, 35 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 36def AVRretiflag : SDNode<"AVRISD::RETI_FLAG", SDTNone, 37 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 38 39def AVRcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AVRCallSeqStart, 40 [SDNPHasChain, SDNPOutGlue]>; 41def AVRcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_AVRCallSeqEnd, 42 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 43 44def AVRcall : SDNode<"AVRISD::CALL", SDT_AVRCall, 45 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, SDNPVariadic]>; 46 47def AVRWrapper : SDNode<"AVRISD::WRAPPER", SDT_AVRWrapper>; 48 49def AVRbrcond : SDNode<"AVRISD::BRCOND", SDT_AVRBrcond, 50 [SDNPHasChain, SDNPInGlue]>; 51def AVRcmp : SDNode<"AVRISD::CMP", SDT_AVRCmp, [SDNPOutGlue]>; 52def AVRcmpc : SDNode<"AVRISD::CMPC", SDT_AVRCmp, [SDNPInGlue, SDNPOutGlue]>; 53def AVRtst : SDNode<"AVRISD::TST", SDT_AVRTst, [SDNPOutGlue]>; 54def AVRselectcc: SDNode<"AVRISD::SELECT_CC", SDT_AVRSelectCC, [SDNPInGlue]>; 55 56// Shift nodes. 57def AVRlsl : SDNode<"AVRISD::LSL", SDTIntUnaryOp>; 58def AVRlsr : SDNode<"AVRISD::LSR", SDTIntUnaryOp>; 59def AVRrol : SDNode<"AVRISD::ROL", SDTIntUnaryOp>; 60def AVRror : SDNode<"AVRISD::ROR", SDTIntUnaryOp>; 61def AVRasr : SDNode<"AVRISD::ASR", SDTIntUnaryOp>; 62def AVRlslbn : SDNode<"AVRISD::LSLBN", SDTIntBinOp>; 63def AVRlsrbn : SDNode<"AVRISD::LSRBN", SDTIntBinOp>; 64def AVRasrbn : SDNode<"AVRISD::ASRBN", SDTIntBinOp>; 65def AVRlslwn : SDNode<"AVRISD::LSLWN", SDTIntBinOp>; 66def AVRlsrwn : SDNode<"AVRISD::LSRWN", SDTIntBinOp>; 67def AVRasrwn : SDNode<"AVRISD::ASRWN", SDTIntBinOp>; 68 69// Pseudo shift nodes for non-constant shift amounts. 70def AVRlslLoop : SDNode<"AVRISD::LSLLOOP", SDTIntShiftOp>; 71def AVRlsrLoop : SDNode<"AVRISD::LSRLOOP", SDTIntShiftOp>; 72def AVRrolLoop : SDNode<"AVRISD::ROLLOOP", SDTIntShiftOp>; 73def AVRrorLoop : SDNode<"AVRISD::RORLOOP", SDTIntShiftOp>; 74def AVRasrLoop : SDNode<"AVRISD::ASRLOOP", SDTIntShiftOp>; 75 76// SWAP node. 77def AVRSwap : SDNode<"AVRISD::SWAP", SDTIntUnaryOp>; 78 79//===----------------------------------------------------------------------===// 80// AVR Operands, Complex Patterns and Transformations Definitions. 81//===----------------------------------------------------------------------===// 82 83def imm8_neg_XFORM : SDNodeXForm<imm, 84[{ 85 return CurDAG->getTargetConstant(-N->getAPIntValue(), SDLoc(N), MVT::i8); 86}]>; 87 88def imm16_neg_XFORM : SDNodeXForm<imm, 89[{ 90 return CurDAG->getTargetConstant(-N->getAPIntValue(), SDLoc(N), MVT::i16); 91}]>; 92 93def imm0_63_neg : PatLeaf<(imm), 94[{ 95 int64_t val = -N->getSExtValue(); 96 return val >= 0 && val < 64; 97}], imm16_neg_XFORM>; 98 99def uimm6 : PatLeaf<(imm), [{ return isUInt<6>(N->getZExtValue()); }]>; 100 101// imm_com8_XFORM - Return the complement of a imm_com8 value 102def imm_com8_XFORM : SDNodeXForm<imm, [{ 103 return CurDAG->getTargetConstant(~((uint8_t)N->getZExtValue()), SDLoc(N), 104 MVT::i8); 105}]>; 106 107// imm_com8 - Match an immediate that is a complement 108// of a 8-bit immediate. 109// Note: this pattern doesn't require an encoder method and such, as it's 110// only used on aliases (Pat<> and InstAlias<>). The actual encoding 111// is handled by the destination instructions, which use imm_com8. 112def imm_com8_asmoperand : AsmOperandClass { let Name = "ImmCom8"; } 113def imm_com8 : Operand<i8> { 114 let ParserMatchClass = imm_com8_asmoperand; 115} 116 117def ioaddr_XFORM : SDNodeXForm<imm, 118[{ 119 uint8_t offset = Subtarget->getIORegisterOffset(); 120 return CurDAG->getTargetConstant(uint8_t(N->getZExtValue()) - offset, 121 SDLoc(N), MVT::i8); 122}]>; 123 124def iobitpos8_XFORM : SDNodeXForm<imm, 125[{ 126 return CurDAG->getTargetConstant(Log2_32(uint8_t(N->getZExtValue())), 127 SDLoc(N), MVT::i8); 128}]>; 129 130def iobitposn8_XFORM : SDNodeXForm<imm, 131[{ 132 return CurDAG->getTargetConstant(Log2_32(uint8_t(~N->getZExtValue())), 133 SDLoc(N), MVT::i8); 134}]>; 135 136def ioaddr8 : PatLeaf<(imm), 137[{ 138 uint8_t offset = Subtarget->getIORegisterOffset(); 139 uint64_t val = N->getZExtValue() - offset; 140 return val < 0x40; 141}], ioaddr_XFORM>; 142 143def lowioaddr8 : PatLeaf<(imm), 144[{ 145 uint8_t offset = Subtarget->getIORegisterOffset(); 146 uint64_t val = N->getZExtValue() - offset; 147 return val < 0x20; 148}], ioaddr_XFORM>; 149 150def ioaddr16 : PatLeaf<(imm), 151[{ 152 uint8_t offset = Subtarget->getIORegisterOffset(); 153 uint64_t val = N->getZExtValue() - offset; 154 return val < 0x3f; 155}], ioaddr_XFORM>; 156 157def iobitpos8 : PatLeaf<(imm), 158[{ 159 return isPowerOf2_32(uint8_t(N->getZExtValue())); 160}], iobitpos8_XFORM>; 161 162def iobitposn8 : PatLeaf<(imm), 163[{ 164 return isPowerOf2_32(uint8_t(~N->getZExtValue())); 165}], iobitposn8_XFORM>; 166 167def MemriAsmOperand : AsmOperandClass { 168 let Name = "Memri"; 169 let ParserMethod = "parseMemriOperand"; 170} 171 172/// Address operand for `reg+imm` used by STD and LDD. 173def memri : Operand<iPTR> 174{ 175 let MIOperandInfo = (ops PTRDISPREGS, i16imm); 176 177 let PrintMethod = "printMemri"; 178 let EncoderMethod = "encodeMemri"; 179 180 let ParserMatchClass = MemriAsmOperand; 181} 182 183// Address operand for `SP+imm` used by STD{W}SPQRr 184def memspi : Operand<iPTR> 185{ 186 let MIOperandInfo = (ops GPRSP, i16imm); 187} 188 189def relbrtarget_7 : Operand<OtherVT> 190{ 191 let PrintMethod = "printPCRelImm"; 192 let EncoderMethod = "encodeRelCondBrTarget<AVR::fixup_7_pcrel>"; 193} 194 195def brtarget_13 : Operand<OtherVT> 196{ 197 let PrintMethod = "printPCRelImm"; 198 let EncoderMethod = "encodeRelCondBrTarget<AVR::fixup_13_pcrel>"; 199} 200 201// The target of a 22 or 16-bit call/jmp instruction. 202def call_target : Operand<iPTR> 203{ 204 let EncoderMethod = "encodeCallTarget"; 205 let DecoderMethod = "decodeCallTarget"; 206} 207 208// A 16-bit address (which can lead to an R_AVR_16 relocation). 209def imm16 : Operand<i16> 210{ 211 let EncoderMethod = "encodeImm<AVR::fixup_16, 2>"; 212} 213 214/// A 6-bit immediate used in the ADIW/SBIW instructions. 215def imm_arith6 : Operand<i16> 216{ 217 let EncoderMethod = "encodeImm<AVR::fixup_6_adiw, 0>"; 218} 219 220/// An 8-bit immediate inside an instruction with the same format 221/// as the `LDI` instruction (the `FRdK` format). 222def imm_ldi8 : Operand<i8> 223{ 224 let EncoderMethod = "encodeImm<AVR::fixup_ldi, 0>"; 225} 226 227/// A 5-bit port number used in SBIC and friends (the `FIOBIT` format). 228def imm_port5 : Operand<i8> 229{ 230 let EncoderMethod = "encodeImm<AVR::fixup_port5, 0>"; 231} 232 233/// A 6-bit port number used in the `IN` instruction and friends (the 234/// `FIORdA` format. 235def imm_port6 : Operand<i8> 236{ 237 let EncoderMethod = "encodeImm<AVR::fixup_port6, 0>"; 238} 239 240// Addressing mode pattern reg+imm6 241def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], [SDNPWantRoot]>; 242 243// AsmOperand class for a pointer register. 244// Used with the LD/ST family of instructions. 245// See FSTLD in AVRInstrFormats.td 246def PtrRegAsmOperand : AsmOperandClass 247{ 248 let Name = "Reg"; 249} 250 251// A special operand type for the LD/ST instructions. 252// It converts the pointer register number into a two-bit field used in the 253// instruction. 254def LDSTPtrReg : Operand<i16> 255{ 256 let MIOperandInfo = (ops PTRREGS); 257 let EncoderMethod = "encodeLDSTPtrReg"; 258 259 let ParserMatchClass = PtrRegAsmOperand; 260} 261 262// A special operand type for the LDD/STD instructions. 263// It behaves identically to the LD/ST version, except restricts 264// the pointer registers to Y and Z. 265def LDDSTDPtrReg : Operand<i16> 266{ 267 let MIOperandInfo = (ops PTRDISPREGS); 268 let EncoderMethod = "encodeLDSTPtrReg"; 269 270 let ParserMatchClass = PtrRegAsmOperand; 271} 272 273//===----------------------------------------------------------------------===// 274// AVR predicates for subtarget features 275//===----------------------------------------------------------------------===// 276 277def HasSRAM : Predicate<"Subtarget->hasSRAM()">, 278 AssemblerPredicate<(all_of FeatureSRAM)>; 279 280def HasJMPCALL : Predicate<"Subtarget->hasJMPCALL()">, 281 AssemblerPredicate<(all_of FeatureJMPCALL)>; 282 283def HasIJMPCALL : Predicate<"Subtarget->hasIJMPCALL()">, 284 AssemblerPredicate<(all_of FeatureIJMPCALL)>; 285 286def HasEIJMPCALL : Predicate<"Subtarget->hasEIJMPCALL()">, 287 AssemblerPredicate<(all_of FeatureEIJMPCALL)>; 288 289def HasADDSUBIW : Predicate<"Subtarget->hasADDSUBIW()">, 290 AssemblerPredicate<(all_of FeatureADDSUBIW)>; 291 292def HasSmallStack : Predicate<"Subtarget->HasSmallStack()">, 293 AssemblerPredicate<(all_of FeatureSmallStack)>; 294 295def HasMOVW : Predicate<"Subtarget->hasMOVW()">, 296 AssemblerPredicate<(all_of FeatureMOVW)>; 297 298def HasLPM : Predicate<"Subtarget->hasLPM()">, 299 AssemblerPredicate<(all_of FeatureLPM)>; 300 301def HasLPMX : Predicate<"Subtarget->hasLPMX()">, 302 AssemblerPredicate<(all_of FeatureLPMX)>; 303 304def HasELPM : Predicate<"Subtarget->hasELPM()">, 305 AssemblerPredicate<(all_of FeatureELPM)>; 306 307def HasELPMX : Predicate<"Subtarget->hasELPMX()">, 308 AssemblerPredicate<(all_of FeatureELPMX)>; 309 310def HasSPM : Predicate<"Subtarget->hasSPM()">, 311 AssemblerPredicate<(all_of FeatureSPM)>; 312 313def HasSPMX : Predicate<"Subtarget->hasSPMX()">, 314 AssemblerPredicate<(all_of FeatureSPMX)>; 315 316def HasDES : Predicate<"Subtarget->hasDES()">, 317 AssemblerPredicate<(all_of FeatureDES)>; 318 319def SupportsRMW : Predicate<"Subtarget->supportsRMW()">, 320 AssemblerPredicate<(all_of FeatureRMW)>; 321 322def SupportsMultiplication : Predicate<"Subtarget->supportsMultiplication()">, 323 AssemblerPredicate<(all_of FeatureMultiplication)>; 324 325def HasBREAK : Predicate<"Subtarget->hasBREAK()">, 326 AssemblerPredicate<(all_of FeatureBREAK)>; 327 328def HasTinyEncoding : Predicate<"Subtarget->hasTinyEncoding()">, 329 AssemblerPredicate<(all_of FeatureTinyEncoding)>; 330 331 332// AVR specific condition code. These correspond to AVR_*_COND in 333// AVRInstrInfo.td. They must be kept in synch. 334def AVR_COND_EQ : PatLeaf<(i8 0)>; 335def AVR_COND_NE : PatLeaf<(i8 1)>; 336def AVR_COND_GE : PatLeaf<(i8 2)>; 337def AVR_COND_LT : PatLeaf<(i8 3)>; 338def AVR_COND_SH : PatLeaf<(i8 4)>; 339def AVR_COND_LO : PatLeaf<(i8 5)>; 340def AVR_COND_MI : PatLeaf<(i8 6)>; 341def AVR_COND_PL : PatLeaf<(i8 7)>; 342 343 344//===----------------------------------------------------------------------===// 345//===----------------------------------------------------------------------===// 346// AVR Instruction list 347//===----------------------------------------------------------------------===// 348//===----------------------------------------------------------------------===// 349 350// ADJCALLSTACKDOWN/UP implicitly use/def SP because they may be expanded into 351// a stack adjustment and the codegen must know that they may modify the stack 352// pointer before prolog-epilog rewriting occurs. 353// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 354// sub / add which can clobber SREG. 355let Defs = [SP, SREG], 356Uses = [SP] in 357{ 358 def ADJCALLSTACKDOWN : Pseudo<(outs), 359 (ins i16imm:$amt, i16imm:$amt2), 360 "#ADJCALLSTACKDOWN", 361 [(AVRcallseq_start timm:$amt, timm:$amt2)]>; 362 363 // R31R30 is used to update SP. It is normally free because it is a 364 // call-clobbered register but it is necessary to set it as a def as the 365 // register allocator might use it in rare cases (for rematerialization, it 366 // seems). hasSideEffects needs to be set to true so this instruction isn't 367 // considered dead. 368 let Defs = [R31R30], 369 hasSideEffects=1 in 370 def ADJCALLSTACKUP : Pseudo<(outs), 371 (ins i16imm:$amt1, i16imm:$amt2), 372 "#ADJCALLSTACKUP", 373 [(AVRcallseq_end timm:$amt1, timm:$amt2)]>; 374} 375 376//===----------------------------------------------------------------------===// 377// Addition 378//===----------------------------------------------------------------------===// 379let isCommutable = 1, 380Constraints = "$src = $rd", 381Defs = [SREG] in 382{ 383 // ADD Rd, Rr 384 // Adds two 8-bit registers. 385 def ADDRdRr : FRdRr<0b0000, 386 0b11, 387 (outs GPR8:$rd), 388 (ins GPR8:$src, GPR8:$rr), 389 "add\t$rd, $rr", 390 [(set i8:$rd, (add i8:$src, i8:$rr)), 391 (implicit SREG)]>; 392 393 // ADDW Rd+1:Rd, Rr+1:Rr 394 // Pseudo instruction to add four 8-bit registers as two 16-bit values. 395 // 396 // Expands to: 397 // add Rd, Rr 398 // adc Rd+1, Rr+1 399 def ADDWRdRr : Pseudo<(outs DREGS:$rd), 400 (ins DREGS:$src, DREGS:$rr), 401 "addw\t$rd, $rr", 402 [(set i16:$rd, (add i16:$src, i16:$rr)), 403 (implicit SREG)]>; 404 405 // ADC Rd, Rr 406 // Adds two 8-bit registers with carry. 407 let Uses = [SREG] in 408 def ADCRdRr : FRdRr<0b0001, 409 0b11, 410 (outs GPR8:$rd), 411 (ins GPR8:$src, GPR8:$rr), 412 "adc\t$rd, $rr", 413 [(set i8:$rd, (adde i8:$src, i8:$rr)), 414 (implicit SREG)]>; 415 416 // ADCW Rd+1:Rd, Rr+1:Rr 417 // Pseudo instruction to add four 8-bit registers as two 16-bit values with 418 // carry. 419 // 420 // Expands to: 421 // adc Rd, Rr 422 // adc Rd+1, Rr+1 423 let Uses = [SREG] in 424 def ADCWRdRr : Pseudo<(outs DREGS:$rd), 425 (ins DREGS:$src, DREGS:$rr), 426 "adcw\t$rd, $rr", 427 [(set i16:$rd, (adde i16:$src, i16:$rr)), 428 (implicit SREG)]>; 429 430 // AIDW Rd, k 431 // Adds an immediate 6-bit value K to Rd, placing the result in Rd. 432 def ADIWRdK : FWRdK<0b0, 433 (outs IWREGS:$rd), 434 (ins IWREGS:$src, imm_arith6:$k), 435 "adiw\t$rd, $k", 436 [(set i16:$rd, (add i16:$src, uimm6:$k)), 437 (implicit SREG)]>, 438 Requires<[HasADDSUBIW]>; 439} 440 441//===----------------------------------------------------------------------===// 442// Subtraction 443//===----------------------------------------------------------------------===// 444let Constraints = "$src = $rd", 445Defs = [SREG] in 446{ 447 // SUB Rd, Rr 448 // Subtracts the 8-bit value of Rr from Rd and places the value in Rd. 449 def SUBRdRr : FRdRr<0b0001, 450 0b10, 451 (outs GPR8:$rd), 452 (ins GPR8:$src, GPR8:$rr), 453 "sub\t$rd, $rr", 454 [(set i8:$rd, (sub i8:$src, i8:$rr)), 455 (implicit SREG)]>; 456 457 // SUBW Rd+1:Rd, Rr+1:Rr 458 // Subtracts two 16-bit values and places the result into Rd. 459 // 460 // Expands to: 461 // sub Rd, Rr 462 // sbc Rd+1, Rr+1 463 def SUBWRdRr : Pseudo<(outs DREGS:$rd), 464 (ins DREGS:$src, DREGS:$rr), 465 "subw\t$rd, $rr", 466 [(set i16:$rd, (sub i16:$src, i16:$rr)), 467 (implicit SREG)]>; 468 469 def SUBIRdK : FRdK<0b0101, 470 (outs LD8:$rd), 471 (ins LD8:$src, imm_ldi8:$k), 472 "subi\t$rd, $k", 473 [(set i8:$rd, (sub i8:$src, imm:$k)), 474 (implicit SREG)]>; 475 476 // SUBIW Rd+1:Rd, K+1:K 477 // 478 // Expands to: 479 // subi Rd, K 480 // sbci Rd+1, K+1 481 def SUBIWRdK : Pseudo<(outs DLDREGS:$rd), 482 (ins DLDREGS:$src, i16imm:$rr), 483 "subiw\t$rd, $rr", 484 [(set i16:$rd, (sub i16:$src, imm:$rr)), 485 (implicit SREG)]>; 486 487 def SBIWRdK : FWRdK<0b1, 488 (outs IWREGS:$rd), 489 (ins IWREGS:$src, imm_arith6:$k), 490 "sbiw\t$rd, $k", 491 [(set i16:$rd, (sub i16:$src, uimm6:$k)), 492 (implicit SREG)]>, 493 Requires<[HasADDSUBIW]>; 494 495 // Subtract with carry operations which must read the carry flag in SREG. 496 let Uses = [SREG] in 497 { 498 def SBCRdRr : FRdRr<0b0000, 499 0b10, 500 (outs GPR8:$rd), 501 (ins GPR8:$src, GPR8:$rr), 502 "sbc\t$rd, $rr", 503 [(set i8:$rd, (sube i8:$src, i8:$rr)), 504 (implicit SREG)]>; 505 506 // SBCW Rd+1:Rd, Rr+1:Rr 507 // 508 // Expands to: 509 // sbc Rd, Rr 510 // sbc Rd+1, Rr+1 511 def SBCWRdRr : Pseudo<(outs DREGS:$rd), 512 (ins DREGS:$src, DREGS:$rr), 513 "sbcw\t$rd, $rr", 514 [(set i16:$rd, (sube i16:$src, i16:$rr)), 515 (implicit SREG)]>; 516 517 def SBCIRdK : FRdK<0b0100, 518 (outs LD8:$rd), 519 (ins LD8:$src, imm_ldi8:$k), 520 "sbci\t$rd, $k", 521 [(set i8:$rd, (sube i8:$src, imm:$k)), 522 (implicit SREG)]>; 523 524 // SBCIW Rd+1:Rd, K+1:K 525 // sbci Rd, K 526 // sbci Rd+1, K+1 527 def SBCIWRdK : Pseudo<(outs DLDREGS:$rd), 528 (ins DLDREGS:$src, i16imm:$rr), 529 "sbciw\t$rd, $rr", 530 [(set i16:$rd, (sube i16:$src, imm:$rr)), 531 (implicit SREG)]>; 532 } 533} 534 535//===----------------------------------------------------------------------===// 536// Increment and Decrement 537//===----------------------------------------------------------------------===// 538let Constraints = "$src = $rd", 539Defs = [SREG] in 540{ 541 def INCRd : FRd<0b1001, 542 0b0100011, 543 (outs GPR8:$rd), 544 (ins GPR8:$src), 545 "inc\t$rd", 546 [(set i8:$rd, (add i8:$src, 1)), (implicit SREG)]>; 547 548 def DECRd : FRd<0b1001, 549 0b0101010, 550 (outs GPR8:$rd), 551 (ins GPR8:$src), 552 "dec\t$rd", 553 [(set i8:$rd, (add i8:$src, -1)), (implicit SREG)]>; 554} 555 556//===----------------------------------------------------------------------===// 557// Multiplication 558//===----------------------------------------------------------------------===// 559 560let isCommutable = 1, 561Defs = [R1, R0, SREG] in 562{ 563 // MUL Rd, Rr 564 // Multiplies Rd by Rr and places the result into R1:R0. 565 let usesCustomInserter = 1 in { 566 def MULRdRr : FRdRr<0b1001, 0b11, 567 (outs), 568 (ins GPR8:$lhs, GPR8:$rhs), 569 "mul\t$lhs, $rhs", 570 [/*(set R1, R0, (smullohi i8:$lhs, i8:$rhs))*/]>, 571 Requires<[SupportsMultiplication]>; 572 573 def MULSRdRr : FMUL2RdRr<0, 574 (outs), 575 (ins LD8:$lhs, LD8:$rhs), 576 "muls\t$lhs, $rhs", 577 []>, 578 Requires<[SupportsMultiplication]>; 579 } 580 581 def MULSURdRr : FMUL2RdRr<1, 582 (outs), 583 (ins LD8lo:$lhs, LD8lo:$rhs), 584 "mulsu\t$lhs, $rhs", 585 []>, 586 Requires<[SupportsMultiplication]>; 587 588 def FMUL : FFMULRdRr<0b01, 589 (outs), 590 (ins LD8lo:$lhs, LD8lo:$rhs), 591 "fmul\t$lhs, $rhs", 592 []>, 593 Requires<[SupportsMultiplication]>; 594 595 def FMULS : FFMULRdRr<0b10, 596 (outs), 597 (ins LD8lo:$lhs, LD8lo:$rhs), 598 "fmuls\t$lhs, $rhs", 599 []>, 600 Requires<[SupportsMultiplication]>; 601 602 def FMULSU : FFMULRdRr<0b11, 603 (outs), 604 (ins LD8lo:$lhs, LD8lo:$rhs), 605 "fmulsu\t$lhs, $rhs", 606 []>, 607 Requires<[SupportsMultiplication]>; 608} 609 610let Defs = [R15, R14, R13, R12, R11, R10, R9, 611 R8, R7, R6, R5, R4, R3, R2, R1, R0] in 612def DESK : FDES<(outs), 613 (ins i8imm:$k), 614 "des\t$k", 615 []>, 616 Requires<[HasDES]>; 617 618//===----------------------------------------------------------------------===// 619// Logic 620//===----------------------------------------------------------------------===// 621let Constraints = "$src = $rd", 622Defs = [SREG] in 623{ 624 // Register-Register logic instructions (which have the 625 // property of commutativity). 626 let isCommutable = 1 in 627 { 628 def ANDRdRr : FRdRr<0b0010, 629 0b00, 630 (outs GPR8:$rd), 631 (ins GPR8:$src, GPR8:$rr), 632 "and\t$rd, $rr", 633 [(set i8:$rd, (and i8:$src, i8:$rr)), 634 (implicit SREG)]>; 635 636 // ANDW Rd+1:Rd, Rr+1:Rr 637 // 638 // Expands to: 639 // and Rd, Rr 640 // and Rd+1, Rr+1 641 def ANDWRdRr : Pseudo<(outs DREGS:$rd), 642 (ins DREGS:$src, DREGS:$rr), 643 "andw\t$rd, $rr", 644 [(set i16:$rd, (and i16:$src, i16:$rr)), 645 (implicit SREG)]>; 646 647 def ORRdRr : FRdRr<0b0010, 648 0b10, 649 (outs GPR8:$rd), 650 (ins GPR8:$src, GPR8:$rr), 651 "or\t$rd, $rr", 652 [(set i8:$rd, (or i8:$src, i8:$rr)), 653 (implicit SREG)]>; 654 655 // ORW Rd+1:Rd, Rr+1:Rr 656 // 657 // Expands to: 658 // or Rd, Rr 659 // or Rd+1, Rr+1 660 def ORWRdRr : Pseudo<(outs DREGS:$rd), 661 (ins DREGS:$src, DREGS:$rr), 662 "orw\t$rd, $rr", 663 [(set i16:$rd, (or i16:$src, i16:$rr)), 664 (implicit SREG)]>; 665 666 def EORRdRr : FRdRr<0b0010, 667 0b01, 668 (outs GPR8:$rd), 669 (ins GPR8:$src, GPR8:$rr), 670 "eor\t$rd, $rr", 671 [(set i8:$rd, (xor i8:$src, i8:$rr)), 672 (implicit SREG)]>; 673 674 // EORW Rd+1:Rd, Rr+1:Rr 675 // 676 // Expands to: 677 // eor Rd, Rr 678 // eor Rd+1, Rr+1 679 def EORWRdRr : Pseudo<(outs DREGS:$rd), 680 (ins DREGS:$src, DREGS:$rr), 681 "eorw\t$rd, $rr", 682 [(set i16:$rd, (xor i16:$src, i16:$rr)), 683 (implicit SREG)]>; 684 } 685 686 def ANDIRdK : FRdK<0b0111, 687 (outs LD8:$rd), 688 (ins LD8:$src, imm_ldi8:$k), 689 "andi\t$rd, $k", 690 [(set i8:$rd, (and i8:$src, imm:$k)), 691 (implicit SREG)]>; 692 693 // ANDI Rd+1:Rd, K+1:K 694 // 695 // Expands to: 696 // andi Rd, K 697 // andi Rd+1, K+1 698 def ANDIWRdK : Pseudo<(outs DLDREGS:$rd), 699 (ins DLDREGS:$src, i16imm:$k), 700 "andiw\t$rd, $k", 701 [(set i16:$rd, (and i16:$src, imm:$k)), 702 (implicit SREG)]>; 703 704 def ORIRdK : FRdK<0b0110, 705 (outs LD8:$rd), 706 (ins LD8:$src, imm_ldi8:$k), 707 "ori\t$rd, $k", 708 [(set i8:$rd, (or i8:$src, imm:$k)), 709 (implicit SREG)]>; 710 711 // ORIW Rd+1:Rd, K+1,K 712 // 713 // Expands to: 714 // ori Rd, K 715 // ori Rd+1, K+1 716 def ORIWRdK : Pseudo<(outs DLDREGS:$rd), 717 (ins DLDREGS:$src, i16imm:$rr), 718 "oriw\t$rd, $rr", 719 [(set i16:$rd, (or i16:$src, imm:$rr)), 720 (implicit SREG)]>; 721} 722 723//===----------------------------------------------------------------------===// 724// One's/Two's Complement 725//===----------------------------------------------------------------------===// 726let Constraints = "$src = $rd", 727Defs = [SREG] in 728{ 729 def COMRd : FRd<0b1001, 730 0b0100000, 731 (outs GPR8:$rd), 732 (ins GPR8:$src), 733 "com\t$rd", 734 [(set i8:$rd, (not i8:$src)), (implicit SREG)]>; 735 736 // COMW Rd+1:Rd 737 // 738 // Expands to: 739 // com Rd 740 // com Rd+1 741 def COMWRd : Pseudo<(outs DREGS:$rd), 742 (ins DREGS:$src), 743 "comw\t$rd", 744 [(set i16:$rd, (not i16:$src)), (implicit SREG)]>; 745 746 def NEGRd : FRd<0b1001, 747 0b0100001, 748 (outs GPR8:$rd), 749 (ins GPR8:$src), 750 "neg\t$rd", 751 [(set i8:$rd, (ineg i8:$src)), (implicit SREG)]>; 752 753 // NEGW Rd+1:Rd 754 // 755 // Expands to: 756 // neg Rd+1 757 // neg Rd 758 // sbc Rd+1, r1 759 def NEGWRd : Pseudo<(outs DREGS:$rd), 760 (ins DREGS:$src), 761 "negw\t$rd", 762 [(set i16:$rd, (ineg i16:$src)), (implicit SREG)]>; 763} 764 765// TST Rd 766// Test for zero of minus. 767// This operation is identical to a `Rd AND Rd`. 768def : InstAlias<"tst\t$rd", (ANDRdRr GPR8:$rd, GPR8:$rd)>; 769 770// SBR Rd, K 771// 772// Mnemonic alias to 'ORI Rd, K'. Same bit pattern, same operands, 773// same everything. 774def : InstAlias<"sbr\t$rd, $k", 775 (ORIRdK LD8:$rd, imm_ldi8:$k), 776 /* Disable display, so we don't override ORI */ 0>; 777 778//===----------------------------------------------------------------------===// 779// Jump instructions 780//===----------------------------------------------------------------------===// 781let isBarrier = 1, 782isBranch = 1, 783isTerminator = 1 in 784{ 785 def RJMPk : FBRk<0, 786 (outs), 787 (ins brtarget_13:$target), 788 "rjmp\t$target", 789 [(br bb:$target)]>; 790 791 let isIndirectBranch = 1, 792 Uses = [R31R30] in 793 def IJMP : F16<0b1001010000001001, 794 (outs), 795 (ins), 796 "ijmp", 797 []>, 798 Requires<[HasIJMPCALL]>; 799 800 let isIndirectBranch = 1, 801 Uses = [R31R30] in 802 def EIJMP : F16<0b1001010000011001, 803 (outs), 804 (ins), 805 "eijmp", 806 []>, 807 Requires<[HasEIJMPCALL]>; 808 809 def JMPk : F32BRk<0b110, 810 (outs), 811 (ins call_target:$k), 812 "jmp\t$k", 813 []>, 814 Requires<[HasJMPCALL]>; 815} 816 817//===----------------------------------------------------------------------===// 818// Call instructions 819//===----------------------------------------------------------------------===// 820let isCall = 1 in 821{ 822 // SP is marked as a use to prevent stack-pointer assignments that appear 823 // immediately before calls from potentially appearing dead. 824 let Uses = [SP] in 825 def RCALLk : FBRk<1, 826 (outs), 827 (ins brtarget_13:$target), 828 "rcall\t$target", 829 []>; 830 831 // SP is marked as a use to prevent stack-pointer assignments that appear 832 // immediately before calls from potentially appearing dead. 833 let Uses = [SP, R31R30] in 834 def ICALL : F16<0b1001010100001001, 835 (outs), 836 (ins variable_ops), 837 "icall", 838 []>, 839 Requires<[HasIJMPCALL]>; 840 841 // SP is marked as a use to prevent stack-pointer assignments that appear 842 // immediately before calls from potentially appearing dead. 843 let Uses = [SP, R31R30] in 844 def EICALL : F16<0b1001010100011001, 845 (outs), 846 (ins variable_ops), 847 "eicall", 848 []>, 849 Requires<[HasEIJMPCALL]>; 850 851 // SP is marked as a use to prevent stack-pointer assignments that appear 852 // immediately before calls from potentially appearing dead. 853 // 854 //:TODO: the imm field can be either 16 or 22 bits in devices with more 855 // than 64k of ROM, fix it once we support the largest devices. 856 let Uses = [SP] in 857 def CALLk : F32BRk<0b111, 858 (outs), 859 (ins call_target:$k), 860 "call\t$k", 861 [(AVRcall imm:$k)]>, 862 Requires<[HasJMPCALL]>; 863} 864 865//===----------------------------------------------------------------------===// 866// Return instructions. 867//===----------------------------------------------------------------------===// 868let isTerminator = 1, 869isReturn = 1, 870isBarrier = 1 in 871{ 872 def RET : F16<0b1001010100001000, 873 (outs), 874 (ins), 875 "ret", 876 [(AVRretflag)]>; 877 878 def RETI : F16<0b1001010100011000, 879 (outs), 880 (ins), 881 "reti", 882 [(AVRretiflag)]>; 883} 884 885//===----------------------------------------------------------------------===// 886// Compare operations. 887//===----------------------------------------------------------------------===// 888let Defs = [SREG] in 889{ 890 // CPSE Rd, Rr 891 // Compare Rd and Rr, skipping the next instruction if they are equal. 892 let isBarrier = 1, 893 isBranch = 1, 894 isTerminator = 1 in 895 def CPSE : FRdRr<0b0001, 896 0b00, 897 (outs), 898 (ins GPR8:$rd, GPR8:$rr), 899 "cpse\t$rd, $rr", 900 []>; 901 902 def CPRdRr : FRdRr<0b0001, 903 0b01, 904 (outs), 905 (ins GPR8:$rd, GPR8:$rr), 906 "cp\t$rd, $rr", 907 [(AVRcmp i8:$rd, i8:$rr), (implicit SREG)]>; 908 909 // CPW Rd+1:Rd, Rr+1:Rr 910 // 911 // Expands to: 912 // cp Rd, Rr 913 // cpc Rd+1, Rr+1 914 def CPWRdRr : Pseudo<(outs), 915 (ins DREGS:$src, DREGS:$src2), 916 "cpw\t$src, $src2", 917 [(AVRcmp i16:$src, i16:$src2), (implicit SREG)]>; 918 919 let Uses = [SREG] in 920 def CPCRdRr : FRdRr<0b0000, 921 0b01, 922 (outs), 923 (ins GPR8:$rd, GPR8:$rr), 924 "cpc\t$rd, $rr", 925 [(AVRcmpc i8:$rd, i8:$rr), (implicit SREG)]>; 926 927 // CPCW Rd+1:Rd. Rr+1:Rr 928 // 929 // Expands to: 930 // cpc Rd, Rr 931 // cpc Rd+1, Rr+1 932 let Uses = [SREG] in 933 def CPCWRdRr : Pseudo<(outs), 934 (ins DREGS:$src, DREGS:$src2), 935 "cpcw\t$src, $src2", 936 [(AVRcmpc i16:$src, i16:$src2), (implicit SREG)]>; 937 938 // CPI Rd, K 939 // Compares a register with an 8 bit immediate. 940 def CPIRdK : FRdK<0b0011, 941 (outs), 942 (ins LD8:$rd, imm_ldi8:$k), 943 "cpi\t$rd, $k", 944 [(AVRcmp i8:$rd, imm:$k), (implicit SREG)]>; 945} 946 947//===----------------------------------------------------------------------===// 948// Register conditional skipping/branching operations. 949//===----------------------------------------------------------------------===// 950let isBranch = 1, 951isTerminator = 1 in 952{ 953 // Conditional skipping on GPR register bits, and 954 // conditional skipping on IO register bits. 955 let isBarrier = 1 in 956 { 957 def SBRCRrB : FRdB<0b10, 958 (outs), 959 (ins GPR8:$rr, i8imm:$b), 960 "sbrc\t$rr, $b", 961 []>; 962 963 def SBRSRrB : FRdB<0b11, 964 (outs), 965 (ins GPR8:$rr, i8imm:$b), 966 "sbrs\t$rr, $b", 967 []>; 968 969 def SBICAb : FIOBIT<0b01, 970 (outs), 971 (ins imm_port5:$a, i8imm:$b), 972 "sbic\t$a, $b", 973 []>; 974 975 def SBISAb : FIOBIT<0b11, 976 (outs), 977 (ins imm_port5:$a, i8imm:$b), 978 "sbis\t$a, $b", 979 []>; 980 } 981 982 // Relative branches on status flag bits. 983 let Uses = [SREG] in 984 { 985 // BRBS s, k 986 // Branch if `s` flag in status register is set. 987 def BRBSsk : FSK<0, 988 (outs), 989 (ins i8imm:$s, relbrtarget_7:$k), 990 "brbs\t$s, $k", 991 []>; 992 993 // BRBC s, k 994 // Branch if `s` flag in status register is clear. 995 def BRBCsk : FSK<1, 996 (outs), 997 (ins i8imm:$s, relbrtarget_7:$k), 998 "brbc\t$s, $k", 999 []>; 1000 } 1001} 1002 1003 1004// BRCS k 1005// Branch if carry flag is set 1006def : InstAlias<"brcs\t$k", (BRBSsk 0, relbrtarget_7:$k)>; 1007 1008// BRCC k 1009// Branch if carry flag is clear 1010def : InstAlias<"brcc\t$k", (BRBCsk 0, relbrtarget_7:$k)>; 1011 1012// BRHS k 1013// Branch if half carry flag is set 1014def : InstAlias<"brhs\t$k", (BRBSsk 5, relbrtarget_7:$k)>; 1015 1016// BRHC k 1017// Branch if half carry flag is clear 1018def : InstAlias<"brhc\t$k", (BRBCsk 5, relbrtarget_7:$k)>; 1019 1020// BRTS k 1021// Branch if the T flag is set 1022def : InstAlias<"brts\t$k", (BRBSsk 6, relbrtarget_7:$k)>; 1023 1024// BRTC k 1025// Branch if the T flag is clear 1026def : InstAlias<"brtc\t$k", (BRBCsk 6, relbrtarget_7:$k)>; 1027 1028// BRVS k 1029// Branch if the overflow flag is set 1030def : InstAlias<"brvs\t$k", (BRBSsk 3, relbrtarget_7:$k)>; 1031 1032// BRVC k 1033// Branch if the overflow flag is clear 1034def : InstAlias<"brvc\t$k", (BRBCsk 3, relbrtarget_7:$k)>; 1035 1036// BRIE k 1037// Branch if the global interrupt flag is enabled 1038def : InstAlias<"brie\t$k", (BRBSsk 7, relbrtarget_7:$k)>; 1039 1040// BRID k 1041// Branch if the global interrupt flag is disabled 1042def : InstAlias<"brid\t$k", (BRBCsk 7, relbrtarget_7:$k)>; 1043 1044//===----------------------------------------------------------------------===// 1045// PC-relative conditional branches 1046//===----------------------------------------------------------------------===// 1047// Based on status register. We cannot simplify these into instruction aliases 1048// because we also need to be able to specify a pattern to match for ISel. 1049let isBranch = 1, 1050isTerminator = 1, 1051Uses = [SREG] in 1052{ 1053 def BREQk : FBRsk<0, 1054 0b001, 1055 (outs), 1056 (ins relbrtarget_7:$target), 1057 "breq\t$target", 1058 [(AVRbrcond bb:$target, AVR_COND_EQ)]>; 1059 1060 def BRNEk : FBRsk<1, 1061 0b001, 1062 (outs), 1063 (ins relbrtarget_7:$target), 1064 "brne\t$target", 1065 [(AVRbrcond bb:$target, AVR_COND_NE)]>; 1066 1067 1068 def BRSHk : FBRsk<1, 1069 0b000, 1070 (outs), 1071 (ins relbrtarget_7:$target), 1072 "brsh\t$target", 1073 [(AVRbrcond bb:$target, AVR_COND_SH)]>; 1074 1075 def BRLOk : FBRsk<0, 1076 0b000, 1077 (outs), 1078 (ins relbrtarget_7:$target), 1079 "brlo\t$target", 1080 [(AVRbrcond bb:$target, AVR_COND_LO)]>; 1081 1082 def BRMIk : FBRsk<0, 1083 0b010, 1084 (outs), 1085 (ins relbrtarget_7:$target), 1086 "brmi\t$target", 1087 [(AVRbrcond bb:$target, AVR_COND_MI)]>; 1088 1089 def BRPLk : FBRsk<1, 1090 0b010, 1091 (outs), 1092 (ins relbrtarget_7:$target), 1093 "brpl\t$target", 1094 [(AVRbrcond bb:$target, AVR_COND_PL)]>; 1095 1096 def BRGEk : FBRsk<1, 1097 0b100, 1098 (outs), 1099 (ins relbrtarget_7:$target), 1100 "brge\t$target", 1101 [(AVRbrcond bb:$target, AVR_COND_GE)]>; 1102 1103 def BRLTk : FBRsk<0, 1104 0b100, 1105 (outs), 1106 (ins relbrtarget_7:$target), 1107 "brlt\t$target", 1108 [(AVRbrcond bb:$target, AVR_COND_LT)]>; 1109} 1110 1111//===----------------------------------------------------------------------===// 1112// Data transfer instructions 1113//===----------------------------------------------------------------------===// 1114// 8 and 16-bit register move instructions. 1115let hasSideEffects = 0 in 1116{ 1117 def MOVRdRr : FRdRr<0b0010, 1118 0b11, 1119 (outs GPR8:$rd), 1120 (ins GPR8:$rr), 1121 "mov\t$rd, $rr", 1122 []>; 1123 1124 def MOVWRdRr : FMOVWRdRr<(outs DREGS:$dst), 1125 (ins DREGS:$src), 1126 "movw\t$dst, $src", 1127 []>, 1128 Requires<[HasMOVW]>; 1129} 1130 1131// Load immediate values into registers. 1132let isReMaterializable = 1 in 1133{ 1134 def LDIRdK : FRdK<0b1110, 1135 (outs LD8:$rd), 1136 (ins imm_ldi8:$k), 1137 "ldi\t$rd, $k", 1138 [(set i8:$rd, imm:$k)]>; 1139 1140 // LDIW Rd+1:Rd, K+1:K 1141 // 1142 // Expands to: 1143 // ldi Rd, K 1144 // ldi Rd+1, K+1 1145 def LDIWRdK : Pseudo<(outs DLDREGS:$dst), 1146 (ins i16imm:$src), 1147 "ldiw\t$dst, $src", 1148 [(set i16:$dst, imm:$src)]>; 1149} 1150 1151// Load from data space into register. 1152let canFoldAsLoad = 1, 1153isReMaterializable = 1 in 1154{ 1155 def LDSRdK : F32DM<0b0, 1156 (outs GPR8:$rd), 1157 (ins imm16:$k), 1158 "lds\t$rd, $k", 1159 [(set i8:$rd, (load imm:$k))]>, 1160 Requires<[HasSRAM]>; 1161 1162 // LDSW Rd+1:Rd, K+1:K 1163 // 1164 // Expands to: 1165 // lds Rd, (K+1:K) 1166 // lds Rd+1 (K+1:K) + 1 1167 def LDSWRdK : Pseudo<(outs DREGS:$dst), 1168 (ins i16imm:$src), 1169 "ldsw\t$dst, $src", 1170 [(set i16:$dst, (load imm:$src))]>, 1171 Requires<[HasSRAM]>; 1172} 1173 1174// Indirect loads. 1175let canFoldAsLoad = 1, 1176isReMaterializable = 1 in 1177{ 1178 def LDRdPtr : FSTLD<0, 1179 0b00, 1180 (outs GPR8:$reg), 1181 (ins LDSTPtrReg:$ptrreg), 1182 "ld\t$reg, $ptrreg", 1183 [(set GPR8:$reg, (load i16:$ptrreg))]>, 1184 Requires<[HasSRAM]>; 1185 1186 // LDW Rd+1:Rd, P 1187 // 1188 // Expands to: 1189 // ld Rd, P 1190 // ldd Rd+1, P+1 1191 let Constraints = "@earlyclobber $reg" in 1192 def LDWRdPtr : Pseudo<(outs DREGS:$reg), 1193 (ins PTRDISPREGS:$ptrreg), 1194 "ldw\t$reg, $ptrreg", 1195 [(set i16:$reg, (load i16:$ptrreg))]>, 1196 Requires<[HasSRAM]>; 1197} 1198 1199// Indirect loads (with postincrement or predecrement). 1200let mayLoad = 1, 1201hasSideEffects = 0, 1202Constraints = "$ptrreg = $base_wb,@earlyclobber $reg" in 1203{ 1204 def LDRdPtrPi : FSTLD<0, 1205 0b01, 1206 (outs GPR8:$reg, PTRREGS:$base_wb), 1207 (ins LDSTPtrReg:$ptrreg), 1208 "ld\t$reg, $ptrreg+", 1209 []>, 1210 Requires<[HasSRAM]>; 1211 1212 // LDW Rd+1:Rd, P+ 1213 // Expands to: 1214 // ld Rd, P+ 1215 // ld Rd+1, P+ 1216 def LDWRdPtrPi : Pseudo<(outs DREGS:$reg, PTRREGS:$base_wb), 1217 (ins PTRREGS:$ptrreg), 1218 "ldw\t$reg, $ptrreg+", 1219 []>, 1220 Requires<[HasSRAM]>; 1221 1222 def LDRdPtrPd : FSTLD<0, 1223 0b10, 1224 (outs GPR8:$reg, PTRREGS:$base_wb), 1225 (ins LDSTPtrReg:$ptrreg), 1226 "ld\t$reg, -$ptrreg", 1227 []>, 1228 Requires<[HasSRAM]>; 1229 1230 // LDW Rd+1:Rd, -P 1231 // 1232 // Expands to: 1233 // ld Rd+1, -P 1234 // ld Rd, -P 1235 def LDWRdPtrPd : Pseudo<(outs DREGS:$reg, PTRREGS:$base_wb), 1236 (ins PTRREGS:$ptrreg), 1237 "ldw\t$reg, -$ptrreg", 1238 []>, 1239 Requires<[HasSRAM]>; 1240} 1241 1242// Load indirect with displacement operations. 1243let canFoldAsLoad = 1, 1244isReMaterializable = 1 in 1245{ 1246 let Constraints = "@earlyclobber $reg" in 1247 def LDDRdPtrQ : FSTDLDD<0, 1248 (outs GPR8:$reg), 1249 (ins memri:$memri), 1250 "ldd\t$reg, $memri", 1251 [(set i8:$reg, (load addr:$memri))]>, 1252 Requires<[HasSRAM]>; 1253 1254 // LDDW Rd+1:Rd, P+q 1255 // 1256 // Expands to: 1257 // ldd Rd, P+q 1258 // ldd Rd+1, P+q+1 1259 let Constraints = "@earlyclobber $dst" in 1260 def LDDWRdPtrQ : Pseudo<(outs DREGS_WITHOUT_YZ_WORKAROUND:$dst), 1261 (ins memri:$memri), 1262 "lddw\t$dst, $memri", 1263 [(set i16:$dst, (load addr:$memri))]>, 1264 Requires<[HasSRAM]>; 1265 1266 // An identical pseudo instruction to LDDWRdPtrQ, expect restricted to the Y 1267 // register and without the @earlyclobber flag. 1268 // 1269 // Used to work around a bug caused by the register allocator not 1270 // being able to handle the expansion of a COPY into an machine instruction 1271 // that has an earlyclobber flag. This is because the register allocator will 1272 // try expand a copy from a register slot into an earlyclobber instruction. 1273 // Instructions that are earlyclobber need to be in a dedicated earlyclobber slot. 1274 // 1275 // This pseudo instruction can be used pre-AVR pseudo expansion in order to 1276 // get a frame index load without directly using earlyclobber instructions. 1277 // 1278 // The pseudo expansion pass trivially expands this into LDDWRdPtrQ. 1279 // 1280 // This instruction may be removed once PR13375 is fixed. 1281 let mayLoad = 1, 1282 hasSideEffects = 0 in 1283 def LDDWRdYQ : Pseudo<(outs DREGS:$dst), 1284 (ins memri:$memri), 1285 "lddw\t$dst, $memri", 1286 []>, 1287 Requires<[HasSRAM]>; 1288} 1289 1290class AtomicLoad<PatFrag Op, RegisterClass DRC, 1291 RegisterClass PTRRC> : 1292 Pseudo<(outs DRC:$rd), (ins PTRRC:$rr), "atomic_op", 1293 [(set DRC:$rd, (Op i16:$rr))]>; 1294 1295class AtomicStore<PatFrag Op, RegisterClass DRC, 1296 RegisterClass PTRRC> : 1297 Pseudo<(outs), (ins PTRRC:$rd, DRC:$rr), "atomic_op", 1298 [(Op i16:$rd, DRC:$rr)]>; 1299 1300let Constraints = "@earlyclobber $rd" in 1301class AtomicLoadOp<PatFrag Op, RegisterClass DRC, 1302 RegisterClass PTRRC> : 1303 Pseudo<(outs DRC:$rd), (ins PTRRC:$rr, DRC:$operand), 1304 "atomic_op", 1305 [(set DRC:$rd, (Op i16:$rr, DRC:$operand))]>; 1306 1307// FIXME: I think 16-bit atomic binary ops need to mark 1308// r0 as clobbered. 1309 1310// Atomic instructions 1311// =================== 1312// 1313// These are all expanded by AVRExpandPseudoInsts 1314// 1315// 8-bit operations can use any pointer register because 1316// they are expanded directly into an LD/ST instruction. 1317// 1318// 16-bit operations use 16-bit load/store postincrement instructions, 1319// which require PTRDISPREGS. 1320 1321def AtomicLoad8 : AtomicLoad<atomic_load_8, GPR8, PTRREGS>; 1322def AtomicLoad16 : AtomicLoad<atomic_load_16, DREGS, PTRDISPREGS>; 1323 1324def AtomicStore8 : AtomicStore<atomic_store_8, GPR8, PTRREGS>; 1325def AtomicStore16 : AtomicStore<atomic_store_16, DREGS, PTRDISPREGS>; 1326 1327class AtomicLoadOp8<PatFrag Op> : AtomicLoadOp<Op, GPR8, PTRREGS>; 1328class AtomicLoadOp16<PatFrag Op> : AtomicLoadOp<Op, DREGS, PTRDISPREGS>; 1329 1330def AtomicLoadAdd8 : AtomicLoadOp8<atomic_load_add_8>; 1331def AtomicLoadAdd16 : AtomicLoadOp16<atomic_load_add_16>; 1332def AtomicLoadSub8 : AtomicLoadOp8<atomic_load_sub_8>; 1333def AtomicLoadSub16 : AtomicLoadOp16<atomic_load_sub_16>; 1334def AtomicLoadAnd8 : AtomicLoadOp8<atomic_load_and_8>; 1335def AtomicLoadAnd16 : AtomicLoadOp16<atomic_load_and_16>; 1336def AtomicLoadOr8 : AtomicLoadOp8<atomic_load_or_8>; 1337def AtomicLoadOr16 : AtomicLoadOp16<atomic_load_or_16>; 1338def AtomicLoadXor8 : AtomicLoadOp8<atomic_load_xor_8>; 1339def AtomicLoadXor16 : AtomicLoadOp16<atomic_load_xor_16>; 1340def AtomicFence : Pseudo<(outs), (ins), "atomic_fence", 1341 [(atomic_fence timm, timm)]>; 1342 1343// Indirect store from register to data space. 1344def STSKRr : F32DM<0b1, 1345 (outs), 1346 (ins imm16:$k, GPR8:$rd), 1347 "sts\t$k, $rd", 1348 [(store i8:$rd, imm:$k)]>, 1349 Requires<[HasSRAM]>; 1350 1351// STSW K+1:K, Rr+1:Rr 1352// 1353// Expands to: 1354// sts Rr+1, (K+1:K) + 1 1355// sts Rr, (K+1:K) 1356def STSWKRr : Pseudo<(outs), 1357 (ins i16imm:$dst, DREGS:$src), 1358 "stsw\t$dst, $src", 1359 [(store i16:$src, imm:$dst)]>, 1360 Requires<[HasSRAM]>; 1361 1362// Indirect stores. 1363// ST P, Rr 1364// Stores the value of Rr into the location addressed by pointer P. 1365def STPtrRr : FSTLD<1, 1366 0b00, 1367 (outs), 1368 (ins LDSTPtrReg:$ptrreg, GPR8:$reg), 1369 "st\t$ptrreg, $reg", 1370 [(store GPR8:$reg, i16:$ptrreg)]>, 1371 Requires<[HasSRAM]>; 1372 1373// STW P, Rr+1:Rr 1374// Stores the value of Rr into the location addressed by pointer P. 1375// 1376// Expands to: 1377// st P, Rr 1378// std P+1, Rr+1 1379def STWPtrRr : Pseudo<(outs), 1380 (ins PTRDISPREGS:$ptrreg, DREGS:$reg), 1381 "stw\t$ptrreg, $reg", 1382 [(store i16:$reg, i16:$ptrreg)]>, 1383 Requires<[HasSRAM]>; 1384 1385// Indirect stores (with postincrement or predecrement). 1386let Constraints = "$ptrreg = $base_wb,@earlyclobber $base_wb" in 1387{ 1388 1389 // ST P+, Rr 1390 // Stores the value of Rr into the location addressed by pointer P. 1391 // Post increments P. 1392 def STPtrPiRr : FSTLD<1, 1393 0b01, 1394 (outs LDSTPtrReg:$base_wb), 1395 (ins LDSTPtrReg:$ptrreg, GPR8:$reg, i8imm:$offs), 1396 "st\t$ptrreg+, $reg", 1397 [(set i16:$base_wb, 1398 (post_store GPR8:$reg, i16:$ptrreg, imm:$offs))]>, 1399 Requires<[HasSRAM]>; 1400 1401 // STW P+, Rr+1:Rr 1402 // Stores the value of Rr into the location addressed by pointer P. 1403 // Post increments P. 1404 // 1405 // Expands to: 1406 // st P+, Rr 1407 // st P+, Rr+1 1408 def STWPtrPiRr : Pseudo<(outs PTRREGS:$base_wb), 1409 (ins PTRREGS:$ptrreg, DREGS:$trh, i8imm:$offs), 1410 "stw\t$ptrreg+, $trh", 1411 [(set PTRREGS:$base_wb, 1412 (post_store DREGS:$trh, PTRREGS:$ptrreg, imm:$offs))]>, 1413 Requires<[HasSRAM]>; 1414 1415 // ST -P, Rr 1416 // Stores the value of Rr into the location addressed by pointer P. 1417 // Pre decrements P. 1418 def STPtrPdRr : FSTLD<1, 1419 0b10, 1420 (outs LDSTPtrReg:$base_wb), 1421 (ins LDSTPtrReg:$ptrreg, GPR8:$reg, i8imm:$offs), 1422 "st\t-$ptrreg, $reg", 1423 [(set i16:$base_wb, 1424 (pre_store GPR8:$reg, i16:$ptrreg, imm:$offs))]>, 1425 Requires<[HasSRAM]>; 1426 1427 // STW -P, Rr+1:Rr 1428 // Stores the value of Rr into the location addressed by pointer P. 1429 // Pre decrements P. 1430 // 1431 // Expands to: 1432 // st -P, Rr+1 1433 // st -P, Rr 1434 def STWPtrPdRr : Pseudo<(outs PTRREGS:$base_wb), 1435 (ins PTRREGS:$ptrreg, DREGS:$reg, i8imm:$offs), 1436 "stw\t-$ptrreg, $reg", 1437 [(set PTRREGS:$base_wb, 1438 (pre_store i16:$reg, i16:$ptrreg, imm:$offs))]>, 1439 Requires<[HasSRAM]>; 1440} 1441 1442// Store indirect with displacement operations. 1443// STD P+q, Rr 1444// Stores the value of Rr into the location addressed by pointer P with a 1445// displacement of q. Does not modify P. 1446def STDPtrQRr : FSTDLDD<1, 1447 (outs), 1448 (ins memri:$memri, GPR8:$reg), 1449 "std\t$memri, $reg", 1450 [(store i8:$reg, addr:$memri)]>, 1451 Requires<[HasSRAM]>; 1452 1453// STDW P+q, Rr+1:Rr 1454// Stores the value of Rr into the location addressed by pointer P with a 1455// displacement of q. Does not modify P. 1456// 1457// Expands to: 1458// std P+q, Rr 1459// std P+q+1, Rr+1 1460def STDWPtrQRr : Pseudo<(outs), 1461 (ins memri:$memri, DREGS:$src), 1462 "stdw\t$memri, $src", 1463 [(store i16:$src, addr:$memri)]>, 1464 Requires<[HasSRAM]>; 1465 1466 1467// Load program memory operations. 1468let canFoldAsLoad = 1, 1469isReMaterializable = 1, 1470mayLoad = 1, 1471hasSideEffects = 0 in 1472{ 1473 let Defs = [R0], 1474 Uses = [R31R30] in 1475 def LPM : F16<0b1001010111001000, 1476 (outs), 1477 (ins), 1478 "lpm", 1479 []>, 1480 Requires<[HasLPM]>; 1481 1482 def LPMRdZ : FLPMX<0, 1483 0, 1484 (outs GPR8:$dst), 1485 (ins ZREG:$z), 1486 "lpm\t$dst, $z", 1487 []>, 1488 Requires<[HasLPMX]>; 1489 1490 // Load program memory, while postincrementing the Z register. 1491 let Defs = [R31R30] in 1492 { 1493 def LPMRdZPi : FLPMX<0, 1494 1, 1495 (outs GPR8:$dst), 1496 (ins ZREG:$z), 1497 "lpm\t$dst, $z+", 1498 []>, 1499 Requires<[HasLPMX]>; 1500 1501 def LPMWRdZ : Pseudo<(outs DREGS:$dst), 1502 (ins ZREG:$z), 1503 "lpmw\t$dst, $z", 1504 []>, 1505 Requires<[HasLPMX]>; 1506 1507 def LPMWRdZPi : Pseudo<(outs DREGS:$dst), 1508 (ins ZREG:$z), 1509 "lpmw\t$dst, $z+", 1510 []>, 1511 Requires<[HasLPMX]>; 1512 } 1513} 1514 1515// Extended load program memory operations. 1516let mayLoad = 1, 1517hasSideEffects = 0 in 1518{ 1519 let Defs = [R0], 1520 Uses = [R31R30] in 1521 def ELPM : F16<0b1001010111011000, 1522 (outs), 1523 (ins), 1524 "elpm", 1525 []>, 1526 Requires<[HasELPM]>; 1527 1528 def ELPMRdZ : FLPMX<1, 1529 0, 1530 (outs GPR8:$dst), 1531 (ins ZREG:$z), 1532 "elpm\t$dst, $z", 1533 []>, 1534 Requires<[HasELPMX]>; 1535 1536 let Defs = [R31R30] in 1537 def ELPMRdZPi : FLPMX<1, 1538 1, 1539 (outs GPR8:$dst), 1540 (ins ZREG: $z), 1541 "elpm\t$dst, $z+", 1542 []>, 1543 Requires<[HasELPMX]>; 1544} 1545 1546// Store program memory operations. 1547let Uses = [R1, R0] in 1548{ 1549 let Uses = [R31R30, R1, R0] in 1550 def SPM : F16<0b1001010111101000, 1551 (outs), 1552 (ins), 1553 "spm", 1554 []>, 1555 Requires<[HasSPM]>; 1556 1557 let Defs = [R31R30] in 1558 def SPMZPi : F16<0b1001010111111000, 1559 (outs), 1560 (ins ZREG:$z), 1561 "spm $z+", 1562 []>, 1563 Requires<[HasSPMX]>; 1564} 1565 1566// Read data from IO location operations. 1567let canFoldAsLoad = 1, 1568isReMaterializable = 1 in 1569{ 1570 def INRdA : FIORdA<(outs GPR8:$dst), 1571 (ins imm_port6:$src), 1572 "in\t$dst, $src", 1573 [(set i8:$dst, (load ioaddr8:$src))]>; 1574 1575 def INWRdA : Pseudo<(outs DREGS:$dst), 1576 (ins imm_port6:$src), 1577 "inw\t$dst, $src", 1578 [(set i16:$dst, (load ioaddr16:$src))]>; 1579} 1580 1581// Write data to IO location operations. 1582def OUTARr : FIOARr<(outs), 1583 (ins imm_port6:$dst, GPR8:$src), 1584 "out\t$dst, $src", 1585 [(store i8:$src, ioaddr8:$dst)]>; 1586 1587def OUTWARr : Pseudo<(outs), 1588 (ins imm_port6:$dst, DREGS:$src), 1589 "outw\t$dst, $src", 1590 [(store i16:$src, ioaddr16:$dst)]>; 1591 1592// Stack push/pop operations. 1593let Defs = [SP], 1594Uses = [SP], 1595hasSideEffects = 0 in 1596{ 1597 // Stack push operations. 1598 let mayStore = 1 in 1599 { 1600 def PUSHRr : FRd<0b1001, 1601 0b0011111, 1602 (outs), 1603 (ins GPR8:$reg), 1604 "push\t$reg", 1605 []>, 1606 Requires<[HasSRAM]>; 1607 1608 def PUSHWRr : Pseudo<(outs), 1609 (ins DREGS:$reg), 1610 "pushw\t$reg", 1611 []>, 1612 Requires<[HasSRAM]>; 1613 } 1614 1615 // Stack pop operations. 1616 let mayLoad = 1 in 1617 { 1618 def POPRd : FRd<0b1001, 1619 0b0001111, 1620 (outs GPR8:$reg), 1621 (ins), 1622 "pop\t$reg", 1623 []>, 1624 Requires<[HasSRAM]>; 1625 1626 def POPWRd : Pseudo<(outs DREGS:$reg), 1627 (ins), 1628 "popw\t$reg", 1629 []>, 1630 Requires<[HasSRAM]>; 1631 } 1632} 1633 1634// Read-Write-Modify (RMW) instructions. 1635def XCHZRd : FZRd<0b100, 1636 (outs GPR8:$rd), 1637 (ins ZREG:$z), 1638 "xch\t$z, $rd", 1639 []>, 1640 Requires<[SupportsRMW]>; 1641 1642def LASZRd : FZRd<0b101, 1643 (outs GPR8:$rd), 1644 (ins ZREG:$z), 1645 "las\t$z, $rd", 1646 []>, 1647 Requires<[SupportsRMW]>; 1648 1649def LACZRd : FZRd<0b110, 1650 (outs GPR8:$rd), 1651 (ins ZREG:$z), 1652 "lac\t$z, $rd", 1653 []>, 1654 Requires<[SupportsRMW]>; 1655 1656def LATZRd : FZRd<0b111, 1657 (outs GPR8:$rd), 1658 (ins ZREG:$z), 1659 "lat\t$z, $rd", 1660 []>, 1661 Requires<[SupportsRMW]>; 1662 1663//===----------------------------------------------------------------------===// 1664// Bit and bit-test instructions 1665//===----------------------------------------------------------------------===// 1666 1667// Bit shift/rotate operations. 1668let Constraints = "$src = $rd", 1669Defs = [SREG] in 1670{ 1671 // 8-bit LSL is an alias of ADD Rd, Rd 1672 1673 def LSLWRd : Pseudo<(outs DREGS:$rd), 1674 (ins DREGS:$src), 1675 "lslw\t$rd", 1676 [(set i16:$rd, (AVRlsl i16:$src)), (implicit SREG)]>; 1677 1678 def LSLWNRd : Pseudo<(outs DLDREGS:$rd), 1679 (ins DREGS:$src, imm16:$bits), 1680 "lslwn\t$rd, $bits", 1681 [(set i16:$rd, (AVRlslwn i16:$src, imm:$bits)), 1682 (implicit SREG)]>; 1683 1684 def LSLBNRd : Pseudo<(outs LD8:$rd), 1685 (ins GPR8:$src, imm_ldi8:$bits), 1686 "lslbn\t$rd, $bits", 1687 [(set i8:$rd, (AVRlslbn i8:$src, imm:$bits)), 1688 (implicit SREG)]>; 1689 1690 def LSRRd : FRd<0b1001, 1691 0b0100110, 1692 (outs GPR8:$rd), 1693 (ins GPR8:$src), 1694 "lsr\t$rd", 1695 [(set i8:$rd, (AVRlsr i8:$src)), (implicit SREG)]>; 1696 1697 def LSRWRd : Pseudo<(outs DREGS:$rd), 1698 (ins DREGS:$src), 1699 "lsrw\t$rd", 1700 [(set i16:$rd, (AVRlsr i16:$src)), (implicit SREG)]>; 1701 1702 def LSRWNRd : Pseudo<(outs DLDREGS:$rd), 1703 (ins DREGS:$src, imm16:$bits), 1704 "lsrwn\t$rd, $bits", 1705 [(set i16:$rd, (AVRlsrwn i16:$src, imm:$bits)), 1706 (implicit SREG)]>; 1707 1708 def LSRBNRd : Pseudo<(outs LD8:$rd), 1709 (ins GPR8:$src, imm_ldi8:$bits), 1710 "lsrbn\t$rd, $bits", 1711 [(set i8:$rd, (AVRlsrbn i8:$src, imm:$bits)), 1712 (implicit SREG)]>; 1713 1714 def ASRRd : FRd<0b1001, 1715 0b0100101, 1716 (outs GPR8:$rd), 1717 (ins GPR8:$src), 1718 "asr\t$rd", 1719 [(set i8:$rd, (AVRasr i8:$src)), (implicit SREG)]>; 1720 1721 def ASRWNRd : Pseudo<(outs DLDREGS:$rd), 1722 (ins DREGS:$src, imm16:$bits), 1723 "asrwn\t$rd, $bits", 1724 [(set i16:$rd, (AVRasrwn i16:$src, imm:$bits)), 1725 (implicit SREG)]>; 1726 1727 def ASRBNRd : Pseudo<(outs LD8:$rd), 1728 (ins GPR8:$src, imm_ldi8:$bits), 1729 "asrbn\t$rd, $bits", 1730 [(set i8:$rd, (AVRasrbn i8:$src, imm:$bits)), 1731 (implicit SREG)]>; 1732 1733 def ASRWRd : Pseudo<(outs DREGS:$rd), 1734 (ins DREGS:$src), 1735 "asrw\t$rd", 1736 [(set i16:$rd, (AVRasr i16:$src)), (implicit SREG)]>; 1737 1738 def ROLBRd : Pseudo<(outs GPR8:$rd), 1739 (ins GPR8:$src), 1740 "rolb\t$rd", 1741 [(set i8:$rd, (AVRrol i8:$src)), (implicit SREG)]>; 1742 1743 def RORBRd : Pseudo<(outs GPR8:$rd), 1744 (ins GPR8:$src), 1745 "rorb\t$rd", 1746 [(set i8:$rd, (AVRror i8:$src)), (implicit SREG)]>; 1747 1748 // Bit rotate operations. 1749 let Uses = [SREG] in 1750 { 1751 1752 def ROLWRd : Pseudo<(outs DREGS:$rd), 1753 (ins DREGS:$src), 1754 "rolw\t$rd", 1755 [(set i16:$rd, (AVRrol i16:$src)), (implicit SREG)]>; 1756 1757 def RORRd : FRd<0b1001, 1758 0b0100111, 1759 (outs GPR8:$rd), 1760 (ins GPR8:$src), 1761 "ror\t$rd", 1762 []>; 1763 1764 def RORWRd : Pseudo<(outs DREGS:$rd), 1765 (ins DREGS:$src), 1766 "rorw\t$rd", 1767 [(set i16:$rd, (AVRror i16:$src)), (implicit SREG)]>; 1768 } 1769} 1770 1771// SWAP Rd 1772// Swaps the high and low nibbles in a register. 1773let Constraints = "$src = $rd" in 1774def SWAPRd : FRd<0b1001, 1775 0b0100010, 1776 (outs GPR8:$rd), 1777 (ins GPR8:$src), 1778 "swap\t$rd", 1779 [(set i8:$rd, (AVRSwap i8:$src))]>; 1780 1781// IO register bit set/clear operations. 1782//:TODO: add patterns when popcount(imm)==2 to be expanded with 2 sbi/cbi 1783// instead of in+ori+out which requires one more instr. 1784def SBIAb : FIOBIT<0b10, 1785 (outs), 1786 (ins imm_port5:$addr, i8imm:$bit), 1787 "sbi\t$addr, $bit", 1788 [(store (or (i8 (load lowioaddr8:$addr)), iobitpos8:$bit), 1789 lowioaddr8:$addr)]>; 1790 1791def CBIAb : FIOBIT<0b00, 1792 (outs), 1793 (ins imm_port5:$addr, i8imm:$bit), 1794 "cbi\t$addr, $bit", 1795 [(store (and (i8 (load lowioaddr8:$addr)), iobitposn8:$bit), 1796 lowioaddr8:$addr)]>; 1797 1798// Status register bit load/store operations. 1799let Defs = [SREG] in 1800def BST : FRdB<0b01, 1801 (outs), 1802 (ins GPR8:$rd, i8imm:$b), 1803 "bst\t$rd, $b", 1804 []>; 1805 1806let Constraints = "$src = $rd", 1807Uses = [SREG] in 1808def BLD : FRdB<0b00, 1809 (outs GPR8:$rd), 1810 (ins GPR8:$src, i8imm:$b), 1811 "bld\t$rd, $b", 1812 []>; 1813 1814def CBR : InstAlias<"cbr\t$rd, $k", (ANDIRdK LD8:$rd, imm_com8:$k), 0>; 1815 1816// CLR Rd 1817// Alias for EOR Rd, Rd 1818// ------------- 1819// Clears all bits in a register. 1820def CLR : InstAlias<"clr\t$rd", (EORRdRr GPR8:$rd, GPR8:$rd)>; 1821 1822// LSL Rd 1823// Alias for ADD Rd, Rd 1824// -------------- 1825// Logical shift left one bit. 1826def LSL : InstAlias<"lsl\t$rd", (ADDRdRr GPR8:$rd, GPR8:$rd)>; 1827 1828def ROL : InstAlias<"rol\t$rd", (ADCRdRr GPR8:$rd, GPR8:$rd)>; 1829 1830// SER Rd 1831// Alias for LDI Rd, 0xff 1832// --------- 1833// Sets all bits in a register. 1834def : InstAlias<"ser\t$rd", (LDIRdK LD8:$rd, 0xff), 0>; 1835 1836let Defs = [SREG] in 1837def BSETs : FS<0, 1838 (outs), 1839 (ins i8imm:$s), 1840 "bset\t$s", 1841 []>; 1842 1843let Defs = [SREG] in 1844def BCLRs : FS<1, 1845 (outs), 1846 (ins i8imm:$s), 1847 "bclr\t$s", 1848 []>; 1849 1850// Set/clear aliases for the carry (C) status flag (bit 0). 1851def : InstAlias<"sec", (BSETs 0)>; 1852def : InstAlias<"clc", (BCLRs 0)>; 1853 1854// Set/clear aliases for the zero (Z) status flag (bit 1). 1855def : InstAlias<"sez", (BSETs 1)>; 1856def : InstAlias<"clz", (BCLRs 1)>; 1857 1858// Set/clear aliases for the negative (N) status flag (bit 2). 1859def : InstAlias<"sen", (BSETs 2)>; 1860def : InstAlias<"cln", (BCLRs 2)>; 1861 1862// Set/clear aliases for the overflow (V) status flag (bit 3). 1863def : InstAlias<"sev", (BSETs 3)>; 1864def : InstAlias<"clv", (BCLRs 3)>; 1865 1866// Set/clear aliases for the signed (S) status flag (bit 4). 1867def : InstAlias<"ses", (BSETs 4)>; 1868def : InstAlias<"cls", (BCLRs 4)>; 1869 1870// Set/clear aliases for the half-carry (H) status flag (bit 5). 1871def : InstAlias<"seh", (BSETs 5)>; 1872def : InstAlias<"clh", (BCLRs 5)>; 1873 1874// Set/clear aliases for the T status flag (bit 6). 1875def : InstAlias<"set", (BSETs 6)>; 1876def : InstAlias<"clt", (BCLRs 6)>; 1877 1878// Set/clear aliases for the interrupt (I) status flag (bit 7). 1879def : InstAlias<"sei", (BSETs 7)>; 1880def : InstAlias<"cli", (BCLRs 7)>; 1881 1882//===----------------------------------------------------------------------===// 1883// Special/Control instructions 1884//===----------------------------------------------------------------------===// 1885 1886// BREAK 1887// Breakpoint instruction 1888// --------- 1889// <|1001|0101|1001|1000> 1890def BREAK : F16<0b1001010110011000, 1891 (outs), 1892 (ins), 1893 "break", 1894 []>, 1895 Requires<[HasBREAK]>; 1896 1897// NOP 1898// No-operation instruction 1899// --------- 1900// <|0000|0000|0000|0000> 1901def NOP : F16<0b0000000000000000, 1902 (outs), 1903 (ins), 1904 "nop", 1905 []>; 1906 1907// SLEEP 1908// Sleep instruction 1909// --------- 1910// <|1001|0101|1000|1000> 1911def SLEEP : F16<0b1001010110001000, 1912 (outs), 1913 (ins), 1914 "sleep", 1915 []>; 1916 1917// WDR 1918// Watchdog reset 1919// --------- 1920// <|1001|0101|1010|1000> 1921def WDR : F16<0b1001010110101000, 1922 (outs), 1923 (ins), 1924 "wdr", 1925 []>; 1926 1927//===----------------------------------------------------------------------===// 1928// Pseudo instructions for later expansion 1929//===----------------------------------------------------------------------===// 1930 1931//:TODO: Optimize this for wider types AND optimize the following code 1932// compile int foo(char a, char b, char c, char d) {return d+b;} 1933// looks like a missed sext_inreg opportunity. 1934def SEXT : ExtensionPseudo< 1935 (outs DREGS:$dst), 1936 (ins GPR8:$src), 1937 "sext\t$dst, $src", 1938 [(set i16:$dst, (sext i8:$src)), (implicit SREG)] 1939>; 1940 1941def ZEXT : ExtensionPseudo< 1942 (outs DREGS:$dst), 1943 (ins GPR8:$src), 1944 "zext\t$dst, $src", 1945 [(set i16:$dst, (zext i8:$src)), (implicit SREG)] 1946>; 1947 1948// This pseudo gets expanded into a movw+adiw thus it clobbers SREG. 1949let Defs = [SREG], 1950 hasSideEffects = 0 in 1951def FRMIDX : Pseudo<(outs DLDREGS:$dst), 1952 (ins DLDREGS:$src, i16imm:$src2), 1953 "frmidx\t$dst, $src, $src2", 1954 []>; 1955 1956// This pseudo is either converted to a regular store or a push which clobbers 1957// SP. 1958def STDSPQRr : StorePseudo< 1959 (outs), 1960 (ins memspi:$dst, GPR8:$src), 1961 "stdstk\t$dst, $src", 1962 [(store i8:$src, addr:$dst)] 1963>; 1964 1965// This pseudo is either converted to a regular store or a push which clobbers 1966// SP. 1967def STDWSPQRr : StorePseudo< 1968 (outs), 1969 (ins memspi:$dst, DREGS:$src), 1970 "stdwstk\t$dst, $src", 1971 [(store i16:$src, addr:$dst)] 1972>; 1973 1974// SP read/write pseudos. 1975let hasSideEffects = 0 in 1976{ 1977 let Uses = [SP] in 1978 def SPREAD : Pseudo< 1979 (outs DREGS:$dst), 1980 (ins GPRSP:$src), 1981 "spread\t$dst, $src", 1982 [] 1983 >; 1984 1985 let Defs = [SP] in 1986 def SPWRITE : Pseudo< 1987 (outs GPRSP:$dst), 1988 (ins DREGS:$src), 1989 "spwrite\t$dst, $src", 1990 []>; 1991} 1992 1993def Select8 : SelectPseudo< 1994 (outs GPR8:$dst), 1995 (ins GPR8:$src, GPR8:$src2, i8imm:$cc), 1996 "# Select8 PSEUDO", 1997 [(set i8:$dst, (AVRselectcc i8:$src, i8:$src2, imm:$cc))] 1998>; 1999 2000def Select16 : SelectPseudo< 2001 (outs DREGS:$dst), 2002 (ins DREGS:$src, DREGS:$src2, i8imm:$cc), 2003 "# Select16 PSEUDO", 2004 [(set i16:$dst, (AVRselectcc i16:$src, i16:$src2, imm:$cc))] 2005>; 2006 2007def Lsl8 : ShiftPseudo< 2008 (outs GPR8:$dst), 2009 (ins GPR8:$src, GPR8:$cnt), 2010 "# Lsl8 PSEUDO", 2011 [(set i8:$dst, (AVRlslLoop i8:$src, i8:$cnt))] 2012>; 2013 2014def Lsl16 : ShiftPseudo< 2015 (outs DREGS:$dst), 2016 (ins DREGS:$src, GPR8:$cnt), 2017 "# Lsl16 PSEUDO", 2018 [(set i16:$dst, (AVRlslLoop i16:$src, i8:$cnt))] 2019>; 2020 2021def Lsr8 : ShiftPseudo< 2022 (outs GPR8:$dst), 2023 (ins GPR8:$src, GPR8:$cnt), 2024 "# Lsr8 PSEUDO", 2025 [(set i8:$dst, (AVRlsrLoop i8:$src, i8:$cnt))] 2026>; 2027 2028def Lsr16 : ShiftPseudo< 2029 (outs DREGS:$dst), 2030 (ins DREGS:$src, GPR8:$cnt), 2031 "# Lsr16 PSEUDO", 2032 [(set i16:$dst, (AVRlsrLoop i16:$src, i8:$cnt))] 2033>; 2034 2035def Rol8 : ShiftPseudo< 2036 (outs GPR8:$dst), 2037 (ins GPR8:$src, GPR8:$cnt), 2038 "# Rol8 PSEUDO", 2039 [(set i8:$dst, (AVRrolLoop i8:$src, i8:$cnt))] 2040>; 2041 2042def Rol16 : ShiftPseudo< 2043 (outs DREGS:$dst), 2044 (ins DREGS:$src, GPR8:$cnt), 2045 "# Rol16 PSEUDO", 2046 [(set i16:$dst, (AVRrolLoop i16:$src, i8:$cnt))] 2047>; 2048 2049def Ror8 : ShiftPseudo< 2050 (outs GPR8:$dst), 2051 (ins GPR8:$src, GPR8:$cnt), 2052 "# Ror8 PSEUDO", 2053 [(set i8:$dst, (AVRrorLoop i8:$src, i8:$cnt))] 2054>; 2055 2056def Ror16 : ShiftPseudo< 2057 (outs DREGS:$dst), 2058 (ins DREGS:$src, GPR8:$cnt), 2059 "# Ror16 PSEUDO", 2060 [(set i16:$dst, (AVRrorLoop i16:$src, i8:$cnt))] 2061>; 2062 2063def Asr8 : ShiftPseudo< 2064 (outs GPR8:$dst), 2065 (ins GPR8:$src, GPR8:$cnt), 2066 "# Asr8 PSEUDO", 2067 [(set i8:$dst, (AVRasrLoop i8:$src, i8:$cnt))] 2068>; 2069 2070def Asr16 : ShiftPseudo< 2071 (outs DREGS:$dst), 2072 (ins DREGS:$src, GPR8:$cnt), 2073 "# Asr16 PSEUDO", 2074 [(set i16:$dst, (AVRasrLoop i16:$src, i8:$cnt))] 2075>; 2076 2077 2078//===----------------------------------------------------------------------===// 2079// Non-Instruction Patterns 2080//===----------------------------------------------------------------------===// 2081 2082//:TODO: look in x86InstrCompiler.td for odd encoding trick related to 2083// add x, 128 -> sub x, -128. Clang is emitting an eor for this (ldi+eor) 2084 2085// the add instruction always writes the carry flag 2086def : Pat<(addc i8:$src, i8:$src2), 2087 (ADDRdRr i8:$src, i8:$src2)>; 2088def : Pat<(addc DREGS:$src, DREGS:$src2), 2089 (ADDWRdRr DREGS:$src, DREGS:$src2)>; 2090 2091// all sub instruction variants always writes the carry flag 2092def : Pat<(subc i8:$src, i8:$src2), 2093 (SUBRdRr i8:$src, i8:$src2)>; 2094def : Pat<(subc i16:$src, i16:$src2), 2095 (SUBWRdRr i16:$src, i16:$src2)>; 2096def : Pat<(subc i8:$src, imm:$src2), 2097 (SUBIRdK i8:$src, imm:$src2)>; 2098def : Pat<(subc i16:$src, imm:$src2), 2099 (SUBIWRdK i16:$src, imm:$src2)>; 2100 2101// These patterns convert add (x, -imm) to sub (x, imm) since we dont have 2102// any add with imm instructions. Also take care of the adiw/sbiw instructions. 2103def : Pat<(add i16:$src1, imm0_63_neg:$src2), 2104 (SBIWRdK i16:$src1, (imm0_63_neg:$src2))>; 2105def : Pat<(add i16:$src1, imm:$src2), 2106 (SUBIWRdK i16:$src1, (imm16_neg_XFORM imm:$src2))>; 2107def : Pat<(addc i16:$src1, imm:$src2), 2108 (SUBIWRdK i16:$src1, (imm16_neg_XFORM imm:$src2))>; 2109 2110def : Pat<(add i8:$src1, imm:$src2), 2111 (SUBIRdK i8:$src1, (imm8_neg_XFORM imm:$src2))>; 2112def : Pat<(addc i8:$src1, imm:$src2), 2113 (SUBIRdK i8:$src1, (imm8_neg_XFORM imm:$src2))>; 2114def : Pat<(adde i8:$src1, imm:$src2), 2115 (SBCIRdK i8:$src1, (imm8_neg_XFORM imm:$src2))>; 2116 2117// Calls. 2118def : Pat<(AVRcall (i16 tglobaladdr:$dst)), 2119 (CALLk tglobaladdr:$dst)>; 2120def : Pat<(AVRcall (i16 texternalsym:$dst)), 2121 (CALLk texternalsym:$dst)>; 2122 2123// `anyext` 2124def : Pat<(i16 (anyext i8:$src)), 2125 (INSERT_SUBREG (i16 (IMPLICIT_DEF)), i8:$src, sub_lo)>; 2126 2127// `trunc` 2128def : Pat<(i8 (trunc i16:$src)), 2129 (EXTRACT_SUBREG i16:$src, sub_lo)>; 2130 2131// sext_inreg 2132def : Pat<(sext_inreg i16:$src, i8), 2133 (SEXT (i8 (EXTRACT_SUBREG i16:$src, sub_lo)))>; 2134 2135// GlobalAddress 2136def : Pat<(i16 (AVRWrapper tglobaladdr:$dst)), 2137 (LDIWRdK tglobaladdr:$dst)>; 2138def : Pat<(add i16:$src, (AVRWrapper tglobaladdr:$src2)), 2139 (SUBIWRdK i16:$src, tglobaladdr:$src2)>; 2140def : Pat<(i8 (load (AVRWrapper tglobaladdr:$dst))), 2141 (LDSRdK tglobaladdr:$dst)>; 2142def : Pat<(i16 (load (AVRWrapper tglobaladdr:$dst))), 2143 (LDSWRdK tglobaladdr:$dst)>; 2144def : Pat<(store i8:$src, (i16 (AVRWrapper tglobaladdr:$dst))), 2145 (STSKRr tglobaladdr:$dst, i8:$src)>; 2146def : Pat<(store i16:$src, (i16 (AVRWrapper tglobaladdr:$dst))), 2147 (STSWKRr tglobaladdr:$dst, i16:$src)>; 2148 2149// BlockAddress 2150def : Pat<(i16 (AVRWrapper tblockaddress:$dst)), 2151 (LDIWRdK tblockaddress:$dst)>; 2152 2153def : Pat<(i8 (trunc (AVRlsrwn DLDREGS:$src, (i16 8)))), 2154 (EXTRACT_SUBREG DREGS:$src, sub_hi)>; 2155 2156// :FIXME: DAGCombiner produces an shl node after legalization from these seq: 2157// BR_JT -> (mul x, 2) -> (shl x, 1) 2158def : Pat<(shl i16:$src1, (i8 1)), 2159 (LSLWRd i16:$src1)>; 2160 2161// Lowering of 'tst' node to 'TST' instruction. 2162// TST is an alias of AND Rd, Rd. 2163def : Pat<(AVRtst i8:$rd), 2164 (ANDRdRr GPR8:$rd, GPR8:$rd)>; 2165 2166// Lowering of 'lsl' node to 'LSL' instruction. 2167// LSL is an alias of 'ADD Rd, Rd' 2168def : Pat<(AVRlsl i8:$rd), 2169 (ADDRdRr GPR8:$rd, GPR8:$rd)>; 2170 2171