1//===-- AVRRegisterInfo.td - AVR Register defs -------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Declarations that describe the AVR register file 11//===----------------------------------------------------------------------===// 12 13// 8-bit General purpose register definition. 14class AVRReg<bits<16> num, string name, list<Register> subregs = [], 15 list<string> altNames = []> : RegisterWithSubRegs<name, subregs> { 16 field bits<16> Num = num; 17 18 let HWEncoding = num; 19 let Namespace = "AVR"; 20 let SubRegs = subregs; 21 let AltNames = altNames; 22} 23 24// Subregister indices. 25let Namespace = "AVR" in { 26 def sub_lo : SubRegIndex<8>; 27 def sub_hi : SubRegIndex<8, 8>; 28} 29 30let Namespace = "AVR" in { def ptr : RegAltNameIndex; } 31 32//===----------------------------------------------------------------------===// 33// 8-bit general purpose registers 34//===----------------------------------------------------------------------===// 35 36def R0 : AVRReg<0, "r0">, DwarfRegNum<[0]>; 37def R1 : AVRReg<1, "r1">, DwarfRegNum<[1]>; 38def R2 : AVRReg<2, "r2">, DwarfRegNum<[2]>; 39def R3 : AVRReg<3, "r3">, DwarfRegNum<[3]>; 40def R4 : AVRReg<4, "r4">, DwarfRegNum<[4]>; 41def R5 : AVRReg<5, "r5">, DwarfRegNum<[5]>; 42def R6 : AVRReg<6, "r6">, DwarfRegNum<[6]>; 43def R7 : AVRReg<7, "r7">, DwarfRegNum<[7]>; 44def R8 : AVRReg<8, "r8">, DwarfRegNum<[8]>; 45def R9 : AVRReg<9, "r9">, DwarfRegNum<[9]>; 46def R10 : AVRReg<10, "r10">, DwarfRegNum<[10]>; 47def R11 : AVRReg<11, "r11">, DwarfRegNum<[11]>; 48def R12 : AVRReg<12, "r12">, DwarfRegNum<[12]>; 49def R13 : AVRReg<13, "r13">, DwarfRegNum<[13]>; 50def R14 : AVRReg<14, "r14">, DwarfRegNum<[14]>; 51def R15 : AVRReg<15, "r15">, DwarfRegNum<[15]>; 52def R16 : AVRReg<16, "r16">, DwarfRegNum<[16]>; 53def R17 : AVRReg<17, "r17">, DwarfRegNum<[17]>; 54def R18 : AVRReg<18, "r18">, DwarfRegNum<[18]>; 55def R19 : AVRReg<19, "r19">, DwarfRegNum<[19]>; 56def R20 : AVRReg<20, "r20">, DwarfRegNum<[20]>; 57def R21 : AVRReg<21, "r21">, DwarfRegNum<[21]>; 58def R22 : AVRReg<22, "r22">, DwarfRegNum<[22]>; 59def R23 : AVRReg<23, "r23">, DwarfRegNum<[23]>; 60def R24 : AVRReg<24, "r24">, DwarfRegNum<[24]>; 61def R25 : AVRReg<25, "r25">, DwarfRegNum<[25]>; 62def R26 : AVRReg<26, "r26", [], ["xl"]>, DwarfRegNum<[26]>; 63def R27 : AVRReg<27, "r27", [], ["xh"]>, DwarfRegNum<[27]>; 64def R28 : AVRReg<28, "r28", [], ["yl"]>, DwarfRegNum<[28]>; 65def R29 : AVRReg<29, "r29", [], ["yh"]>, DwarfRegNum<[29]>; 66def R30 : AVRReg<30, "r30", [], ["zl"]>, DwarfRegNum<[30]>; 67def R31 : AVRReg<31, "r31", [], ["zh"]>, DwarfRegNum<[31]>; 68def SPL : AVRReg<32, "SPL">, DwarfRegNum<[32]>; 69def SPH : AVRReg<33, "SPH">, DwarfRegNum<[33]>; 70 71let SubRegIndices = [sub_lo, sub_hi], CoveredBySubRegs = 1 in { 72 // 16 bit GPR pairs. 73 def SP : AVRReg<32, "SP", [SPL, SPH]>, DwarfRegNum<[32]>; 74 75 // The pointer registers (X,Y,Z) are a special case because they 76 // are printed as a `high:low` pair when a DREG is expected, 77 // but printed using `X`, `Y`, `Z` when a pointer register is expected. 78 let RegAltNameIndices = [ptr] in { 79 def R31R30 : AVRReg<30, "r31:r30", [R30, R31], ["Z"]>, DwarfRegNum<[30]>; 80 def R29R28 : AVRReg<28, "r29:r28", [R28, R29], ["Y"]>, DwarfRegNum<[28]>; 81 def R27R26 : AVRReg<26, "r27:r26", [R26, R27], ["X"]>, DwarfRegNum<[26]>; 82 } 83 def R25R24 : AVRReg<24, "r25:r24", [R24, R25]>, DwarfRegNum<[24]>; 84 def R23R22 : AVRReg<22, "r23:r22", [R22, R23]>, DwarfRegNum<[22]>; 85 def R21R20 : AVRReg<20, "r21:r20", [R20, R21]>, DwarfRegNum<[20]>; 86 def R19R18 : AVRReg<18, "r19:r18", [R18, R19]>, DwarfRegNum<[18]>; 87 def R17R16 : AVRReg<16, "r17:r16", [R16, R17]>, DwarfRegNum<[16]>; 88 def R15R14 : AVRReg<14, "r15:r14", [R14, R15]>, DwarfRegNum<[14]>; 89 def R13R12 : AVRReg<12, "r13:r12", [R12, R13]>, DwarfRegNum<[12]>; 90 def R11R10 : AVRReg<10, "r11:r10", [R10, R11]>, DwarfRegNum<[10]>; 91 def R9R8 : AVRReg<8, "r9:r8", [R8, R9]>, DwarfRegNum<[8]>; 92 def R7R6 : AVRReg<6, "r7:r6", [R6, R7]>, DwarfRegNum<[6]>; 93 def R5R4 : AVRReg<4, "r5:r4", [R4, R5]>, DwarfRegNum<[4]>; 94 def R3R2 : AVRReg<2, "r3:r2", [R2, R3]>, DwarfRegNum<[2]>; 95 def R1R0 : AVRReg<0, "r1:r0", [R0, R1]>, DwarfRegNum<[0]>; 96 97 // Pseudo registers for unaligned i16 98 def R26R25 : AVRReg<25, "r26:r25", [R25, R26]>, DwarfRegNum<[25]>; 99 def R24R23 : AVRReg<23, "r24:r23", [R23, R24]>, DwarfRegNum<[23]>; 100 def R22R21 : AVRReg<21, "r22:r21", [R21, R22]>, DwarfRegNum<[21]>; 101 def R20R19 : AVRReg<19, "r20:r19", [R19, R20]>, DwarfRegNum<[19]>; 102 def R18R17 : AVRReg<17, "r18:r17", [R17, R18]>, DwarfRegNum<[17]>; 103 def R16R15 : AVRReg<15, "r16:r15", [R15, R16]>, DwarfRegNum<[15]>; 104 def R14R13 : AVRReg<13, "r14:r13", [R13, R14]>, DwarfRegNum<[13]>; 105 def R12R11 : AVRReg<11, "r12:r11", [R11, R12]>, DwarfRegNum<[11]>; 106 def R10R9 : AVRReg<9, "r10:r9", [R9, R10]>, DwarfRegNum<[9]>; 107} 108 109//===----------------------------------------------------------------------===// 110// Register Classes 111//===----------------------------------------------------------------------===// 112 113// Main 8-bit register class. 114def GPR8 : RegisterClass<"AVR", [i8], 8, 115 ( 116 // Return value and argument registers. 117 add R24, R25, R18, R19, R20, R21, R22, R23, 118 // Scratch registers. 119 R30, R31, R26, R27, 120 // Callee saved registers. 121 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10, 122 R9, R8, R7, R6, R5, R4, R3, R2, R0, R1)>; 123 124// Simple lower registers r0..r15 125def GPR8lo : RegisterClass<"AVR", [i8], 8, 126 (add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, 127 R5, R4, R3, R2, R0, R1)>; 128 129// 8-bit register class for instructions which take immediates. 130def LD8 : RegisterClass<"AVR", [i8], 8, 131 ( 132 // Return value and arguments. 133 add R24, R25, R18, R19, R20, R21, R22, R23, 134 // Scratch registers. 135 R30, R31, R26, R27, 136 // Callee saved registers. 137 R28, R29, R17, R16)>; 138 139// Simple lower registers r16..r23 140def LD8lo : RegisterClass<"AVR", [i8], 8, 141 (add R23, R22, R21, R20, R19, R18, R17, R16)>; 142 143// Main 16-bit pair register class. 144def DREGS : RegisterClass<"AVR", [i16], 8, 145 ( 146 // Return value and arguments. 147 add R25R24, R19R18, R21R20, R23R22, 148 // Scratch registers. 149 R31R30, R27R26, 150 // Callee saved registers. 151 R29R28, R17R16, R15R14, R13R12, R11R10, R9R8, 152 R7R6, R5R4, R3R2, R1R0, 153 // Pseudo regs for unaligned 16-bits 154 R26R25, R24R23, R22R21, R20R19, R18R17, R16R15, 155 R14R13, R12R11, R10R9)>; 156 157// Lower 16-bit pair registers in R0..R15, only used in inline assembly. 158def DREGSlo 159 : RegisterClass<"AVR", [i16], 8, 160 (add R15R14, R13R12, R11R10, R9R8, R7R6, R5R4, R3R2, R1R0)>; 161 162// Lower 16-bit pair registers in r16..r23, only used in inline assembly. 163def DREGSLD8lo : RegisterClass<"AVR", [i16], 8, 164 ( 165 // Return value and arguments. 166 add R19R18, R21R20, R23R22, 167 // Callee saved registers. 168 R17R16)>; 169 170// 16-bit pair register class for movw 171def DREGSMOVW : RegisterClass<"AVR", [i16], 8, 172 ( 173 // Return value and arguments. 174 add R25R24, R19R18, R21R20, R23R22, 175 // Scratch registers. 176 R31R30, R27R26, 177 // Callee saved registers. 178 R29R28, R17R16, R15R14, R13R12, R11R10, R9R8, 179 R7R6, R5R4, R3R2, R1R0)>; 180 181// 16-bit register class for immediate instructions. 182def DLDREGS : RegisterClass<"AVR", [i16], 8, 183 ( 184 // Return value and arguments. 185 add R25R24, R19R18, R21R20, R23R22, 186 // Scratch registers. 187 R31R30, R27R26, 188 // Callee saved registers. 189 R29R28, R17R16)>; 190 191// 16-bit register class for the adiw/sbiw instructions. 192def IWREGS : RegisterClass<"AVR", [i16], 8, 193 ( 194 // Return value and arguments. 195 add R25R24, 196 // Scratch registers. 197 R31R30, R27R26, 198 // Callee saved registers. 199 R29R28)>; 200 201// 16-bit register class for the ld and st instructions. 202// AKA X,Y, and Z 203def PTRREGS : RegisterClass<"AVR", [i16], 8, 204 (add R27R26, // X 205 R29R28, // Y 206 R31R30 // Z 207 ), 208 ptr>; 209 210// 16-bit register class for the ldd and std instructions. 211// AKA Y and Z. 212def PTRDISPREGS : RegisterClass<"AVR", [i16], 8, (add R31R30, R29R28), ptr>; 213 214// We have a bunch of instructions with an explicit Z register argument. We 215// model this using a register class containing only the Z register. 216def ZREG : RegisterClass<"AVR", [i16], 8, (add R31R30)>; 217 218// Register class used for the stack read pseudo instruction. 219def GPRSP : RegisterClass<"AVR", [i16], 8, (add SP)>; 220 221// Status register. 222def SREG : AVRReg<14, "FLAGS">, DwarfRegNum<[88]>; 223def CCR : RegisterClass<"AVR", [i8], 8, (add SREG)> { 224 let CopyCost = -1; // Don't allow copying of status registers 225} 226