1//===-- CSKYInstrInfo.td - Target Description for CSKY -----*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the CSKY instructions in TableGen format.
10//
11//===----------------------------------------------------------------------===//
12
13include "CSKYInstrFormats.td"
14
15//===----------------------------------------------------------------------===//
16// CSKY specific DAG Nodes.
17//===----------------------------------------------------------------------===//
18
19// TODO: Add CSKY specific DAG Nodes.
20
21//===----------------------------------------------------------------------===//
22// Operand and SDNode transformation definitions.
23//===----------------------------------------------------------------------===//
24
25class oimm<int num> : Operand<i32>,
26  ImmLeaf<i32, "return isUInt<"#num#">(Imm - 1);"> {
27  let EncoderMethod = "getOImmOpValue";
28}
29
30class uimm<int num, int shift = 0> : Operand<i32>,
31  ImmLeaf<i32, "return isShiftedUInt<"#num#", "#shift#">(Imm);"> {
32  let EncoderMethod = "getImmOpValue<"#shift#">";
33}
34
35class simm<int num, int shift = 0> : Operand<i32>,
36  ImmLeaf<i32, "return isShiftedInt<"#num#", "#shift#">(Imm);"> {
37  let EncoderMethod = "getImmOpValue<"#shift#">";
38}
39
40def nimm_XFORM : SDNodeXForm<imm, [{
41  return CurDAG->getTargetConstant(~N->getSExtValue(), SDLoc(N), MVT::i32);
42}]>;
43class nimm<int num> : Operand<i32>,
44  ImmLeaf<i32, "return isUInt<"#num#">(~Imm);", nimm_XFORM> {
45}
46
47
48def oimm12 : oimm<12>;
49
50def nimm12 : nimm<12>;
51
52def uimm5 : uimm<5>;
53def uimm12 : uimm<12>;
54
55//===----------------------------------------------------------------------===//
56// Instruction definitions.
57//===----------------------------------------------------------------------===//
58
59class TriOpFrag<dag res> : PatFrag<(ops node: $LHS, node:$MHS, node:$RHS), res>;
60class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
61class UnOpFrag<dag res> : PatFrag<(ops node:$Src), res>;
62
63def ADDI32 : I_12<0x0, "addi32", add, oimm12>;
64def SUBI32 : I_12<0x1, "subi32", sub, oimm12>;
65def ANDI32 : I_12<0x2, "andi32", and, uimm12>;
66def ANDNI32 : I_12<0x3, "andni32", and, nimm12>;
67def XORI32 : I_12<0x4, "xori32", xor, uimm12>;
68def LSLI32 : I_5_XZ<0x12, 0x1, "lsli32",
69  (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
70  [(set GPR:$rz, (shl GPR:$rx, uimm5:$imm5))]>;
71def LSRI32 : I_5_XZ<0x12, 0x2, "lsri32",
72  (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
73  [(set GPR:$rz, (srl GPR:$rx, uimm5:$imm5))]>;
74def ASRI32 : I_5_XZ<0x12, 0x4, "asri32",
75  (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
76  [(set GPR:$rz, (sra GPR:$rx, uimm5:$imm5))]>;
77
78
79
80def ADDU32 : R_YXZ_SP_F1<0x0, 0x1,
81  BinOpFrag<(add node:$LHS, node:$RHS)>, "addu32", 1>;
82def SUBU32 : R_YXZ_SP_F1<0x0, 0x4,
83  BinOpFrag<(sub node:$LHS, node:$RHS)>, "subu32">;
84def AND32 : R_YXZ_SP_F1<0x8, 0x1,
85  BinOpFrag<(and node:$LHS, node:$RHS)>, "and32", 1>;
86def ANDN32 : R_YXZ_SP_F1<0x8, 0x2,
87  BinOpFrag<(and node:$LHS, (not node:$RHS))>, "andn32">;
88def OR32: R_YXZ_SP_F1<0x9, 0x1,
89  BinOpFrag<(or node:$LHS, node:$RHS)>, "or32", 1>;
90def XOR32 : R_YXZ_SP_F1<0x9, 0x2,
91  BinOpFrag<(xor node:$LHS, node:$RHS)>, "xor32", 1>;
92def NOR32 : R_YXZ_SP_F1<0x9, 0x4,
93  BinOpFrag<(not (or node:$LHS, node:$RHS))>, "nor32", 1>;
94def LSL32 : R_YXZ_SP_F1<0x10, 0x1,
95  BinOpFrag<(shl node:$LHS, node:$RHS)>, "lsl32">;
96def LSR32 : R_YXZ_SP_F1<0x10, 0x2,
97  BinOpFrag<(srl node:$LHS, node:$RHS)>, "lsr32">;
98def ASR32 : R_YXZ_SP_F1<0x10, 0x4,
99  BinOpFrag<(sra node:$LHS, node:$RHS)>, "asr32">;
100def MULT32 : R_YXZ_SP_F1<0x21, 0x1,
101  BinOpFrag<(mul node:$LHS, node:$RHS)>, "mult32", 1>;
102def DIVS32 : R_YXZ_SP_F1<0x20, 0x2,
103  BinOpFrag<(sdiv node:$LHS, node:$RHS)>, "divs32">;
104def DIVU32 : R_YXZ_SP_F1<0x20, 0x1,
105  BinOpFrag<(udiv node:$LHS, node:$RHS)>, "divu32">;
106
107def NOT32 : R_XXZ<0b001001, 0b00100, (outs GPR:$rz), (ins GPR:$rx),
108  "not", [(set GPR:$rz, (not GPR:$rx))]>;
109