10b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 85ffd83dbSDimitry Andric// Automatically generated file, do not edit! 90b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 100b57cec5SDimitry Andric 11fe6060f1SDimitry Andricclass Enc_01d3d0 : OpcodeHexagon { 12fe6060f1SDimitry Andric bits <5> Vu32; 13fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 14fe6060f1SDimitry Andric bits <5> Rt32; 15fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 16fe6060f1SDimitry Andric bits <5> Vdd32; 17fe6060f1SDimitry Andric let Inst{4-0} = Vdd32{4-0}; 18fe6060f1SDimitry Andric} 19fe6060f1SDimitry Andricclass Enc_02553a : OpcodeHexagon { 20fe6060f1SDimitry Andric bits <7> Ii; 21fe6060f1SDimitry Andric let Inst{11-5} = Ii{6-0}; 220b57cec5SDimitry Andric bits <5> Rs32; 230b57cec5SDimitry Andric let Inst{20-16} = Rs32{4-0}; 24fe6060f1SDimitry Andric bits <2> Pd4; 25fe6060f1SDimitry Andric let Inst{1-0} = Pd4{1-0}; 26fe6060f1SDimitry Andric} 27fe6060f1SDimitry Andricclass Enc_03833b : OpcodeHexagon { 28fe6060f1SDimitry Andric bits <5> Rss32; 29fe6060f1SDimitry Andric let Inst{20-16} = Rss32{4-0}; 30fe6060f1SDimitry Andric bits <5> Rt32; 31fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 32fe6060f1SDimitry Andric bits <2> Pd4; 33fe6060f1SDimitry Andric let Inst{1-0} = Pd4{1-0}; 34fe6060f1SDimitry Andric} 35fe6060f1SDimitry Andricclass Enc_041d7b : OpcodeHexagon { 36fe6060f1SDimitry Andric bits <11> Ii; 37fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 38fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 39fe6060f1SDimitry Andric bits <4> Rs16; 40fe6060f1SDimitry Andric let Inst{19-16} = Rs16{3-0}; 41fe6060f1SDimitry Andric bits <5> n1; 42fe6060f1SDimitry Andric let Inst{28-28} = n1{4-4}; 43fe6060f1SDimitry Andric let Inst{24-23} = n1{3-2}; 44fe6060f1SDimitry Andric let Inst{13-13} = n1{1-1}; 45fe6060f1SDimitry Andric let Inst{8-8} = n1{0-0}; 46fe6060f1SDimitry Andric} 47fe6060f1SDimitry Andricclass Enc_04c959 : OpcodeHexagon { 48fe6060f1SDimitry Andric bits <2> Ii; 49fe6060f1SDimitry Andric let Inst{13-13} = Ii{1-1}; 50fe6060f1SDimitry Andric let Inst{7-7} = Ii{0-0}; 51fe6060f1SDimitry Andric bits <6> II; 52fe6060f1SDimitry Andric let Inst{11-8} = II{5-2}; 53fe6060f1SDimitry Andric let Inst{6-5} = II{1-0}; 54fe6060f1SDimitry Andric bits <5> Rt32; 55fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 56fe6060f1SDimitry Andric bits <5> Ryy32; 57fe6060f1SDimitry Andric let Inst{4-0} = Ryy32{4-0}; 58fe6060f1SDimitry Andric} 59fe6060f1SDimitry Andricclass Enc_0527db : OpcodeHexagon { 60fe6060f1SDimitry Andric bits <4> Rs16; 61fe6060f1SDimitry Andric let Inst{7-4} = Rs16{3-0}; 62fe6060f1SDimitry Andric bits <4> Rx16; 63fe6060f1SDimitry Andric let Inst{3-0} = Rx16{3-0}; 64fe6060f1SDimitry Andric} 65fe6060f1SDimitry Andricclass Enc_052c7d : OpcodeHexagon { 66fe6060f1SDimitry Andric bits <5> Ii; 67fe6060f1SDimitry Andric let Inst{6-3} = Ii{4-1}; 68fe6060f1SDimitry Andric bits <5> Rt32; 69fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 70fe6060f1SDimitry Andric bits <5> Rx32; 71fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 72fe6060f1SDimitry Andric} 73fe6060f1SDimitry Andricclass Enc_08d755 : OpcodeHexagon { 74fe6060f1SDimitry Andric bits <8> Ii; 75fe6060f1SDimitry Andric let Inst{12-5} = Ii{7-0}; 76fe6060f1SDimitry Andric bits <5> Rs32; 77fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 78fe6060f1SDimitry Andric bits <2> Pd4; 79fe6060f1SDimitry Andric let Inst{1-0} = Pd4{1-0}; 80fe6060f1SDimitry Andric} 81fe6060f1SDimitry Andricclass Enc_0aa344 : OpcodeHexagon { 82fe6060f1SDimitry Andric bits <5> Gss32; 83fe6060f1SDimitry Andric let Inst{20-16} = Gss32{4-0}; 84fe6060f1SDimitry Andric bits <5> Rdd32; 85fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 86fe6060f1SDimitry Andric} 87fe6060f1SDimitry Andricclass Enc_0b2e5b : OpcodeHexagon { 88fe6060f1SDimitry Andric bits <3> Ii; 89fe6060f1SDimitry Andric let Inst{7-5} = Ii{2-0}; 90fe6060f1SDimitry Andric bits <5> Vu32; 91fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 92fe6060f1SDimitry Andric bits <5> Vv32; 93fe6060f1SDimitry Andric let Inst{20-16} = Vv32{4-0}; 94fe6060f1SDimitry Andric bits <5> Vd32; 95fe6060f1SDimitry Andric let Inst{4-0} = Vd32{4-0}; 96fe6060f1SDimitry Andric} 97fe6060f1SDimitry Andricclass Enc_0b51ce : OpcodeHexagon { 98fe6060f1SDimitry Andric bits <3> Ii; 99fe6060f1SDimitry Andric let Inst{10-8} = Ii{2-0}; 100fe6060f1SDimitry Andric bits <2> Qv4; 101fe6060f1SDimitry Andric let Inst{12-11} = Qv4{1-0}; 102fe6060f1SDimitry Andric bits <5> Vs32; 103fe6060f1SDimitry Andric let Inst{4-0} = Vs32{4-0}; 104fe6060f1SDimitry Andric bits <5> Rx32; 105fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 106fe6060f1SDimitry Andric} 107fe6060f1SDimitry Andricclass Enc_0cb018 : OpcodeHexagon { 108fe6060f1SDimitry Andric bits <5> Cs32; 109fe6060f1SDimitry Andric let Inst{20-16} = Cs32{4-0}; 1100b57cec5SDimitry Andric bits <5> Rd32; 1110b57cec5SDimitry Andric let Inst{4-0} = Rd32{4-0}; 1120b57cec5SDimitry Andric} 113fe6060f1SDimitry Andricclass Enc_0d8870 : OpcodeHexagon { 114fe6060f1SDimitry Andric bits <12> Ii; 115fe6060f1SDimitry Andric let Inst{26-25} = Ii{11-10}; 116fe6060f1SDimitry Andric let Inst{13-13} = Ii{9-9}; 117fe6060f1SDimitry Andric let Inst{7-0} = Ii{8-1}; 118fe6060f1SDimitry Andric bits <5> Rs32; 119fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 120fe6060f1SDimitry Andric bits <3> Nt8; 121fe6060f1SDimitry Andric let Inst{10-8} = Nt8{2-0}; 122fe6060f1SDimitry Andric} 123fe6060f1SDimitry Andricclass Enc_0d8adb : OpcodeHexagon { 124fe6060f1SDimitry Andric bits <8> Ii; 125fe6060f1SDimitry Andric let Inst{12-5} = Ii{7-0}; 126fe6060f1SDimitry Andric bits <5> Rss32; 127fe6060f1SDimitry Andric let Inst{20-16} = Rss32{4-0}; 128fe6060f1SDimitry Andric bits <2> Pd4; 129fe6060f1SDimitry Andric let Inst{1-0} = Pd4{1-0}; 130fe6060f1SDimitry Andric} 131fe6060f1SDimitry Andricclass Enc_0e41fa : OpcodeHexagon { 132fe6060f1SDimitry Andric bits <5> Vuu32; 133fe6060f1SDimitry Andric let Inst{12-8} = Vuu32{4-0}; 134fe6060f1SDimitry Andric bits <5> Rt32; 135fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 136fe6060f1SDimitry Andric bits <5> Vd32; 137fe6060f1SDimitry Andric let Inst{4-0} = Vd32{4-0}; 138fe6060f1SDimitry Andric} 139fe6060f1SDimitry Andricclass Enc_0ed752 : OpcodeHexagon { 140fe6060f1SDimitry Andric bits <5> Rss32; 141fe6060f1SDimitry Andric let Inst{20-16} = Rss32{4-0}; 142fe6060f1SDimitry Andric bits <5> Cdd32; 143fe6060f1SDimitry Andric let Inst{4-0} = Cdd32{4-0}; 144fe6060f1SDimitry Andric} 145fe6060f1SDimitry Andricclass Enc_0f8bab : OpcodeHexagon { 146fe6060f1SDimitry Andric bits <5> Vu32; 147fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 148fe6060f1SDimitry Andric bits <5> Rt32; 149fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 150fe6060f1SDimitry Andric bits <2> Qd4; 151fe6060f1SDimitry Andric let Inst{1-0} = Qd4{1-0}; 152fe6060f1SDimitry Andric} 153fe6060f1SDimitry Andricclass Enc_0fa531 : OpcodeHexagon { 154fe6060f1SDimitry Andric bits <15> Ii; 155fe6060f1SDimitry Andric let Inst{21-21} = Ii{14-14}; 156fe6060f1SDimitry Andric let Inst{13-13} = Ii{13-13}; 157fe6060f1SDimitry Andric let Inst{11-1} = Ii{12-2}; 158fe6060f1SDimitry Andric bits <5> Rs32; 159fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 160fe6060f1SDimitry Andric} 161fe6060f1SDimitry Andricclass Enc_10bc21 : OpcodeHexagon { 162fe6060f1SDimitry Andric bits <4> Ii; 163fe6060f1SDimitry Andric let Inst{6-3} = Ii{3-0}; 164fe6060f1SDimitry Andric bits <5> Rt32; 165fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 166fe6060f1SDimitry Andric bits <5> Rx32; 167fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 168fe6060f1SDimitry Andric} 169fe6060f1SDimitry Andricclass Enc_1178da : OpcodeHexagon { 170fe6060f1SDimitry Andric bits <3> Ii; 171fe6060f1SDimitry Andric let Inst{7-5} = Ii{2-0}; 172fe6060f1SDimitry Andric bits <5> Vu32; 173fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 174fe6060f1SDimitry Andric bits <5> Vv32; 175fe6060f1SDimitry Andric let Inst{20-16} = Vv32{4-0}; 176fe6060f1SDimitry Andric bits <5> Vxx32; 177fe6060f1SDimitry Andric let Inst{4-0} = Vxx32{4-0}; 178fe6060f1SDimitry Andric} 179fe6060f1SDimitry Andricclass Enc_11a146 : OpcodeHexagon { 180fe6060f1SDimitry Andric bits <4> Ii; 181fe6060f1SDimitry Andric let Inst{11-8} = Ii{3-0}; 182fe6060f1SDimitry Andric bits <5> Rss32; 183fe6060f1SDimitry Andric let Inst{20-16} = Rss32{4-0}; 184fe6060f1SDimitry Andric bits <5> Rd32; 185fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 186fe6060f1SDimitry Andric} 187fe6060f1SDimitry Andricclass Enc_12b6e9 : OpcodeHexagon { 188fe6060f1SDimitry Andric bits <4> Ii; 189fe6060f1SDimitry Andric let Inst{11-8} = Ii{3-0}; 1905ffd83dbSDimitry Andric bits <5> Rss32; 1915ffd83dbSDimitry Andric let Inst{20-16} = Rss32{4-0}; 1925ffd83dbSDimitry Andric bits <5> Rdd32; 1935ffd83dbSDimitry Andric let Inst{4-0} = Rdd32{4-0}; 1945ffd83dbSDimitry Andric} 195fe6060f1SDimitry Andricclass Enc_134437 : OpcodeHexagon { 196fe6060f1SDimitry Andric bits <2> Qs4; 197fe6060f1SDimitry Andric let Inst{9-8} = Qs4{1-0}; 198fe6060f1SDimitry Andric bits <2> Qt4; 199fe6060f1SDimitry Andric let Inst{23-22} = Qt4{1-0}; 200fe6060f1SDimitry Andric bits <2> Qd4; 201fe6060f1SDimitry Andric let Inst{1-0} = Qd4{1-0}; 2020b57cec5SDimitry Andric} 2030b57cec5SDimitry Andricclass Enc_140c83 : OpcodeHexagon { 2040b57cec5SDimitry Andric bits <10> Ii; 2050b57cec5SDimitry Andric let Inst{21-21} = Ii{9-9}; 2060b57cec5SDimitry Andric let Inst{13-5} = Ii{8-0}; 2070b57cec5SDimitry Andric bits <5> Rs32; 2080b57cec5SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2090b57cec5SDimitry Andric bits <5> Rd32; 2100b57cec5SDimitry Andric let Inst{4-0} = Rd32{4-0}; 2110b57cec5SDimitry Andric} 212fe6060f1SDimitry Andricclass Enc_143445 : OpcodeHexagon { 213fe6060f1SDimitry Andric bits <13> Ii; 214fe6060f1SDimitry Andric let Inst{26-25} = Ii{12-11}; 215fe6060f1SDimitry Andric let Inst{13-13} = Ii{10-10}; 216fe6060f1SDimitry Andric let Inst{7-0} = Ii{9-2}; 217fe6060f1SDimitry Andric bits <5> Rs32; 218fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 219fe6060f1SDimitry Andric bits <5> Rt32; 220fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 221fe6060f1SDimitry Andric} 222fe6060f1SDimitry Andricclass Enc_143a3c : OpcodeHexagon { 223fe6060f1SDimitry Andric bits <6> Ii; 224fe6060f1SDimitry Andric let Inst{13-8} = Ii{5-0}; 225fe6060f1SDimitry Andric bits <6> II; 226fe6060f1SDimitry Andric let Inst{23-21} = II{5-3}; 227fe6060f1SDimitry Andric let Inst{7-5} = II{2-0}; 228fe6060f1SDimitry Andric bits <5> Rss32; 229fe6060f1SDimitry Andric let Inst{20-16} = Rss32{4-0}; 230fe6060f1SDimitry Andric bits <5> Rxx32; 231fe6060f1SDimitry Andric let Inst{4-0} = Rxx32{4-0}; 232fe6060f1SDimitry Andric} 233fe6060f1SDimitry Andricclass Enc_14640c : OpcodeHexagon { 234fe6060f1SDimitry Andric bits <11> Ii; 235fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 236fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 237fe6060f1SDimitry Andric bits <4> Rs16; 238fe6060f1SDimitry Andric let Inst{19-16} = Rs16{3-0}; 239fe6060f1SDimitry Andric bits <5> n1; 240fe6060f1SDimitry Andric let Inst{28-28} = n1{4-4}; 241fe6060f1SDimitry Andric let Inst{24-22} = n1{3-1}; 242fe6060f1SDimitry Andric let Inst{13-13} = n1{0-0}; 243fe6060f1SDimitry Andric} 244fe6060f1SDimitry Andricclass Enc_14d27a : OpcodeHexagon { 245fe6060f1SDimitry Andric bits <5> II; 246fe6060f1SDimitry Andric let Inst{12-8} = II{4-0}; 247fe6060f1SDimitry Andric bits <11> Ii; 248fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 249fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 250fe6060f1SDimitry Andric bits <4> Rs16; 251fe6060f1SDimitry Andric let Inst{19-16} = Rs16{3-0}; 252fe6060f1SDimitry Andric} 253fe6060f1SDimitry Andricclass Enc_152467 : OpcodeHexagon { 254fe6060f1SDimitry Andric bits <5> Ii; 255fe6060f1SDimitry Andric let Inst{8-5} = Ii{4-1}; 256fe6060f1SDimitry Andric bits <5> Rd32; 257fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 258fe6060f1SDimitry Andric bits <5> Rx32; 259fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 260fe6060f1SDimitry Andric} 261fe6060f1SDimitry Andricclass Enc_158beb : OpcodeHexagon { 262fe6060f1SDimitry Andric bits <2> Qs4; 263fe6060f1SDimitry Andric let Inst{6-5} = Qs4{1-0}; 264fe6060f1SDimitry Andric bits <5> Rt32; 265fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 266fe6060f1SDimitry Andric bits <1> Mu2; 267fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 268fe6060f1SDimitry Andric bits <5> Vv32; 269fe6060f1SDimitry Andric let Inst{4-0} = Vv32{4-0}; 270fe6060f1SDimitry Andric} 271fe6060f1SDimitry Andricclass Enc_163a3c : OpcodeHexagon { 272fe6060f1SDimitry Andric bits <7> Ii; 273fe6060f1SDimitry Andric let Inst{12-7} = Ii{6-1}; 274fe6060f1SDimitry Andric bits <5> Rs32; 275fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 276fe6060f1SDimitry Andric bits <5> Rt32; 277fe6060f1SDimitry Andric let Inst{4-0} = Rt32{4-0}; 278fe6060f1SDimitry Andric} 279fe6060f1SDimitry Andricclass Enc_16c48b : OpcodeHexagon { 280fe6060f1SDimitry Andric bits <5> Rt32; 281fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 282fe6060f1SDimitry Andric bits <1> Mu2; 283fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 284fe6060f1SDimitry Andric bits <5> Vv32; 285fe6060f1SDimitry Andric let Inst{12-8} = Vv32{4-0}; 286fe6060f1SDimitry Andric bits <5> Vw32; 287fe6060f1SDimitry Andric let Inst{4-0} = Vw32{4-0}; 288fe6060f1SDimitry Andric} 289fe6060f1SDimitry Andricclass Enc_178717 : OpcodeHexagon { 290fe6060f1SDimitry Andric bits <11> Ii; 291fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 292fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 293fe6060f1SDimitry Andric bits <4> Rs16; 294fe6060f1SDimitry Andric let Inst{19-16} = Rs16{3-0}; 295fe6060f1SDimitry Andric bits <6> n1; 296fe6060f1SDimitry Andric let Inst{28-28} = n1{5-5}; 297fe6060f1SDimitry Andric let Inst{25-23} = n1{4-2}; 298fe6060f1SDimitry Andric let Inst{13-13} = n1{1-1}; 299fe6060f1SDimitry Andric let Inst{8-8} = n1{0-0}; 300fe6060f1SDimitry Andric} 301fe6060f1SDimitry Andricclass Enc_179b35 : OpcodeHexagon { 302fe6060f1SDimitry Andric bits <5> Rs32; 303fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 304fe6060f1SDimitry Andric bits <5> Rtt32; 305fe6060f1SDimitry Andric let Inst{12-8} = Rtt32{4-0}; 306fe6060f1SDimitry Andric bits <5> Rx32; 307fe6060f1SDimitry Andric let Inst{4-0} = Rx32{4-0}; 308fe6060f1SDimitry Andric} 3095ffd83dbSDimitry Andricclass Enc_18c338 : OpcodeHexagon { 3105ffd83dbSDimitry Andric bits <8> Ii; 3115ffd83dbSDimitry Andric let Inst{12-5} = Ii{7-0}; 3125ffd83dbSDimitry Andric bits <8> II; 3135ffd83dbSDimitry Andric let Inst{22-16} = II{7-1}; 3145ffd83dbSDimitry Andric let Inst{13-13} = II{0-0}; 3150b57cec5SDimitry Andric bits <5> Rdd32; 3160b57cec5SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 3170b57cec5SDimitry Andric} 318fe6060f1SDimitry Andricclass Enc_1a9974 : OpcodeHexagon { 319fe6060f1SDimitry Andric bits <2> Ii; 320fe6060f1SDimitry Andric let Inst{13-13} = Ii{1-1}; 321fe6060f1SDimitry Andric let Inst{7-7} = Ii{0-0}; 322fe6060f1SDimitry Andric bits <2> Pv4; 323fe6060f1SDimitry Andric let Inst{6-5} = Pv4{1-0}; 3240b57cec5SDimitry Andric bits <5> Rs32; 3250b57cec5SDimitry Andric let Inst{20-16} = Rs32{4-0}; 326fe6060f1SDimitry Andric bits <5> Ru32; 327fe6060f1SDimitry Andric let Inst{12-8} = Ru32{4-0}; 3280b57cec5SDimitry Andric bits <5> Rtt32; 329fe6060f1SDimitry Andric let Inst{4-0} = Rtt32{4-0}; 330fe6060f1SDimitry Andric} 331fe6060f1SDimitry Andricclass Enc_1aa186 : OpcodeHexagon { 3325ffd83dbSDimitry Andric bits <5> Rss32; 3335ffd83dbSDimitry Andric let Inst{20-16} = Rss32{4-0}; 3345ffd83dbSDimitry Andric bits <5> Rt32; 3355ffd83dbSDimitry Andric let Inst{12-8} = Rt32{4-0}; 336fe6060f1SDimitry Andric bits <5> Rxx32; 337fe6060f1SDimitry Andric let Inst{4-0} = Rxx32{4-0}; 3380b57cec5SDimitry Andric} 339fe6060f1SDimitry Andricclass Enc_1aaec1 : OpcodeHexagon { 340fe6060f1SDimitry Andric bits <3> Ii; 341fe6060f1SDimitry Andric let Inst{10-8} = Ii{2-0}; 342fe6060f1SDimitry Andric bits <3> Os8; 343fe6060f1SDimitry Andric let Inst{2-0} = Os8{2-0}; 3445ffd83dbSDimitry Andric bits <5> Rx32; 3455ffd83dbSDimitry Andric let Inst{20-16} = Rx32{4-0}; 3465ffd83dbSDimitry Andric} 347fe6060f1SDimitry Andricclass Enc_1b64fb : OpcodeHexagon { 348fe6060f1SDimitry Andric bits <16> Ii; 349fe6060f1SDimitry Andric let Inst{26-25} = Ii{15-14}; 350fe6060f1SDimitry Andric let Inst{20-16} = Ii{13-9}; 351fe6060f1SDimitry Andric let Inst{13-13} = Ii{8-8}; 352fe6060f1SDimitry Andric let Inst{7-0} = Ii{7-0}; 353fe6060f1SDimitry Andric bits <5> Rt32; 354fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 355fe6060f1SDimitry Andric} 356fe6060f1SDimitry Andricclass Enc_1bd127 : OpcodeHexagon { 357fe6060f1SDimitry Andric bits <5> Vu32; 358fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 359fe6060f1SDimitry Andric bits <3> Rt8; 360fe6060f1SDimitry Andric let Inst{18-16} = Rt8{2-0}; 361fe6060f1SDimitry Andric bits <5> Vdddd32; 362fe6060f1SDimitry Andric let Inst{4-0} = Vdddd32{4-0}; 363fe6060f1SDimitry Andric} 364fe6060f1SDimitry Andricclass Enc_1cf4ca : OpcodeHexagon { 365fe6060f1SDimitry Andric bits <6> Ii; 366fe6060f1SDimitry Andric let Inst{17-16} = Ii{5-4}; 367fe6060f1SDimitry Andric let Inst{6-3} = Ii{3-0}; 368fe6060f1SDimitry Andric bits <2> Pv4; 369fe6060f1SDimitry Andric let Inst{1-0} = Pv4{1-0}; 370fe6060f1SDimitry Andric bits <5> Rt32; 371fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 372fe6060f1SDimitry Andric} 373fe6060f1SDimitry Andricclass Enc_1de724 : OpcodeHexagon { 374fe6060f1SDimitry Andric bits <11> Ii; 375fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 376fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 377fe6060f1SDimitry Andric bits <4> Rs16; 378fe6060f1SDimitry Andric let Inst{19-16} = Rs16{3-0}; 379fe6060f1SDimitry Andric bits <4> n1; 380fe6060f1SDimitry Andric let Inst{28-28} = n1{3-3}; 381fe6060f1SDimitry Andric let Inst{24-22} = n1{2-0}; 382fe6060f1SDimitry Andric} 383fe6060f1SDimitry Andricclass Enc_1ef990 : OpcodeHexagon { 384fe6060f1SDimitry Andric bits <2> Pv4; 385fe6060f1SDimitry Andric let Inst{12-11} = Pv4{1-0}; 386fe6060f1SDimitry Andric bits <1> Mu2; 387fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 388fe6060f1SDimitry Andric bits <5> Vs32; 389fe6060f1SDimitry Andric let Inst{4-0} = Vs32{4-0}; 390fe6060f1SDimitry Andric bits <5> Rx32; 391fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 392fe6060f1SDimitry Andric} 393fe6060f1SDimitry Andricclass Enc_1f19b5 : OpcodeHexagon { 394fe6060f1SDimitry Andric bits <5> Ii; 395fe6060f1SDimitry Andric let Inst{9-5} = Ii{4-0}; 396fe6060f1SDimitry Andric bits <5> Rss32; 397fe6060f1SDimitry Andric let Inst{20-16} = Rss32{4-0}; 398fe6060f1SDimitry Andric bits <2> Pd4; 399fe6060f1SDimitry Andric let Inst{1-0} = Pd4{1-0}; 400fe6060f1SDimitry Andric} 401fe6060f1SDimitry Andricclass Enc_1f5ba6 : OpcodeHexagon { 402fe6060f1SDimitry Andric bits <4> Rd16; 403fe6060f1SDimitry Andric let Inst{3-0} = Rd16{3-0}; 404fe6060f1SDimitry Andric} 405fe6060f1SDimitry Andricclass Enc_1f5d8f : OpcodeHexagon { 406fe6060f1SDimitry Andric bits <1> Mu2; 407fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 408fe6060f1SDimitry Andric bits <5> Ryy32; 409fe6060f1SDimitry Andric let Inst{4-0} = Ryy32{4-0}; 410fe6060f1SDimitry Andric bits <5> Rx32; 411fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 412fe6060f1SDimitry Andric} 413fe6060f1SDimitry Andricclass Enc_211aaa : OpcodeHexagon { 414fe6060f1SDimitry Andric bits <11> Ii; 415fe6060f1SDimitry Andric let Inst{26-25} = Ii{10-9}; 416fe6060f1SDimitry Andric let Inst{13-5} = Ii{8-0}; 4175ffd83dbSDimitry Andric bits <5> Rs32; 4185ffd83dbSDimitry Andric let Inst{20-16} = Rs32{4-0}; 419fe6060f1SDimitry Andric bits <5> Rd32; 420fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 4215ffd83dbSDimitry Andric} 422fe6060f1SDimitry Andricclass Enc_217147 : OpcodeHexagon { 423fe6060f1SDimitry Andric bits <2> Qv4; 424fe6060f1SDimitry Andric let Inst{23-22} = Qv4{1-0}; 425fe6060f1SDimitry Andric} 426fe6060f1SDimitry Andricclass Enc_222336 : OpcodeHexagon { 427fe6060f1SDimitry Andric bits <4> Ii; 428fe6060f1SDimitry Andric let Inst{8-5} = Ii{3-0}; 429fe6060f1SDimitry Andric bits <5> Rd32; 430fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 431fe6060f1SDimitry Andric bits <5> Rx32; 432fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 433fe6060f1SDimitry Andric} 434fe6060f1SDimitry Andricclass Enc_223005 : OpcodeHexagon { 435fe6060f1SDimitry Andric bits <6> Ii; 436fe6060f1SDimitry Andric let Inst{6-3} = Ii{5-2}; 437fe6060f1SDimitry Andric bits <3> Nt8; 438fe6060f1SDimitry Andric let Inst{10-8} = Nt8{2-0}; 439fe6060f1SDimitry Andric bits <5> Rx32; 440fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 441fe6060f1SDimitry Andric} 442fe6060f1SDimitry Andricclass Enc_226535 : OpcodeHexagon { 443fe6060f1SDimitry Andric bits <8> Ii; 444fe6060f1SDimitry Andric let Inst{12-7} = Ii{7-2}; 445fe6060f1SDimitry Andric bits <5> Rs32; 446fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 447fe6060f1SDimitry Andric bits <5> Rt32; 448fe6060f1SDimitry Andric let Inst{4-0} = Rt32{4-0}; 449fe6060f1SDimitry Andric} 450fe6060f1SDimitry Andricclass Enc_22c845 : OpcodeHexagon { 451fe6060f1SDimitry Andric bits <14> Ii; 452fe6060f1SDimitry Andric let Inst{10-0} = Ii{13-3}; 453fe6060f1SDimitry Andric bits <5> Rx32; 454fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 455fe6060f1SDimitry Andric} 456fe6060f1SDimitry Andricclass Enc_2301d6 : OpcodeHexagon { 457fe6060f1SDimitry Andric bits <6> Ii; 458fe6060f1SDimitry Andric let Inst{20-16} = Ii{5-1}; 459fe6060f1SDimitry Andric let Inst{8-8} = Ii{0-0}; 460fe6060f1SDimitry Andric bits <2> Pt4; 461fe6060f1SDimitry Andric let Inst{10-9} = Pt4{1-0}; 462fe6060f1SDimitry Andric bits <5> Rd32; 463fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 464fe6060f1SDimitry Andric} 465fe6060f1SDimitry Andricclass Enc_245865 : OpcodeHexagon { 466fe6060f1SDimitry Andric bits <5> Vu32; 467fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 468fe6060f1SDimitry Andric bits <5> Vv32; 469fe6060f1SDimitry Andric let Inst{23-19} = Vv32{4-0}; 470fe6060f1SDimitry Andric bits <3> Rt8; 471fe6060f1SDimitry Andric let Inst{18-16} = Rt8{2-0}; 472fe6060f1SDimitry Andric bits <5> Vx32; 473fe6060f1SDimitry Andric let Inst{4-0} = Vx32{4-0}; 474fe6060f1SDimitry Andric} 475fe6060f1SDimitry Andricclass Enc_24a7dc : OpcodeHexagon { 476fe6060f1SDimitry Andric bits <5> Vu32; 477fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 478fe6060f1SDimitry Andric bits <5> Vv32; 479fe6060f1SDimitry Andric let Inst{23-19} = Vv32{4-0}; 480fe6060f1SDimitry Andric bits <3> Rt8; 481fe6060f1SDimitry Andric let Inst{18-16} = Rt8{2-0}; 482fe6060f1SDimitry Andric bits <5> Vdd32; 483fe6060f1SDimitry Andric let Inst{4-0} = Vdd32{4-0}; 484fe6060f1SDimitry Andric} 485fe6060f1SDimitry Andricclass Enc_25bef0 : OpcodeHexagon { 4865ffd83dbSDimitry Andric bits <16> Ii; 487fe6060f1SDimitry Andric let Inst{26-25} = Ii{15-14}; 4885ffd83dbSDimitry Andric let Inst{20-16} = Ii{13-9}; 4895ffd83dbSDimitry Andric let Inst{13-5} = Ii{8-0}; 4905ffd83dbSDimitry Andric bits <5> Rd32; 4915ffd83dbSDimitry Andric let Inst{4-0} = Rd32{4-0}; 4925ffd83dbSDimitry Andric} 493fe6060f1SDimitry Andricclass Enc_263841 : OpcodeHexagon { 494fe6060f1SDimitry Andric bits <5> Vu32; 495fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 4965ffd83dbSDimitry Andric bits <5> Rtt32; 497fe6060f1SDimitry Andric let Inst{20-16} = Rtt32{4-0}; 498fe6060f1SDimitry Andric bits <5> Vd32; 499fe6060f1SDimitry Andric let Inst{4-0} = Vd32{4-0}; 500fe6060f1SDimitry Andric} 501fe6060f1SDimitry Andricclass Enc_277737 : OpcodeHexagon { 502fe6060f1SDimitry Andric bits <8> Ii; 503fe6060f1SDimitry Andric let Inst{22-21} = Ii{7-6}; 504fe6060f1SDimitry Andric let Inst{13-13} = Ii{5-5}; 505fe6060f1SDimitry Andric let Inst{7-5} = Ii{4-2}; 506fe6060f1SDimitry Andric bits <5> Ru32; 507fe6060f1SDimitry Andric let Inst{4-0} = Ru32{4-0}; 508fe6060f1SDimitry Andric bits <5> Rs32; 509fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 510fe6060f1SDimitry Andric bits <5> Rd32; 511fe6060f1SDimitry Andric let Inst{12-8} = Rd32{4-0}; 512fe6060f1SDimitry Andric} 513fe6060f1SDimitry Andricclass Enc_27b757 : OpcodeHexagon { 514fe6060f1SDimitry Andric bits <4> Ii; 515fe6060f1SDimitry Andric let Inst{13-13} = Ii{3-3}; 516fe6060f1SDimitry Andric let Inst{10-8} = Ii{2-0}; 517fe6060f1SDimitry Andric bits <2> Pv4; 518fe6060f1SDimitry Andric let Inst{12-11} = Pv4{1-0}; 519fe6060f1SDimitry Andric bits <5> Rt32; 520fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 521fe6060f1SDimitry Andric bits <5> Vs32; 522fe6060f1SDimitry Andric let Inst{4-0} = Vs32{4-0}; 523fe6060f1SDimitry Andric} 524fe6060f1SDimitry Andricclass Enc_27fd0e : OpcodeHexagon { 525fe6060f1SDimitry Andric bits <6> Ii; 526fe6060f1SDimitry Andric let Inst{8-5} = Ii{5-2}; 527fe6060f1SDimitry Andric bits <1> Mu2; 528fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 529fe6060f1SDimitry Andric bits <5> Rd32; 530fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 531fe6060f1SDimitry Andric bits <5> Rx32; 532fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 533fe6060f1SDimitry Andric} 534fe6060f1SDimitry Andricclass Enc_284ebb : OpcodeHexagon { 535fe6060f1SDimitry Andric bits <2> Ps4; 536fe6060f1SDimitry Andric let Inst{17-16} = Ps4{1-0}; 537fe6060f1SDimitry Andric bits <2> Pt4; 538fe6060f1SDimitry Andric let Inst{9-8} = Pt4{1-0}; 5395ffd83dbSDimitry Andric bits <2> Pd4; 5405ffd83dbSDimitry Andric let Inst{1-0} = Pd4{1-0}; 5415ffd83dbSDimitry Andric} 542fe6060f1SDimitry Andricclass Enc_28a2dc : OpcodeHexagon { 543fe6060f1SDimitry Andric bits <5> Ii; 544fe6060f1SDimitry Andric let Inst{12-8} = Ii{4-0}; 545fe6060f1SDimitry Andric bits <5> Rs32; 546fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 547fe6060f1SDimitry Andric bits <5> Rx32; 548fe6060f1SDimitry Andric let Inst{4-0} = Rx32{4-0}; 549fe6060f1SDimitry Andric} 550fe6060f1SDimitry Andricclass Enc_28dcbb : OpcodeHexagon { 551fe6060f1SDimitry Andric bits <5> Rt32; 552fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 553fe6060f1SDimitry Andric bits <1> Mu2; 554fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 555fe6060f1SDimitry Andric bits <5> Vvv32; 556fe6060f1SDimitry Andric let Inst{4-0} = Vvv32{4-0}; 557fe6060f1SDimitry Andric} 558fe6060f1SDimitry Andricclass Enc_2a3787 : OpcodeHexagon { 559fe6060f1SDimitry Andric bits <13> Ii; 560fe6060f1SDimitry Andric let Inst{26-25} = Ii{12-11}; 561fe6060f1SDimitry Andric let Inst{13-5} = Ii{10-2}; 562fe6060f1SDimitry Andric bits <5> Rs32; 563fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 564fe6060f1SDimitry Andric bits <5> Rd32; 565fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 566fe6060f1SDimitry Andric} 567fe6060f1SDimitry Andricclass Enc_2a7b91 : OpcodeHexagon { 568fe6060f1SDimitry Andric bits <6> Ii; 569fe6060f1SDimitry Andric let Inst{20-16} = Ii{5-1}; 570fe6060f1SDimitry Andric let Inst{8-8} = Ii{0-0}; 571fe6060f1SDimitry Andric bits <2> Pt4; 572fe6060f1SDimitry Andric let Inst{10-9} = Pt4{1-0}; 573fe6060f1SDimitry Andric bits <5> Rdd32; 574fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 575fe6060f1SDimitry Andric} 576fe6060f1SDimitry Andricclass Enc_2ae154 : OpcodeHexagon { 577fe6060f1SDimitry Andric bits <5> Rs32; 578fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 579fe6060f1SDimitry Andric bits <5> Rt32; 580fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 581fe6060f1SDimitry Andric bits <5> Rx32; 582fe6060f1SDimitry Andric let Inst{4-0} = Rx32{4-0}; 5835ffd83dbSDimitry Andric} 5845ffd83dbSDimitry Andricclass Enc_2b3f60 : OpcodeHexagon { 5855ffd83dbSDimitry Andric bits <5> Rss32; 5865ffd83dbSDimitry Andric let Inst{20-16} = Rss32{4-0}; 5875ffd83dbSDimitry Andric bits <5> Rtt32; 5885ffd83dbSDimitry Andric let Inst{12-8} = Rtt32{4-0}; 5895ffd83dbSDimitry Andric bits <5> Rdd32; 5905ffd83dbSDimitry Andric let Inst{4-0} = Rdd32{4-0}; 5915ffd83dbSDimitry Andric bits <2> Px4; 5925ffd83dbSDimitry Andric let Inst{6-5} = Px4{1-0}; 5935ffd83dbSDimitry Andric} 594fe6060f1SDimitry Andricclass Enc_2b518f : OpcodeHexagon { 595fe6060f1SDimitry Andric bits <32> Ii; 596fe6060f1SDimitry Andric let Inst{27-16} = Ii{31-20}; 597fe6060f1SDimitry Andric let Inst{13-0} = Ii{19-6}; 598fe6060f1SDimitry Andric} 599fe6060f1SDimitry Andricclass Enc_2bae10 : OpcodeHexagon { 600fe6060f1SDimitry Andric bits <4> Ii; 601fe6060f1SDimitry Andric let Inst{10-8} = Ii{3-1}; 602fe6060f1SDimitry Andric bits <4> Rs16; 603fe6060f1SDimitry Andric let Inst{7-4} = Rs16{3-0}; 604fe6060f1SDimitry Andric bits <4> Rd16; 605fe6060f1SDimitry Andric let Inst{3-0} = Rd16{3-0}; 606fe6060f1SDimitry Andric} 607fe6060f1SDimitry Andricclass Enc_2d7491 : OpcodeHexagon { 608fe6060f1SDimitry Andric bits <13> Ii; 609fe6060f1SDimitry Andric let Inst{26-25} = Ii{12-11}; 610fe6060f1SDimitry Andric let Inst{13-5} = Ii{10-2}; 611fe6060f1SDimitry Andric bits <5> Rs32; 612fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 613fe6060f1SDimitry Andric bits <5> Rdd32; 614fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 615fe6060f1SDimitry Andric} 616fe6060f1SDimitry Andricclass Enc_2d829e : OpcodeHexagon { 617fe6060f1SDimitry Andric bits <14> Ii; 618fe6060f1SDimitry Andric let Inst{10-0} = Ii{13-3}; 619fe6060f1SDimitry Andric bits <5> Rs32; 620fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 621fe6060f1SDimitry Andric} 622fe6060f1SDimitry Andricclass Enc_2df31d : OpcodeHexagon { 623fe6060f1SDimitry Andric bits <8> Ii; 624fe6060f1SDimitry Andric let Inst{9-4} = Ii{7-2}; 625fe6060f1SDimitry Andric bits <4> Rd16; 626fe6060f1SDimitry Andric let Inst{3-0} = Rd16{3-0}; 627fe6060f1SDimitry Andric} 628fe6060f1SDimitry Andricclass Enc_2e1979 : OpcodeHexagon { 629fe6060f1SDimitry Andric bits <2> Ii; 630fe6060f1SDimitry Andric let Inst{13-13} = Ii{1-1}; 631fe6060f1SDimitry Andric let Inst{7-7} = Ii{0-0}; 632fe6060f1SDimitry Andric bits <2> Pv4; 633fe6060f1SDimitry Andric let Inst{6-5} = Pv4{1-0}; 634fe6060f1SDimitry Andric bits <5> Rs32; 635fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 636fe6060f1SDimitry Andric bits <5> Rt32; 637fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 638fe6060f1SDimitry Andric bits <5> Rd32; 639fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 640fe6060f1SDimitry Andric} 641fe6060f1SDimitry Andricclass Enc_2ea740 : OpcodeHexagon { 642fe6060f1SDimitry Andric bits <4> Ii; 643fe6060f1SDimitry Andric let Inst{13-13} = Ii{3-3}; 644fe6060f1SDimitry Andric let Inst{10-8} = Ii{2-0}; 645fe6060f1SDimitry Andric bits <2> Qv4; 646fe6060f1SDimitry Andric let Inst{12-11} = Qv4{1-0}; 647fe6060f1SDimitry Andric bits <5> Rt32; 648fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 649fe6060f1SDimitry Andric bits <5> Vs32; 650fe6060f1SDimitry Andric let Inst{4-0} = Vs32{4-0}; 651fe6060f1SDimitry Andric} 652fe6060f1SDimitry Andricclass Enc_2ebe3b : OpcodeHexagon { 653fe6060f1SDimitry Andric bits <1> Mu2; 654fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 655fe6060f1SDimitry Andric bits <5> Vd32; 656fe6060f1SDimitry Andric let Inst{4-0} = Vd32{4-0}; 657fe6060f1SDimitry Andric bits <5> Rx32; 658fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 659fe6060f1SDimitry Andric} 660fe6060f1SDimitry Andricclass Enc_2f2f04 : OpcodeHexagon { 661fe6060f1SDimitry Andric bits <1> Ii; 662fe6060f1SDimitry Andric let Inst{5-5} = Ii{0-0}; 663fe6060f1SDimitry Andric bits <5> Vuu32; 664fe6060f1SDimitry Andric let Inst{12-8} = Vuu32{4-0}; 665fe6060f1SDimitry Andric bits <5> Rt32; 666fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 667fe6060f1SDimitry Andric bits <5> Vdd32; 668fe6060f1SDimitry Andric let Inst{4-0} = Vdd32{4-0}; 669fe6060f1SDimitry Andric} 670fe6060f1SDimitry Andricclass Enc_2fbf3c : OpcodeHexagon { 671fe6060f1SDimitry Andric bits <3> Ii; 672fe6060f1SDimitry Andric let Inst{10-8} = Ii{2-0}; 673fe6060f1SDimitry Andric bits <4> Rs16; 674fe6060f1SDimitry Andric let Inst{7-4} = Rs16{3-0}; 675fe6060f1SDimitry Andric bits <4> Rd16; 676fe6060f1SDimitry Andric let Inst{3-0} = Rd16{3-0}; 677fe6060f1SDimitry Andric} 678fe6060f1SDimitry Andricclass Enc_310ba1 : OpcodeHexagon { 679fe6060f1SDimitry Andric bits <5> Vu32; 680fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 681fe6060f1SDimitry Andric bits <5> Rtt32; 682fe6060f1SDimitry Andric let Inst{20-16} = Rtt32{4-0}; 683fe6060f1SDimitry Andric bits <5> Vx32; 684fe6060f1SDimitry Andric let Inst{4-0} = Vx32{4-0}; 685fe6060f1SDimitry Andric} 6865ffd83dbSDimitry Andricclass Enc_311abd : OpcodeHexagon { 6875ffd83dbSDimitry Andric bits <5> Ii; 6885ffd83dbSDimitry Andric let Inst{12-8} = Ii{4-0}; 6895ffd83dbSDimitry Andric bits <5> Rs32; 6905ffd83dbSDimitry Andric let Inst{20-16} = Rs32{4-0}; 6915ffd83dbSDimitry Andric bits <5> Rdd32; 6925ffd83dbSDimitry Andric let Inst{4-0} = Rdd32{4-0}; 6935ffd83dbSDimitry Andric} 694fe6060f1SDimitry Andricclass Enc_31aa6a : OpcodeHexagon { 6955ffd83dbSDimitry Andric bits <5> Ii; 696fe6060f1SDimitry Andric let Inst{6-3} = Ii{4-1}; 697fe6060f1SDimitry Andric bits <2> Pv4; 698fe6060f1SDimitry Andric let Inst{1-0} = Pv4{1-0}; 699fe6060f1SDimitry Andric bits <3> Nt8; 700fe6060f1SDimitry Andric let Inst{10-8} = Nt8{2-0}; 701fe6060f1SDimitry Andric bits <5> Rx32; 702fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 703fe6060f1SDimitry Andric} 704fe6060f1SDimitry Andricclass Enc_31db33 : OpcodeHexagon { 705fe6060f1SDimitry Andric bits <2> Qt4; 706fe6060f1SDimitry Andric let Inst{6-5} = Qt4{1-0}; 707fe6060f1SDimitry Andric bits <5> Vu32; 708fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 709fe6060f1SDimitry Andric bits <5> Vv32; 710fe6060f1SDimitry Andric let Inst{20-16} = Vv32{4-0}; 711fe6060f1SDimitry Andric bits <5> Vd32; 712fe6060f1SDimitry Andric let Inst{4-0} = Vd32{4-0}; 713fe6060f1SDimitry Andric} 714fe6060f1SDimitry Andricclass Enc_322e1b : OpcodeHexagon { 715fe6060f1SDimitry Andric bits <6> Ii; 716fe6060f1SDimitry Andric let Inst{22-21} = Ii{5-4}; 717fe6060f1SDimitry Andric let Inst{13-13} = Ii{3-3}; 718fe6060f1SDimitry Andric let Inst{7-5} = Ii{2-0}; 719fe6060f1SDimitry Andric bits <6> II; 720fe6060f1SDimitry Andric let Inst{23-23} = II{5-5}; 721fe6060f1SDimitry Andric let Inst{4-0} = II{4-0}; 7225ffd83dbSDimitry Andric bits <5> Rs32; 7235ffd83dbSDimitry Andric let Inst{20-16} = Rs32{4-0}; 7245ffd83dbSDimitry Andric bits <5> Rd32; 725fe6060f1SDimitry Andric let Inst{12-8} = Rd32{4-0}; 726fe6060f1SDimitry Andric} 727fe6060f1SDimitry Andricclass Enc_323f2d : OpcodeHexagon { 728fe6060f1SDimitry Andric bits <6> II; 729fe6060f1SDimitry Andric let Inst{11-8} = II{5-2}; 730fe6060f1SDimitry Andric let Inst{6-5} = II{1-0}; 731fe6060f1SDimitry Andric bits <5> Rd32; 7325ffd83dbSDimitry Andric let Inst{4-0} = Rd32{4-0}; 733fe6060f1SDimitry Andric bits <5> Re32; 734fe6060f1SDimitry Andric let Inst{20-16} = Re32{4-0}; 7355ffd83dbSDimitry Andric} 736fe6060f1SDimitry Andricclass Enc_329361 : OpcodeHexagon { 7375ffd83dbSDimitry Andric bits <2> Pu4; 738fe6060f1SDimitry Andric let Inst{6-5} = Pu4{1-0}; 739fe6060f1SDimitry Andric bits <5> Rss32; 740fe6060f1SDimitry Andric let Inst{20-16} = Rss32{4-0}; 741fe6060f1SDimitry Andric bits <5> Rtt32; 742fe6060f1SDimitry Andric let Inst{12-8} = Rtt32{4-0}; 7435ffd83dbSDimitry Andric bits <5> Rdd32; 7445ffd83dbSDimitry Andric let Inst{4-0} = Rdd32{4-0}; 7455ffd83dbSDimitry Andric} 746fe6060f1SDimitry Andricclass Enc_33f8ba : OpcodeHexagon { 7475ffd83dbSDimitry Andric bits <8> Ii; 748fe6060f1SDimitry Andric let Inst{12-8} = Ii{7-3}; 749fe6060f1SDimitry Andric let Inst{4-2} = Ii{2-0}; 750fe6060f1SDimitry Andric bits <5> Rx32; 751fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 7525ffd83dbSDimitry Andric} 7535ffd83dbSDimitry Andricclass Enc_3680c2 : OpcodeHexagon { 7545ffd83dbSDimitry Andric bits <7> Ii; 7555ffd83dbSDimitry Andric let Inst{11-5} = Ii{6-0}; 7565ffd83dbSDimitry Andric bits <5> Rss32; 7575ffd83dbSDimitry Andric let Inst{20-16} = Rss32{4-0}; 7585ffd83dbSDimitry Andric bits <2> Pd4; 7595ffd83dbSDimitry Andric let Inst{1-0} = Pd4{1-0}; 7605ffd83dbSDimitry Andric} 761fe6060f1SDimitry Andricclass Enc_3694bd : OpcodeHexagon { 762fe6060f1SDimitry Andric bits <11> Ii; 763fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 764fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 765fe6060f1SDimitry Andric bits <3> Ns8; 766fe6060f1SDimitry Andric let Inst{18-16} = Ns8{2-0}; 767fe6060f1SDimitry Andric bits <5> n1; 768fe6060f1SDimitry Andric let Inst{29-29} = n1{4-4}; 769fe6060f1SDimitry Andric let Inst{26-25} = n1{3-2}; 770fe6060f1SDimitry Andric let Inst{23-22} = n1{1-0}; 771fe6060f1SDimitry Andric} 772fe6060f1SDimitry Andricclass Enc_372c9d : OpcodeHexagon { 773fe6060f1SDimitry Andric bits <2> Pv4; 774fe6060f1SDimitry Andric let Inst{12-11} = Pv4{1-0}; 775fe6060f1SDimitry Andric bits <1> Mu2; 776fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 777fe6060f1SDimitry Andric bits <3> Os8; 778fe6060f1SDimitry Andric let Inst{2-0} = Os8{2-0}; 779fe6060f1SDimitry Andric bits <5> Rx32; 780fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 781fe6060f1SDimitry Andric} 782fe6060f1SDimitry Andricclass Enc_395cc4 : OpcodeHexagon { 783fe6060f1SDimitry Andric bits <7> Ii; 784fe6060f1SDimitry Andric let Inst{6-3} = Ii{6-3}; 785fe6060f1SDimitry Andric bits <1> Mu2; 786fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 787fe6060f1SDimitry Andric bits <5> Rtt32; 788fe6060f1SDimitry Andric let Inst{12-8} = Rtt32{4-0}; 789fe6060f1SDimitry Andric bits <5> Rx32; 790fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 791fe6060f1SDimitry Andric} 792fe6060f1SDimitry Andricclass Enc_397f23 : OpcodeHexagon { 793fe6060f1SDimitry Andric bits <8> Ii; 794fe6060f1SDimitry Andric let Inst{13-13} = Ii{7-7}; 795fe6060f1SDimitry Andric let Inst{7-3} = Ii{6-2}; 796fe6060f1SDimitry Andric bits <2> Pv4; 797fe6060f1SDimitry Andric let Inst{1-0} = Pv4{1-0}; 798fe6060f1SDimitry Andric bits <5> Rs32; 799fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 800fe6060f1SDimitry Andric bits <5> Rt32; 801fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 802fe6060f1SDimitry Andric} 803fe6060f1SDimitry Andricclass Enc_399e12 : OpcodeHexagon { 804fe6060f1SDimitry Andric bits <4> Rs16; 805fe6060f1SDimitry Andric let Inst{7-4} = Rs16{3-0}; 806fe6060f1SDimitry Andric bits <3> Rdd8; 807fe6060f1SDimitry Andric let Inst{2-0} = Rdd8{2-0}; 808fe6060f1SDimitry Andric} 809fe6060f1SDimitry Andricclass Enc_3a2484 : OpcodeHexagon { 810fe6060f1SDimitry Andric bits <11> Ii; 811fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 812fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 813fe6060f1SDimitry Andric bits <4> Rs16; 814fe6060f1SDimitry Andric let Inst{19-16} = Rs16{3-0}; 815fe6060f1SDimitry Andric bits <4> n1; 816fe6060f1SDimitry Andric let Inst{28-28} = n1{3-3}; 817fe6060f1SDimitry Andric let Inst{24-23} = n1{2-1}; 818fe6060f1SDimitry Andric let Inst{13-13} = n1{0-0}; 819fe6060f1SDimitry Andric} 820fe6060f1SDimitry Andricclass Enc_3a3d62 : OpcodeHexagon { 821fe6060f1SDimitry Andric bits <5> Rs32; 822fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 823fe6060f1SDimitry Andric bits <5> Rdd32; 824fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 825fe6060f1SDimitry Andric} 826fe6060f1SDimitry Andricclass Enc_3b7631 : OpcodeHexagon { 827fe6060f1SDimitry Andric bits <5> Vu32; 828fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 829fe6060f1SDimitry Andric bits <5> Vdddd32; 830fe6060f1SDimitry Andric let Inst{4-0} = Vdddd32{4-0}; 831fe6060f1SDimitry Andric bits <3> Rx8; 832fe6060f1SDimitry Andric let Inst{18-16} = Rx8{2-0}; 833fe6060f1SDimitry Andric} 834fe6060f1SDimitry Andricclass Enc_3d5b28 : OpcodeHexagon { 835fe6060f1SDimitry Andric bits <5> Rss32; 836fe6060f1SDimitry Andric let Inst{20-16} = Rss32{4-0}; 837fe6060f1SDimitry Andric bits <5> Rt32; 838fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 839fe6060f1SDimitry Andric bits <5> Rd32; 840fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 841fe6060f1SDimitry Andric} 842fe6060f1SDimitry Andricclass Enc_3d6d37 : OpcodeHexagon { 843fe6060f1SDimitry Andric bits <2> Qs4; 844fe6060f1SDimitry Andric let Inst{6-5} = Qs4{1-0}; 845fe6060f1SDimitry Andric bits <5> Rt32; 846fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 847fe6060f1SDimitry Andric bits <1> Mu2; 848fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 849fe6060f1SDimitry Andric bits <5> Vvv32; 850fe6060f1SDimitry Andric let Inst{12-8} = Vvv32{4-0}; 851fe6060f1SDimitry Andric bits <5> Vw32; 852fe6060f1SDimitry Andric let Inst{4-0} = Vw32{4-0}; 853fe6060f1SDimitry Andric} 854fe6060f1SDimitry Andricclass Enc_3d920a : OpcodeHexagon { 855fe6060f1SDimitry Andric bits <6> Ii; 856fe6060f1SDimitry Andric let Inst{8-5} = Ii{5-2}; 857fe6060f1SDimitry Andric bits <5> Rd32; 858fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 859fe6060f1SDimitry Andric bits <5> Rx32; 860fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 861fe6060f1SDimitry Andric} 862fe6060f1SDimitry Andricclass Enc_3dac0b : OpcodeHexagon { 863fe6060f1SDimitry Andric bits <2> Qt4; 864fe6060f1SDimitry Andric let Inst{6-5} = Qt4{1-0}; 865fe6060f1SDimitry Andric bits <5> Vu32; 866fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 867fe6060f1SDimitry Andric bits <5> Vv32; 868fe6060f1SDimitry Andric let Inst{20-16} = Vv32{4-0}; 869fe6060f1SDimitry Andric bits <5> Vdd32; 870fe6060f1SDimitry Andric let Inst{4-0} = Vdd32{4-0}; 871fe6060f1SDimitry Andric} 872fe6060f1SDimitry Andricclass Enc_3e3989 : OpcodeHexagon { 873fe6060f1SDimitry Andric bits <11> Ii; 874fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 875fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 876fe6060f1SDimitry Andric bits <4> Rs16; 877fe6060f1SDimitry Andric let Inst{19-16} = Rs16{3-0}; 878fe6060f1SDimitry Andric bits <6> n1; 879fe6060f1SDimitry Andric let Inst{28-28} = n1{5-5}; 880fe6060f1SDimitry Andric let Inst{25-22} = n1{4-1}; 881fe6060f1SDimitry Andric let Inst{8-8} = n1{0-0}; 882fe6060f1SDimitry Andric} 883fe6060f1SDimitry Andricclass Enc_3f97c8 : OpcodeHexagon { 884fe6060f1SDimitry Andric bits <6> Ii; 885fe6060f1SDimitry Andric let Inst{6-3} = Ii{5-2}; 886fe6060f1SDimitry Andric bits <1> Mu2; 887fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 888fe6060f1SDimitry Andric bits <3> Nt8; 889fe6060f1SDimitry Andric let Inst{10-8} = Nt8{2-0}; 890fe6060f1SDimitry Andric bits <5> Rx32; 891fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 892fe6060f1SDimitry Andric} 893fe6060f1SDimitry Andricclass Enc_3fc427 : OpcodeHexagon { 894fe6060f1SDimitry Andric bits <5> Vu32; 895fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 896fe6060f1SDimitry Andric bits <5> Vv32; 897fe6060f1SDimitry Andric let Inst{20-16} = Vv32{4-0}; 898fe6060f1SDimitry Andric bits <5> Vxx32; 899fe6060f1SDimitry Andric let Inst{4-0} = Vxx32{4-0}; 900fe6060f1SDimitry Andric} 901fe6060f1SDimitry Andricclass Enc_405228 : OpcodeHexagon { 902fe6060f1SDimitry Andric bits <11> Ii; 903fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 904fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 905fe6060f1SDimitry Andric bits <4> Rs16; 906fe6060f1SDimitry Andric let Inst{19-16} = Rs16{3-0}; 907fe6060f1SDimitry Andric bits <3> n1; 908fe6060f1SDimitry Andric let Inst{28-28} = n1{2-2}; 909fe6060f1SDimitry Andric let Inst{24-23} = n1{1-0}; 910fe6060f1SDimitry Andric} 9115ffd83dbSDimitry Andricclass Enc_412ff0 : OpcodeHexagon { 9125ffd83dbSDimitry Andric bits <5> Rss32; 9135ffd83dbSDimitry Andric let Inst{20-16} = Rss32{4-0}; 9145ffd83dbSDimitry Andric bits <5> Ru32; 9155ffd83dbSDimitry Andric let Inst{4-0} = Ru32{4-0}; 9165ffd83dbSDimitry Andric bits <5> Rxx32; 9175ffd83dbSDimitry Andric let Inst{12-8} = Rxx32{4-0}; 9185ffd83dbSDimitry Andric} 919fe6060f1SDimitry Andricclass Enc_420cf3 : OpcodeHexagon { 920fe6060f1SDimitry Andric bits <6> Ii; 921fe6060f1SDimitry Andric let Inst{22-21} = Ii{5-4}; 922fe6060f1SDimitry Andric let Inst{13-13} = Ii{3-3}; 923fe6060f1SDimitry Andric let Inst{7-5} = Ii{2-0}; 924fe6060f1SDimitry Andric bits <5> Ru32; 925fe6060f1SDimitry Andric let Inst{4-0} = Ru32{4-0}; 926fe6060f1SDimitry Andric bits <5> Rs32; 927fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 928fe6060f1SDimitry Andric bits <5> Rd32; 929fe6060f1SDimitry Andric let Inst{12-8} = Rd32{4-0}; 930fe6060f1SDimitry Andric} 931fe6060f1SDimitry Andricclass Enc_437f33 : OpcodeHexagon { 932fe6060f1SDimitry Andric bits <5> Rs32; 933fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 934fe6060f1SDimitry Andric bits <5> Rt32; 935fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 936fe6060f1SDimitry Andric bits <2> Pu4; 937fe6060f1SDimitry Andric let Inst{6-5} = Pu4{1-0}; 938fe6060f1SDimitry Andric bits <5> Rx32; 939fe6060f1SDimitry Andric let Inst{4-0} = Rx32{4-0}; 940fe6060f1SDimitry Andric} 941fe6060f1SDimitry Andricclass Enc_44215c : OpcodeHexagon { 942fe6060f1SDimitry Andric bits <6> Ii; 943fe6060f1SDimitry Andric let Inst{17-16} = Ii{5-4}; 944fe6060f1SDimitry Andric let Inst{6-3} = Ii{3-0}; 945fe6060f1SDimitry Andric bits <2> Pv4; 946fe6060f1SDimitry Andric let Inst{1-0} = Pv4{1-0}; 947fe6060f1SDimitry Andric bits <3> Nt8; 948fe6060f1SDimitry Andric let Inst{10-8} = Nt8{2-0}; 949fe6060f1SDimitry Andric} 950fe6060f1SDimitry Andricclass Enc_44271f : OpcodeHexagon { 951fe6060f1SDimitry Andric bits <5> Gs32; 952fe6060f1SDimitry Andric let Inst{20-16} = Gs32{4-0}; 953fe6060f1SDimitry Andric bits <5> Rd32; 954fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 955fe6060f1SDimitry Andric} 956fe6060f1SDimitry Andricclass Enc_44661f : OpcodeHexagon { 957fe6060f1SDimitry Andric bits <1> Mu2; 958fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 959fe6060f1SDimitry Andric bits <5> Rx32; 960fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 961fe6060f1SDimitry Andric} 962fe6060f1SDimitry Andricclass Enc_448f7f : OpcodeHexagon { 963fe6060f1SDimitry Andric bits <11> Ii; 964fe6060f1SDimitry Andric let Inst{26-25} = Ii{10-9}; 965fe6060f1SDimitry Andric let Inst{13-13} = Ii{8-8}; 966fe6060f1SDimitry Andric let Inst{7-0} = Ii{7-0}; 967fe6060f1SDimitry Andric bits <5> Rs32; 968fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 969fe6060f1SDimitry Andric bits <5> Rt32; 970fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 971fe6060f1SDimitry Andric} 972fe6060f1SDimitry Andricclass Enc_45364e : OpcodeHexagon { 973fe6060f1SDimitry Andric bits <5> Vu32; 974fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 975fe6060f1SDimitry Andric bits <5> Vv32; 976fe6060f1SDimitry Andric let Inst{20-16} = Vv32{4-0}; 977fe6060f1SDimitry Andric bits <5> Vd32; 978fe6060f1SDimitry Andric let Inst{4-0} = Vd32{4-0}; 979fe6060f1SDimitry Andric} 980fe6060f1SDimitry Andricclass Enc_454a26 : OpcodeHexagon { 981fe6060f1SDimitry Andric bits <2> Pt4; 982fe6060f1SDimitry Andric let Inst{9-8} = Pt4{1-0}; 983fe6060f1SDimitry Andric bits <2> Ps4; 984fe6060f1SDimitry Andric let Inst{17-16} = Ps4{1-0}; 985fe6060f1SDimitry Andric bits <2> Pd4; 986fe6060f1SDimitry Andric let Inst{1-0} = Pd4{1-0}; 987fe6060f1SDimitry Andric} 988fe6060f1SDimitry Andricclass Enc_46c951 : OpcodeHexagon { 989fe6060f1SDimitry Andric bits <6> Ii; 990fe6060f1SDimitry Andric let Inst{12-7} = Ii{5-0}; 991fe6060f1SDimitry Andric bits <5> II; 992fe6060f1SDimitry Andric let Inst{4-0} = II{4-0}; 993fe6060f1SDimitry Andric bits <5> Rs32; 994fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 995fe6060f1SDimitry Andric} 996fe6060f1SDimitry Andricclass Enc_47ee5e : OpcodeHexagon { 997fe6060f1SDimitry Andric bits <2> Ii; 998fe6060f1SDimitry Andric let Inst{13-13} = Ii{1-1}; 999fe6060f1SDimitry Andric let Inst{7-7} = Ii{0-0}; 1000fe6060f1SDimitry Andric bits <2> Pv4; 1001fe6060f1SDimitry Andric let Inst{6-5} = Pv4{1-0}; 1002fe6060f1SDimitry Andric bits <5> Rs32; 1003fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 1004fe6060f1SDimitry Andric bits <5> Ru32; 1005fe6060f1SDimitry Andric let Inst{12-8} = Ru32{4-0}; 1006fe6060f1SDimitry Andric bits <3> Nt8; 1007fe6060f1SDimitry Andric let Inst{2-0} = Nt8{2-0}; 1008fe6060f1SDimitry Andric} 1009fe6060f1SDimitry Andricclass Enc_47ef61 : OpcodeHexagon { 1010fe6060f1SDimitry Andric bits <3> Ii; 1011fe6060f1SDimitry Andric let Inst{7-5} = Ii{2-0}; 1012fe6060f1SDimitry Andric bits <5> Rt32; 1013fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 1014fe6060f1SDimitry Andric bits <5> Rs32; 1015fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 1016fe6060f1SDimitry Andric bits <5> Rd32; 1017fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 1018fe6060f1SDimitry Andric} 1019fe6060f1SDimitry Andricclass Enc_48b75f : OpcodeHexagon { 1020fe6060f1SDimitry Andric bits <5> Rs32; 1021fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 1022fe6060f1SDimitry Andric bits <2> Pd4; 1023fe6060f1SDimitry Andric let Inst{1-0} = Pd4{1-0}; 1024fe6060f1SDimitry Andric} 1025fe6060f1SDimitry Andricclass Enc_4aca3a : OpcodeHexagon { 1026fe6060f1SDimitry Andric bits <11> Ii; 1027fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 1028fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 1029fe6060f1SDimitry Andric bits <3> Ns8; 1030fe6060f1SDimitry Andric let Inst{18-16} = Ns8{2-0}; 1031fe6060f1SDimitry Andric bits <3> n1; 1032fe6060f1SDimitry Andric let Inst{29-29} = n1{2-2}; 1033fe6060f1SDimitry Andric let Inst{26-25} = n1{1-0}; 1034fe6060f1SDimitry Andric} 1035fe6060f1SDimitry Andricclass Enc_4b39e4 : OpcodeHexagon { 1036fe6060f1SDimitry Andric bits <3> Ii; 1037fe6060f1SDimitry Andric let Inst{7-5} = Ii{2-0}; 1038fe6060f1SDimitry Andric bits <5> Vu32; 1039fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 1040fe6060f1SDimitry Andric bits <5> Vv32; 1041fe6060f1SDimitry Andric let Inst{20-16} = Vv32{4-0}; 1042fe6060f1SDimitry Andric bits <5> Vdd32; 1043fe6060f1SDimitry Andric let Inst{4-0} = Vdd32{4-0}; 1044fe6060f1SDimitry Andric} 1045fe6060f1SDimitry Andricclass Enc_4dc228 : OpcodeHexagon { 1046fe6060f1SDimitry Andric bits <9> Ii; 1047fe6060f1SDimitry Andric let Inst{12-8} = Ii{8-4}; 1048fe6060f1SDimitry Andric let Inst{4-3} = Ii{3-2}; 1049fe6060f1SDimitry Andric bits <10> II; 1050fe6060f1SDimitry Andric let Inst{20-16} = II{9-5}; 1051fe6060f1SDimitry Andric let Inst{7-5} = II{4-2}; 1052fe6060f1SDimitry Andric let Inst{1-0} = II{1-0}; 1053fe6060f1SDimitry Andric} 1054fe6060f1SDimitry Andricclass Enc_4df4e9 : OpcodeHexagon { 1055fe6060f1SDimitry Andric bits <11> Ii; 1056fe6060f1SDimitry Andric let Inst{26-25} = Ii{10-9}; 1057fe6060f1SDimitry Andric let Inst{13-13} = Ii{8-8}; 1058fe6060f1SDimitry Andric let Inst{7-0} = Ii{7-0}; 1059fe6060f1SDimitry Andric bits <5> Rs32; 1060fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 1061fe6060f1SDimitry Andric bits <3> Nt8; 1062fe6060f1SDimitry Andric let Inst{10-8} = Nt8{2-0}; 1063fe6060f1SDimitry Andric} 1064fe6060f1SDimitry Andricclass Enc_4dff07 : OpcodeHexagon { 1065fe6060f1SDimitry Andric bits <2> Qv4; 1066fe6060f1SDimitry Andric let Inst{12-11} = Qv4{1-0}; 1067fe6060f1SDimitry Andric bits <1> Mu2; 1068fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 1069fe6060f1SDimitry Andric bits <5> Vs32; 1070fe6060f1SDimitry Andric let Inst{4-0} = Vs32{4-0}; 1071fe6060f1SDimitry Andric bits <5> Rx32; 1072fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 1073fe6060f1SDimitry Andric} 1074fe6060f1SDimitry Andricclass Enc_4e4a80 : OpcodeHexagon { 1075fe6060f1SDimitry Andric bits <2> Qs4; 1076fe6060f1SDimitry Andric let Inst{6-5} = Qs4{1-0}; 1077fe6060f1SDimitry Andric bits <5> Rt32; 1078fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 1079fe6060f1SDimitry Andric bits <1> Mu2; 1080fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 1081fe6060f1SDimitry Andric bits <5> Vvv32; 1082fe6060f1SDimitry Andric let Inst{4-0} = Vvv32{4-0}; 1083fe6060f1SDimitry Andric} 1084fe6060f1SDimitry Andricclass Enc_4f4ed7 : OpcodeHexagon { 1085fe6060f1SDimitry Andric bits <18> Ii; 1086fe6060f1SDimitry Andric let Inst{26-25} = Ii{17-16}; 1087fe6060f1SDimitry Andric let Inst{20-16} = Ii{15-11}; 1088fe6060f1SDimitry Andric let Inst{13-5} = Ii{10-2}; 1089fe6060f1SDimitry Andric bits <5> Rd32; 1090fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 1091fe6060f1SDimitry Andric} 1092fe6060f1SDimitry Andricclass Enc_4f677b : OpcodeHexagon { 1093fe6060f1SDimitry Andric bits <2> Ii; 1094fe6060f1SDimitry Andric let Inst{13-13} = Ii{1-1}; 1095fe6060f1SDimitry Andric let Inst{7-7} = Ii{0-0}; 1096fe6060f1SDimitry Andric bits <6> II; 1097fe6060f1SDimitry Andric let Inst{11-8} = II{5-2}; 1098fe6060f1SDimitry Andric let Inst{6-5} = II{1-0}; 1099fe6060f1SDimitry Andric bits <5> Rt32; 1100fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 1101fe6060f1SDimitry Andric bits <5> Rd32; 1102fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 1103fe6060f1SDimitry Andric} 1104fe6060f1SDimitry Andricclass Enc_500cb0 : OpcodeHexagon { 1105fe6060f1SDimitry Andric bits <5> Vu32; 1106fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 1107fe6060f1SDimitry Andric bits <5> Vxx32; 1108fe6060f1SDimitry Andric let Inst{4-0} = Vxx32{4-0}; 1109fe6060f1SDimitry Andric} 1110fe6060f1SDimitry Andricclass Enc_509701 : OpcodeHexagon { 1111fe6060f1SDimitry Andric bits <19> Ii; 1112fe6060f1SDimitry Andric let Inst{26-25} = Ii{18-17}; 1113fe6060f1SDimitry Andric let Inst{20-16} = Ii{16-12}; 1114fe6060f1SDimitry Andric let Inst{13-5} = Ii{11-3}; 1115fe6060f1SDimitry Andric bits <5> Rdd32; 1116fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 1117fe6060f1SDimitry Andric} 1118fe6060f1SDimitry Andricclass Enc_50b5ac : OpcodeHexagon { 1119fe6060f1SDimitry Andric bits <6> Ii; 1120fe6060f1SDimitry Andric let Inst{17-16} = Ii{5-4}; 1121fe6060f1SDimitry Andric let Inst{6-3} = Ii{3-0}; 1122fe6060f1SDimitry Andric bits <2> Pv4; 1123fe6060f1SDimitry Andric let Inst{1-0} = Pv4{1-0}; 1124fe6060f1SDimitry Andric bits <5> Rtt32; 1125fe6060f1SDimitry Andric let Inst{12-8} = Rtt32{4-0}; 1126fe6060f1SDimitry Andric} 1127fe6060f1SDimitry Andricclass Enc_50e578 : OpcodeHexagon { 1128fe6060f1SDimitry Andric bits <5> Vu32; 1129fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 1130fe6060f1SDimitry Andric bits <5> Rs32; 1131fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 1132fe6060f1SDimitry Andric bits <5> Rd32; 1133fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 1134fe6060f1SDimitry Andric} 1135fe6060f1SDimitry Andricclass Enc_5138b3 : OpcodeHexagon { 1136fe6060f1SDimitry Andric bits <5> Vu32; 1137fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 1138fe6060f1SDimitry Andric bits <5> Rt32; 1139fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 1140fe6060f1SDimitry Andric bits <5> Vx32; 1141fe6060f1SDimitry Andric let Inst{4-0} = Vx32{4-0}; 1142fe6060f1SDimitry Andric} 1143fe6060f1SDimitry Andricclass Enc_51436c : OpcodeHexagon { 1144fe6060f1SDimitry Andric bits <16> Ii; 1145fe6060f1SDimitry Andric let Inst{23-22} = Ii{15-14}; 1146fe6060f1SDimitry Andric let Inst{13-0} = Ii{13-0}; 1147fe6060f1SDimitry Andric bits <5> Rx32; 1148fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 1149fe6060f1SDimitry Andric} 1150fe6060f1SDimitry Andricclass Enc_51635c : OpcodeHexagon { 1151fe6060f1SDimitry Andric bits <7> Ii; 1152fe6060f1SDimitry Andric let Inst{8-4} = Ii{6-2}; 1153fe6060f1SDimitry Andric bits <4> Rd16; 1154fe6060f1SDimitry Andric let Inst{3-0} = Rd16{3-0}; 1155fe6060f1SDimitry Andric} 1156fe6060f1SDimitry Andricclass Enc_527412 : OpcodeHexagon { 1157fe6060f1SDimitry Andric bits <2> Ps4; 1158fe6060f1SDimitry Andric let Inst{17-16} = Ps4{1-0}; 1159fe6060f1SDimitry Andric bits <2> Pt4; 1160fe6060f1SDimitry Andric let Inst{9-8} = Pt4{1-0}; 1161fe6060f1SDimitry Andric bits <5> Rd32; 1162fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 1163fe6060f1SDimitry Andric} 1164fe6060f1SDimitry Andricclass Enc_52a5dd : OpcodeHexagon { 1165fe6060f1SDimitry Andric bits <4> Ii; 1166fe6060f1SDimitry Andric let Inst{6-3} = Ii{3-0}; 1167fe6060f1SDimitry Andric bits <2> Pv4; 1168fe6060f1SDimitry Andric let Inst{1-0} = Pv4{1-0}; 1169fe6060f1SDimitry Andric bits <3> Nt8; 1170fe6060f1SDimitry Andric let Inst{10-8} = Nt8{2-0}; 1171fe6060f1SDimitry Andric bits <5> Rx32; 1172fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 1173fe6060f1SDimitry Andric} 1174fe6060f1SDimitry Andricclass Enc_53dca9 : OpcodeHexagon { 1175fe6060f1SDimitry Andric bits <6> Ii; 1176fe6060f1SDimitry Andric let Inst{11-8} = Ii{5-2}; 1177fe6060f1SDimitry Andric bits <4> Rs16; 1178fe6060f1SDimitry Andric let Inst{7-4} = Rs16{3-0}; 1179fe6060f1SDimitry Andric bits <4> Rd16; 1180fe6060f1SDimitry Andric let Inst{3-0} = Rd16{3-0}; 1181fe6060f1SDimitry Andric} 1182fe6060f1SDimitry Andricclass Enc_541f26 : OpcodeHexagon { 1183fe6060f1SDimitry Andric bits <18> Ii; 1184fe6060f1SDimitry Andric let Inst{26-25} = Ii{17-16}; 1185fe6060f1SDimitry Andric let Inst{20-16} = Ii{15-11}; 1186fe6060f1SDimitry Andric let Inst{13-13} = Ii{10-10}; 1187fe6060f1SDimitry Andric let Inst{7-0} = Ii{9-2}; 1188fe6060f1SDimitry Andric bits <5> Rt32; 1189fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 1190fe6060f1SDimitry Andric} 1191fe6060f1SDimitry Andricclass Enc_55355c : OpcodeHexagon { 1192fe6060f1SDimitry Andric bits <2> Ii; 1193fe6060f1SDimitry Andric let Inst{13-13} = Ii{1-1}; 1194fe6060f1SDimitry Andric let Inst{7-7} = Ii{0-0}; 1195fe6060f1SDimitry Andric bits <5> Rs32; 1196fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 1197fe6060f1SDimitry Andric bits <5> Ru32; 1198fe6060f1SDimitry Andric let Inst{12-8} = Ru32{4-0}; 1199fe6060f1SDimitry Andric bits <5> Rtt32; 1200fe6060f1SDimitry Andric let Inst{4-0} = Rtt32{4-0}; 1201fe6060f1SDimitry Andric} 1202fe6060f1SDimitry Andricclass Enc_569cfe : OpcodeHexagon { 1203fe6060f1SDimitry Andric bits <5> Rt32; 1204fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 1205fe6060f1SDimitry Andric bits <5> Vx32; 1206fe6060f1SDimitry Andric let Inst{4-0} = Vx32{4-0}; 1207fe6060f1SDimitry Andric} 1208fe6060f1SDimitry Andricclass Enc_57a33e : OpcodeHexagon { 1209fe6060f1SDimitry Andric bits <9> Ii; 1210fe6060f1SDimitry Andric let Inst{13-13} = Ii{8-8}; 1211fe6060f1SDimitry Andric let Inst{7-3} = Ii{7-3}; 1212fe6060f1SDimitry Andric bits <2> Pv4; 1213fe6060f1SDimitry Andric let Inst{1-0} = Pv4{1-0}; 1214fe6060f1SDimitry Andric bits <5> Rs32; 1215fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 1216fe6060f1SDimitry Andric bits <5> Rtt32; 1217fe6060f1SDimitry Andric let Inst{12-8} = Rtt32{4-0}; 1218fe6060f1SDimitry Andric} 1219fe6060f1SDimitry Andricclass Enc_585242 : OpcodeHexagon { 1220fe6060f1SDimitry Andric bits <6> Ii; 1221fe6060f1SDimitry Andric let Inst{13-13} = Ii{5-5}; 1222fe6060f1SDimitry Andric let Inst{7-3} = Ii{4-0}; 1223fe6060f1SDimitry Andric bits <2> Pv4; 1224fe6060f1SDimitry Andric let Inst{1-0} = Pv4{1-0}; 1225fe6060f1SDimitry Andric bits <5> Rs32; 1226fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 1227fe6060f1SDimitry Andric bits <3> Nt8; 1228fe6060f1SDimitry Andric let Inst{10-8} = Nt8{2-0}; 1229fe6060f1SDimitry Andric} 1230fe6060f1SDimitry Andricclass Enc_58a8bf : OpcodeHexagon { 1231fe6060f1SDimitry Andric bits <3> Ii; 1232fe6060f1SDimitry Andric let Inst{10-8} = Ii{2-0}; 1233fe6060f1SDimitry Andric bits <2> Pv4; 1234fe6060f1SDimitry Andric let Inst{12-11} = Pv4{1-0}; 1235fe6060f1SDimitry Andric bits <5> Vd32; 1236fe6060f1SDimitry Andric let Inst{4-0} = Vd32{4-0}; 1237fe6060f1SDimitry Andric bits <5> Rx32; 1238fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 1239fe6060f1SDimitry Andric} 1240fe6060f1SDimitry Andricclass Enc_5a18b3 : OpcodeHexagon { 1241fe6060f1SDimitry Andric bits <11> Ii; 1242fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 1243fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 1244fe6060f1SDimitry Andric bits <3> Ns8; 1245fe6060f1SDimitry Andric let Inst{18-16} = Ns8{2-0}; 1246fe6060f1SDimitry Andric bits <5> n1; 1247fe6060f1SDimitry Andric let Inst{29-29} = n1{4-4}; 1248fe6060f1SDimitry Andric let Inst{26-25} = n1{3-2}; 1249fe6060f1SDimitry Andric let Inst{22-22} = n1{1-1}; 1250fe6060f1SDimitry Andric let Inst{13-13} = n1{0-0}; 1251fe6060f1SDimitry Andric} 1252fe6060f1SDimitry Andricclass Enc_5ab2be : OpcodeHexagon { 1253fe6060f1SDimitry Andric bits <5> Rs32; 1254fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 1255fe6060f1SDimitry Andric bits <5> Rt32; 1256fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 1257fe6060f1SDimitry Andric bits <5> Rd32; 1258fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 1259fe6060f1SDimitry Andric} 1260fe6060f1SDimitry Andricclass Enc_5bdd42 : OpcodeHexagon { 1261fe6060f1SDimitry Andric bits <7> Ii; 1262fe6060f1SDimitry Andric let Inst{8-5} = Ii{6-3}; 1263fe6060f1SDimitry Andric bits <5> Rdd32; 1264fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 1265fe6060f1SDimitry Andric bits <5> Rx32; 1266fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 1267fe6060f1SDimitry Andric} 1268fe6060f1SDimitry Andricclass Enc_5c124a : OpcodeHexagon { 1269fe6060f1SDimitry Andric bits <19> Ii; 1270fe6060f1SDimitry Andric let Inst{26-25} = Ii{18-17}; 1271fe6060f1SDimitry Andric let Inst{20-16} = Ii{16-12}; 1272fe6060f1SDimitry Andric let Inst{13-13} = Ii{11-11}; 1273fe6060f1SDimitry Andric let Inst{7-0} = Ii{10-3}; 1274fe6060f1SDimitry Andric bits <5> Rtt32; 1275fe6060f1SDimitry Andric let Inst{12-8} = Rtt32{4-0}; 1276fe6060f1SDimitry Andric} 1277fe6060f1SDimitry Andricclass Enc_5ccba9 : OpcodeHexagon { 1278fe6060f1SDimitry Andric bits <8> Ii; 1279fe6060f1SDimitry Andric let Inst{12-7} = Ii{7-2}; 1280fe6060f1SDimitry Andric bits <6> II; 1281fe6060f1SDimitry Andric let Inst{13-13} = II{5-5}; 1282fe6060f1SDimitry Andric let Inst{4-0} = II{4-0}; 1283fe6060f1SDimitry Andric bits <2> Pv4; 1284fe6060f1SDimitry Andric let Inst{6-5} = Pv4{1-0}; 1285fe6060f1SDimitry Andric bits <5> Rs32; 1286fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 1287fe6060f1SDimitry Andric} 1288fe6060f1SDimitry Andricclass Enc_5cd7e9 : OpcodeHexagon { 1289fe6060f1SDimitry Andric bits <12> Ii; 1290fe6060f1SDimitry Andric let Inst{26-25} = Ii{11-10}; 1291fe6060f1SDimitry Andric let Inst{13-5} = Ii{9-1}; 1292fe6060f1SDimitry Andric bits <5> Rs32; 1293fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 1294fe6060f1SDimitry Andric bits <5> Ryy32; 1295fe6060f1SDimitry Andric let Inst{4-0} = Ryy32{4-0}; 1296fe6060f1SDimitry Andric} 1297fe6060f1SDimitry Andricclass Enc_5d6c34 : OpcodeHexagon { 1298fe6060f1SDimitry Andric bits <6> Ii; 1299fe6060f1SDimitry Andric let Inst{13-8} = Ii{5-0}; 1300fe6060f1SDimitry Andric bits <5> Rs32; 1301fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 1302fe6060f1SDimitry Andric bits <2> Pd4; 1303fe6060f1SDimitry Andric let Inst{1-0} = Pd4{1-0}; 1304fe6060f1SDimitry Andric} 1305fe6060f1SDimitry Andricclass Enc_5de85f : OpcodeHexagon { 1306fe6060f1SDimitry Andric bits <11> Ii; 1307fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 1308fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 1309fe6060f1SDimitry Andric bits <5> Rt32; 1310fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 1311fe6060f1SDimitry Andric bits <3> Ns8; 1312fe6060f1SDimitry Andric let Inst{18-16} = Ns8{2-0}; 1313fe6060f1SDimitry Andric} 1314fe6060f1SDimitry Andricclass Enc_5e2823 : OpcodeHexagon { 1315fe6060f1SDimitry Andric bits <5> Rs32; 1316fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 1317fe6060f1SDimitry Andric bits <5> Rd32; 1318fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 1319fe6060f1SDimitry Andric} 1320fe6060f1SDimitry Andricclass Enc_5e8512 : OpcodeHexagon { 1321fe6060f1SDimitry Andric bits <5> Vu32; 1322fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 1323fe6060f1SDimitry Andric bits <5> Rt32; 1324fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 1325fe6060f1SDimitry Andric bits <5> Vxx32; 1326fe6060f1SDimitry Andric let Inst{4-0} = Vxx32{4-0}; 1327fe6060f1SDimitry Andric} 1328fe6060f1SDimitry Andricclass Enc_5e87ce : OpcodeHexagon { 1329fe6060f1SDimitry Andric bits <16> Ii; 1330fe6060f1SDimitry Andric let Inst{23-22} = Ii{15-14}; 1331fe6060f1SDimitry Andric let Inst{20-16} = Ii{13-9}; 1332fe6060f1SDimitry Andric let Inst{13-5} = Ii{8-0}; 1333fe6060f1SDimitry Andric bits <5> Rd32; 1334fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 1335fe6060f1SDimitry Andric} 1336fe6060f1SDimitry Andricclass Enc_5eac98 : OpcodeHexagon { 1337fe6060f1SDimitry Andric bits <6> Ii; 1338fe6060f1SDimitry Andric let Inst{13-8} = Ii{5-0}; 1339fe6060f1SDimitry Andric bits <5> Rss32; 1340fe6060f1SDimitry Andric let Inst{20-16} = Rss32{4-0}; 1341fe6060f1SDimitry Andric bits <5> Rdd32; 1342fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 1343fe6060f1SDimitry Andric} 1344fe6060f1SDimitry Andricclass Enc_607661 : OpcodeHexagon { 1345fe6060f1SDimitry Andric bits <6> Ii; 1346fe6060f1SDimitry Andric let Inst{12-7} = Ii{5-0}; 1347fe6060f1SDimitry Andric bits <5> Rd32; 1348fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 1349fe6060f1SDimitry Andric} 1350fe6060f1SDimitry Andricclass Enc_6185fe : OpcodeHexagon { 1351fe6060f1SDimitry Andric bits <2> Ii; 1352fe6060f1SDimitry Andric let Inst{13-13} = Ii{1-1}; 1353fe6060f1SDimitry Andric let Inst{7-7} = Ii{0-0}; 1354fe6060f1SDimitry Andric bits <6> II; 1355fe6060f1SDimitry Andric let Inst{11-8} = II{5-2}; 1356fe6060f1SDimitry Andric let Inst{6-5} = II{1-0}; 1357fe6060f1SDimitry Andric bits <5> Rt32; 1358fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 1359fe6060f1SDimitry Andric bits <5> Rdd32; 1360fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 1361fe6060f1SDimitry Andric} 1362fe6060f1SDimitry Andricclass Enc_61f0b0 : OpcodeHexagon { 1363fe6060f1SDimitry Andric bits <5> Rs32; 1364fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 1365fe6060f1SDimitry Andric bits <5> Rt32; 1366fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 1367fe6060f1SDimitry Andric bits <5> Rxx32; 1368fe6060f1SDimitry Andric let Inst{4-0} = Rxx32{4-0}; 1369fe6060f1SDimitry Andric} 1370fe6060f1SDimitry Andricclass Enc_621fba : OpcodeHexagon { 1371fe6060f1SDimitry Andric bits <5> Rs32; 1372fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 1373fe6060f1SDimitry Andric bits <5> Gd32; 1374fe6060f1SDimitry Andric let Inst{4-0} = Gd32{4-0}; 1375fe6060f1SDimitry Andric} 1376fe6060f1SDimitry Andricclass Enc_625deb : OpcodeHexagon { 1377fe6060f1SDimitry Andric bits <4> Ii; 1378fe6060f1SDimitry Andric let Inst{10-8} = Ii{3-1}; 1379fe6060f1SDimitry Andric bits <4> Rs16; 1380fe6060f1SDimitry Andric let Inst{7-4} = Rs16{3-0}; 1381fe6060f1SDimitry Andric bits <4> Rt16; 1382fe6060f1SDimitry Andric let Inst{3-0} = Rt16{3-0}; 1383fe6060f1SDimitry Andric} 1384fe6060f1SDimitry Andricclass Enc_6339d5 : OpcodeHexagon { 1385fe6060f1SDimitry Andric bits <2> Ii; 1386fe6060f1SDimitry Andric let Inst{13-13} = Ii{1-1}; 1387fe6060f1SDimitry Andric let Inst{7-7} = Ii{0-0}; 1388fe6060f1SDimitry Andric bits <2> Pv4; 1389fe6060f1SDimitry Andric let Inst{6-5} = Pv4{1-0}; 1390fe6060f1SDimitry Andric bits <5> Rs32; 1391fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 1392fe6060f1SDimitry Andric bits <5> Ru32; 1393fe6060f1SDimitry Andric let Inst{12-8} = Ru32{4-0}; 1394fe6060f1SDimitry Andric bits <5> Rt32; 1395fe6060f1SDimitry Andric let Inst{4-0} = Rt32{4-0}; 1396fe6060f1SDimitry Andric} 1397fe6060f1SDimitry Andricclass Enc_63eaeb : OpcodeHexagon { 1398fe6060f1SDimitry Andric bits <2> Ii; 1399fe6060f1SDimitry Andric let Inst{1-0} = Ii{1-0}; 1400fe6060f1SDimitry Andric bits <4> Rs16; 1401fe6060f1SDimitry Andric let Inst{7-4} = Rs16{3-0}; 1402fe6060f1SDimitry Andric} 1403fe6060f1SDimitry Andricclass Enc_6413b6 : OpcodeHexagon { 1404fe6060f1SDimitry Andric bits <11> Ii; 1405fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 1406fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 1407fe6060f1SDimitry Andric bits <3> Ns8; 1408fe6060f1SDimitry Andric let Inst{18-16} = Ns8{2-0}; 1409fe6060f1SDimitry Andric bits <5> n1; 1410fe6060f1SDimitry Andric let Inst{29-29} = n1{4-4}; 1411fe6060f1SDimitry Andric let Inst{26-25} = n1{3-2}; 1412fe6060f1SDimitry Andric let Inst{23-23} = n1{1-1}; 1413fe6060f1SDimitry Andric let Inst{13-13} = n1{0-0}; 1414fe6060f1SDimitry Andric} 1415fe6060f1SDimitry Andricclass Enc_645d54 : OpcodeHexagon { 1416fe6060f1SDimitry Andric bits <2> Ii; 1417fe6060f1SDimitry Andric let Inst{13-13} = Ii{1-1}; 1418fe6060f1SDimitry Andric let Inst{5-5} = Ii{0-0}; 1419fe6060f1SDimitry Andric bits <5> Rss32; 1420fe6060f1SDimitry Andric let Inst{20-16} = Rss32{4-0}; 1421fe6060f1SDimitry Andric bits <5> Rt32; 1422fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 1423fe6060f1SDimitry Andric bits <5> Rdd32; 1424fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 1425fe6060f1SDimitry Andric} 1426fe6060f1SDimitry Andricclass Enc_65d691 : OpcodeHexagon { 1427fe6060f1SDimitry Andric bits <2> Ps4; 1428fe6060f1SDimitry Andric let Inst{17-16} = Ps4{1-0}; 1429fe6060f1SDimitry Andric bits <2> Pd4; 1430fe6060f1SDimitry Andric let Inst{1-0} = Pd4{1-0}; 1431fe6060f1SDimitry Andric} 1432fe6060f1SDimitry Andricclass Enc_65f095 : OpcodeHexagon { 1433fe6060f1SDimitry Andric bits <6> Ii; 1434fe6060f1SDimitry Andric let Inst{6-3} = Ii{5-2}; 1435fe6060f1SDimitry Andric bits <2> Pv4; 1436fe6060f1SDimitry Andric let Inst{1-0} = Pv4{1-0}; 1437fe6060f1SDimitry Andric bits <3> Nt8; 1438fe6060f1SDimitry Andric let Inst{10-8} = Nt8{2-0}; 1439fe6060f1SDimitry Andric bits <5> Rx32; 1440fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 1441fe6060f1SDimitry Andric} 1442fe6060f1SDimitry Andricclass Enc_667b39 : OpcodeHexagon { 1443fe6060f1SDimitry Andric bits <5> Css32; 1444fe6060f1SDimitry Andric let Inst{20-16} = Css32{4-0}; 1445fe6060f1SDimitry Andric bits <5> Rdd32; 1446fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 1447fe6060f1SDimitry Andric} 1448fe6060f1SDimitry Andricclass Enc_668704 : OpcodeHexagon { 1449fe6060f1SDimitry Andric bits <11> Ii; 1450fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 1451fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 1452fe6060f1SDimitry Andric bits <4> Rs16; 1453fe6060f1SDimitry Andric let Inst{19-16} = Rs16{3-0}; 1454fe6060f1SDimitry Andric bits <5> n1; 1455fe6060f1SDimitry Andric let Inst{28-28} = n1{4-4}; 1456fe6060f1SDimitry Andric let Inst{25-22} = n1{3-0}; 1457fe6060f1SDimitry Andric} 1458fe6060f1SDimitry Andricclass Enc_66bce1 : OpcodeHexagon { 1459fe6060f1SDimitry Andric bits <11> Ii; 1460fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 1461fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 1462fe6060f1SDimitry Andric bits <4> Rs16; 1463fe6060f1SDimitry Andric let Inst{19-16} = Rs16{3-0}; 1464fe6060f1SDimitry Andric bits <4> Rd16; 1465fe6060f1SDimitry Andric let Inst{11-8} = Rd16{3-0}; 1466fe6060f1SDimitry Andric} 1467fe6060f1SDimitry Andricclass Enc_690862 : OpcodeHexagon { 1468fe6060f1SDimitry Andric bits <13> Ii; 1469fe6060f1SDimitry Andric let Inst{26-25} = Ii{12-11}; 1470fe6060f1SDimitry Andric let Inst{13-13} = Ii{10-10}; 1471fe6060f1SDimitry Andric let Inst{7-0} = Ii{9-2}; 1472fe6060f1SDimitry Andric bits <5> Rs32; 1473fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 1474fe6060f1SDimitry Andric bits <3> Nt8; 1475fe6060f1SDimitry Andric let Inst{10-8} = Nt8{2-0}; 1476fe6060f1SDimitry Andric} 1477fe6060f1SDimitry Andricclass Enc_691712 : OpcodeHexagon { 1478fe6060f1SDimitry Andric bits <2> Pv4; 1479fe6060f1SDimitry Andric let Inst{12-11} = Pv4{1-0}; 1480fe6060f1SDimitry Andric bits <1> Mu2; 1481fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 1482fe6060f1SDimitry Andric bits <5> Rx32; 1483fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 1484fe6060f1SDimitry Andric} 1485fe6060f1SDimitry Andricclass Enc_69d63b : OpcodeHexagon { 1486fe6060f1SDimitry Andric bits <11> Ii; 1487fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 1488fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 1489fe6060f1SDimitry Andric bits <3> Ns8; 1490fe6060f1SDimitry Andric let Inst{18-16} = Ns8{2-0}; 1491fe6060f1SDimitry Andric} 1492fe6060f1SDimitry Andricclass Enc_6a5972 : OpcodeHexagon { 1493fe6060f1SDimitry Andric bits <11> Ii; 1494fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 1495fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 1496fe6060f1SDimitry Andric bits <4> Rs16; 1497fe6060f1SDimitry Andric let Inst{19-16} = Rs16{3-0}; 1498fe6060f1SDimitry Andric bits <4> Rt16; 1499fe6060f1SDimitry Andric let Inst{11-8} = Rt16{3-0}; 1500fe6060f1SDimitry Andric} 1501fe6060f1SDimitry Andricclass Enc_6b197f : OpcodeHexagon { 1502fe6060f1SDimitry Andric bits <4> Ii; 1503fe6060f1SDimitry Andric let Inst{8-5} = Ii{3-0}; 1504fe6060f1SDimitry Andric bits <5> Ryy32; 1505fe6060f1SDimitry Andric let Inst{4-0} = Ryy32{4-0}; 1506fe6060f1SDimitry Andric bits <5> Rx32; 1507fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 1508fe6060f1SDimitry Andric} 1509fe6060f1SDimitry Andricclass Enc_6baed4 : OpcodeHexagon { 1510fe6060f1SDimitry Andric bits <3> Ii; 1511fe6060f1SDimitry Andric let Inst{10-8} = Ii{2-0}; 1512fe6060f1SDimitry Andric bits <2> Pv4; 1513fe6060f1SDimitry Andric let Inst{12-11} = Pv4{1-0}; 1514fe6060f1SDimitry Andric bits <5> Rx32; 1515fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 1516fe6060f1SDimitry Andric} 1517fe6060f1SDimitry Andricclass Enc_6c9440 : OpcodeHexagon { 1518fe6060f1SDimitry Andric bits <10> Ii; 1519fe6060f1SDimitry Andric let Inst{21-21} = Ii{9-9}; 1520fe6060f1SDimitry Andric let Inst{13-5} = Ii{8-0}; 1521fe6060f1SDimitry Andric bits <5> Rd32; 1522fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 1523fe6060f1SDimitry Andric} 1524fe6060f1SDimitry Andricclass Enc_6c9ee0 : OpcodeHexagon { 1525fe6060f1SDimitry Andric bits <3> Ii; 1526fe6060f1SDimitry Andric let Inst{10-8} = Ii{2-0}; 1527fe6060f1SDimitry Andric bits <5> Rx32; 1528fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 1529fe6060f1SDimitry Andric} 1530fe6060f1SDimitry Andricclass Enc_6f70ca : OpcodeHexagon { 1531fe6060f1SDimitry Andric bits <8> Ii; 1532fe6060f1SDimitry Andric let Inst{8-4} = Ii{7-3}; 1533fe6060f1SDimitry Andric} 1534fe6060f1SDimitry Andricclass Enc_6f83e7 : OpcodeHexagon { 1535fe6060f1SDimitry Andric bits <2> Qv4; 1536fe6060f1SDimitry Andric let Inst{23-22} = Qv4{1-0}; 1537fe6060f1SDimitry Andric bits <5> Vd32; 1538fe6060f1SDimitry Andric let Inst{4-0} = Vd32{4-0}; 1539fe6060f1SDimitry Andric} 1540fe6060f1SDimitry Andricclass Enc_70b24b : OpcodeHexagon { 1541fe6060f1SDimitry Andric bits <6> Ii; 1542fe6060f1SDimitry Andric let Inst{8-5} = Ii{5-2}; 1543fe6060f1SDimitry Andric bits <1> Mu2; 1544fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 1545fe6060f1SDimitry Andric bits <5> Rdd32; 1546fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 1547fe6060f1SDimitry Andric bits <5> Rx32; 1548fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 1549fe6060f1SDimitry Andric} 1550fe6060f1SDimitry Andricclass Enc_70fb07 : OpcodeHexagon { 1551fe6060f1SDimitry Andric bits <6> Ii; 1552fe6060f1SDimitry Andric let Inst{13-8} = Ii{5-0}; 1553fe6060f1SDimitry Andric bits <5> Rss32; 1554fe6060f1SDimitry Andric let Inst{20-16} = Rss32{4-0}; 1555fe6060f1SDimitry Andric bits <5> Rxx32; 1556fe6060f1SDimitry Andric let Inst{4-0} = Rxx32{4-0}; 1557fe6060f1SDimitry Andric} 1558fe6060f1SDimitry Andricclass Enc_71bb9b : OpcodeHexagon { 1559fe6060f1SDimitry Andric bits <5> Vu32; 1560fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 1561fe6060f1SDimitry Andric bits <5> Vv32; 1562fe6060f1SDimitry Andric let Inst{20-16} = Vv32{4-0}; 1563fe6060f1SDimitry Andric bits <5> Vdd32; 1564fe6060f1SDimitry Andric let Inst{4-0} = Vdd32{4-0}; 1565fe6060f1SDimitry Andric} 1566fe6060f1SDimitry Andricclass Enc_71f1b4 : OpcodeHexagon { 1567fe6060f1SDimitry Andric bits <6> Ii; 1568fe6060f1SDimitry Andric let Inst{8-5} = Ii{5-2}; 1569fe6060f1SDimitry Andric bits <5> Rdd32; 1570fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 1571fe6060f1SDimitry Andric bits <5> Rx32; 1572fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 1573fe6060f1SDimitry Andric} 1574fe6060f1SDimitry Andricclass Enc_7222b7 : OpcodeHexagon { 1575fe6060f1SDimitry Andric bits <5> Rt32; 1576fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 1577fe6060f1SDimitry Andric bits <2> Qd4; 1578fe6060f1SDimitry Andric let Inst{1-0} = Qd4{1-0}; 1579fe6060f1SDimitry Andric} 1580fe6060f1SDimitry Andricclass Enc_724154 : OpcodeHexagon { 1581fe6060f1SDimitry Andric bits <6> II; 1582fe6060f1SDimitry Andric let Inst{5-0} = II{5-0}; 1583fe6060f1SDimitry Andric bits <3> Nt8; 1584fe6060f1SDimitry Andric let Inst{10-8} = Nt8{2-0}; 1585fe6060f1SDimitry Andric bits <5> Re32; 1586fe6060f1SDimitry Andric let Inst{20-16} = Re32{4-0}; 1587fe6060f1SDimitry Andric} 1588fe6060f1SDimitry Andricclass Enc_729ff7 : OpcodeHexagon { 1589fe6060f1SDimitry Andric bits <3> Ii; 1590fe6060f1SDimitry Andric let Inst{7-5} = Ii{2-0}; 1591fe6060f1SDimitry Andric bits <5> Rtt32; 1592fe6060f1SDimitry Andric let Inst{12-8} = Rtt32{4-0}; 1593fe6060f1SDimitry Andric bits <5> Rss32; 1594fe6060f1SDimitry Andric let Inst{20-16} = Rss32{4-0}; 1595fe6060f1SDimitry Andric bits <5> Rdd32; 1596fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 1597fe6060f1SDimitry Andric} 1598fe6060f1SDimitry Andricclass Enc_733b27 : OpcodeHexagon { 1599fe6060f1SDimitry Andric bits <5> Ii; 1600fe6060f1SDimitry Andric let Inst{8-5} = Ii{4-1}; 1601fe6060f1SDimitry Andric bits <2> Pt4; 1602fe6060f1SDimitry Andric let Inst{10-9} = Pt4{1-0}; 1603fe6060f1SDimitry Andric bits <5> Rd32; 1604fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 1605fe6060f1SDimitry Andric bits <5> Rx32; 1606fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 1607fe6060f1SDimitry Andric} 1608fe6060f1SDimitry Andricclass Enc_736575 : OpcodeHexagon { 1609fe6060f1SDimitry Andric bits <11> Ii; 1610fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 1611fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 1612fe6060f1SDimitry Andric bits <4> Rs16; 1613fe6060f1SDimitry Andric let Inst{19-16} = Rs16{3-0}; 1614fe6060f1SDimitry Andric bits <4> n1; 1615fe6060f1SDimitry Andric let Inst{28-28} = n1{3-3}; 1616fe6060f1SDimitry Andric let Inst{25-23} = n1{2-0}; 1617fe6060f1SDimitry Andric} 1618fe6060f1SDimitry Andricclass Enc_74aef2 : OpcodeHexagon { 1619fe6060f1SDimitry Andric bits <4> Ii; 1620fe6060f1SDimitry Andric let Inst{8-5} = Ii{3-0}; 1621fe6060f1SDimitry Andric bits <1> Mu2; 1622fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 1623fe6060f1SDimitry Andric bits <5> Ryy32; 1624fe6060f1SDimitry Andric let Inst{4-0} = Ryy32{4-0}; 1625fe6060f1SDimitry Andric bits <5> Rx32; 1626fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 1627fe6060f1SDimitry Andric} 1628fe6060f1SDimitry Andricclass Enc_74d4e5 : OpcodeHexagon { 1629fe6060f1SDimitry Andric bits <1> Mu2; 1630fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 1631fe6060f1SDimitry Andric bits <5> Rd32; 1632fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 1633fe6060f1SDimitry Andric bits <5> Rx32; 1634fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 1635fe6060f1SDimitry Andric} 1636fe6060f1SDimitry Andricclass Enc_770858 : OpcodeHexagon { 1637fe6060f1SDimitry Andric bits <2> Ps4; 1638fe6060f1SDimitry Andric let Inst{6-5} = Ps4{1-0}; 1639fe6060f1SDimitry Andric bits <5> Vu32; 1640fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 1641fe6060f1SDimitry Andric bits <5> Vd32; 1642fe6060f1SDimitry Andric let Inst{4-0} = Vd32{4-0}; 1643fe6060f1SDimitry Andric} 1644fe6060f1SDimitry Andricclass Enc_784502 : OpcodeHexagon { 1645fe6060f1SDimitry Andric bits <3> Ii; 1646fe6060f1SDimitry Andric let Inst{10-8} = Ii{2-0}; 1647fe6060f1SDimitry Andric bits <2> Pv4; 1648fe6060f1SDimitry Andric let Inst{12-11} = Pv4{1-0}; 1649fe6060f1SDimitry Andric bits <3> Os8; 1650fe6060f1SDimitry Andric let Inst{2-0} = Os8{2-0}; 1651fe6060f1SDimitry Andric bits <5> Rx32; 1652fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 1653fe6060f1SDimitry Andric} 1654fe6060f1SDimitry Andricclass Enc_78cbf0 : OpcodeHexagon { 1655fe6060f1SDimitry Andric bits <18> Ii; 1656fe6060f1SDimitry Andric let Inst{26-25} = Ii{17-16}; 1657fe6060f1SDimitry Andric let Inst{20-16} = Ii{15-11}; 1658fe6060f1SDimitry Andric let Inst{13-13} = Ii{10-10}; 1659fe6060f1SDimitry Andric let Inst{7-0} = Ii{9-2}; 1660fe6060f1SDimitry Andric bits <3> Nt8; 1661fe6060f1SDimitry Andric let Inst{10-8} = Nt8{2-0}; 1662fe6060f1SDimitry Andric} 1663fe6060f1SDimitry Andricclass Enc_78e566 : OpcodeHexagon { 1664fe6060f1SDimitry Andric bits <2> Pt4; 1665fe6060f1SDimitry Andric let Inst{9-8} = Pt4{1-0}; 1666fe6060f1SDimitry Andric bits <5> Rdd32; 1667fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 1668fe6060f1SDimitry Andric} 1669fe6060f1SDimitry Andricclass Enc_79b8c8 : OpcodeHexagon { 1670fe6060f1SDimitry Andric bits <6> Ii; 1671fe6060f1SDimitry Andric let Inst{6-3} = Ii{5-2}; 1672fe6060f1SDimitry Andric bits <1> Mu2; 1673fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 1674fe6060f1SDimitry Andric bits <5> Rt32; 1675fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 1676fe6060f1SDimitry Andric bits <5> Rx32; 1677fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 1678fe6060f1SDimitry Andric} 1679fe6060f1SDimitry Andricclass Enc_7a0ea6 : OpcodeHexagon { 1680fe6060f1SDimitry Andric bits <4> Rd16; 1681fe6060f1SDimitry Andric let Inst{3-0} = Rd16{3-0}; 1682fe6060f1SDimitry Andric bits <1> n1; 1683fe6060f1SDimitry Andric let Inst{9-9} = n1{0-0}; 1684fe6060f1SDimitry Andric} 1685fe6060f1SDimitry Andricclass Enc_7b523d : OpcodeHexagon { 1686fe6060f1SDimitry Andric bits <5> Vu32; 1687fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 1688fe6060f1SDimitry Andric bits <5> Vv32; 1689fe6060f1SDimitry Andric let Inst{23-19} = Vv32{4-0}; 1690fe6060f1SDimitry Andric bits <3> Rt8; 1691fe6060f1SDimitry Andric let Inst{18-16} = Rt8{2-0}; 1692fe6060f1SDimitry Andric bits <5> Vxx32; 1693fe6060f1SDimitry Andric let Inst{4-0} = Vxx32{4-0}; 1694fe6060f1SDimitry Andric} 1695fe6060f1SDimitry Andricclass Enc_7b7ba8 : OpcodeHexagon { 1696fe6060f1SDimitry Andric bits <2> Qu4; 1697fe6060f1SDimitry Andric let Inst{9-8} = Qu4{1-0}; 1698fe6060f1SDimitry Andric bits <5> Rt32; 1699fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 1700fe6060f1SDimitry Andric bits <5> Vd32; 1701fe6060f1SDimitry Andric let Inst{4-0} = Vd32{4-0}; 1702fe6060f1SDimitry Andric} 1703349cc55cSDimitry Andricclass Enc_7d1542 : OpcodeHexagon { 1704349cc55cSDimitry Andric bits <7> Ss128; 1705349cc55cSDimitry Andric let Inst{22-16} = Ss128{6-0}; 1706349cc55cSDimitry Andric bits <5> Rd32; 1707349cc55cSDimitry Andric let Inst{4-0} = Rd32{4-0}; 1708349cc55cSDimitry Andric} 1709fe6060f1SDimitry Andricclass Enc_7e5a82 : OpcodeHexagon { 1710fe6060f1SDimitry Andric bits <5> Ii; 1711fe6060f1SDimitry Andric let Inst{12-8} = Ii{4-0}; 1712fe6060f1SDimitry Andric bits <5> Rss32; 1713fe6060f1SDimitry Andric let Inst{20-16} = Rss32{4-0}; 1714fe6060f1SDimitry Andric bits <5> Rdd32; 1715fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 1716fe6060f1SDimitry Andric} 1717fe6060f1SDimitry Andricclass Enc_7eaeb6 : OpcodeHexagon { 1718fe6060f1SDimitry Andric bits <6> Ii; 1719fe6060f1SDimitry Andric let Inst{6-3} = Ii{5-2}; 1720fe6060f1SDimitry Andric bits <2> Pv4; 1721fe6060f1SDimitry Andric let Inst{1-0} = Pv4{1-0}; 1722fe6060f1SDimitry Andric bits <5> Rt32; 1723fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 1724fe6060f1SDimitry Andric bits <5> Rx32; 1725fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 1726fe6060f1SDimitry Andric} 1727fe6060f1SDimitry Andricclass Enc_7eb485 : OpcodeHexagon { 1728fe6060f1SDimitry Andric bits <2> Ii; 1729fe6060f1SDimitry Andric let Inst{13-13} = Ii{1-1}; 1730fe6060f1SDimitry Andric let Inst{6-6} = Ii{0-0}; 1731fe6060f1SDimitry Andric bits <6> II; 1732fe6060f1SDimitry Andric let Inst{5-0} = II{5-0}; 1733fe6060f1SDimitry Andric bits <5> Ru32; 1734fe6060f1SDimitry Andric let Inst{20-16} = Ru32{4-0}; 1735fe6060f1SDimitry Andric bits <3> Nt8; 1736fe6060f1SDimitry Andric let Inst{10-8} = Nt8{2-0}; 1737fe6060f1SDimitry Andric} 1738fe6060f1SDimitry Andricclass Enc_7eee72 : OpcodeHexagon { 1739fe6060f1SDimitry Andric bits <1> Mu2; 1740fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 1741fe6060f1SDimitry Andric bits <5> Rdd32; 1742fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 1743fe6060f1SDimitry Andric bits <5> Rx32; 1744fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 1745fe6060f1SDimitry Andric} 1746fe6060f1SDimitry Andricclass Enc_7f1a05 : OpcodeHexagon { 1747fe6060f1SDimitry Andric bits <5> Ru32; 1748fe6060f1SDimitry Andric let Inst{4-0} = Ru32{4-0}; 1749fe6060f1SDimitry Andric bits <5> Rs32; 1750fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 1751fe6060f1SDimitry Andric bits <5> Ry32; 1752fe6060f1SDimitry Andric let Inst{12-8} = Ry32{4-0}; 1753fe6060f1SDimitry Andric} 1754fe6060f1SDimitry Andricclass Enc_7fa7f6 : OpcodeHexagon { 1755fe6060f1SDimitry Andric bits <6> II; 1756fe6060f1SDimitry Andric let Inst{11-8} = II{5-2}; 1757fe6060f1SDimitry Andric let Inst{6-5} = II{1-0}; 1758fe6060f1SDimitry Andric bits <5> Rdd32; 1759fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 1760fe6060f1SDimitry Andric bits <5> Re32; 1761fe6060f1SDimitry Andric let Inst{20-16} = Re32{4-0}; 1762fe6060f1SDimitry Andric} 1763fe6060f1SDimitry Andricclass Enc_800e04 : OpcodeHexagon { 1764fe6060f1SDimitry Andric bits <11> Ii; 1765fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 1766fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 1767fe6060f1SDimitry Andric bits <4> Rs16; 1768fe6060f1SDimitry Andric let Inst{19-16} = Rs16{3-0}; 1769fe6060f1SDimitry Andric bits <6> n1; 1770fe6060f1SDimitry Andric let Inst{28-28} = n1{5-5}; 1771fe6060f1SDimitry Andric let Inst{25-22} = n1{4-1}; 1772fe6060f1SDimitry Andric let Inst{13-13} = n1{0-0}; 1773fe6060f1SDimitry Andric} 1774fe6060f1SDimitry Andricclass Enc_802dc0 : OpcodeHexagon { 1775fe6060f1SDimitry Andric bits <1> Ii; 1776fe6060f1SDimitry Andric let Inst{8-8} = Ii{0-0}; 1777fe6060f1SDimitry Andric bits <2> Qv4; 1778fe6060f1SDimitry Andric let Inst{23-22} = Qv4{1-0}; 1779fe6060f1SDimitry Andric} 1780fe6060f1SDimitry Andricclass Enc_81ac1d : OpcodeHexagon { 1781fe6060f1SDimitry Andric bits <24> Ii; 1782fe6060f1SDimitry Andric let Inst{24-16} = Ii{23-15}; 1783fe6060f1SDimitry Andric let Inst{13-1} = Ii{14-2}; 1784fe6060f1SDimitry Andric} 1785fe6060f1SDimitry Andricclass Enc_8203bb : OpcodeHexagon { 1786fe6060f1SDimitry Andric bits <6> Ii; 1787fe6060f1SDimitry Andric let Inst{12-7} = Ii{5-0}; 1788fe6060f1SDimitry Andric bits <8> II; 1789fe6060f1SDimitry Andric let Inst{13-13} = II{7-7}; 1790fe6060f1SDimitry Andric let Inst{6-0} = II{6-0}; 1791fe6060f1SDimitry Andric bits <5> Rs32; 1792fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 1793fe6060f1SDimitry Andric} 1794fe6060f1SDimitry Andricclass Enc_830e5d : OpcodeHexagon { 1795fe6060f1SDimitry Andric bits <8> Ii; 1796fe6060f1SDimitry Andric let Inst{12-5} = Ii{7-0}; 1797fe6060f1SDimitry Andric bits <8> II; 1798fe6060f1SDimitry Andric let Inst{22-16} = II{7-1}; 1799fe6060f1SDimitry Andric let Inst{13-13} = II{0-0}; 1800fe6060f1SDimitry Andric bits <2> Pu4; 1801fe6060f1SDimitry Andric let Inst{24-23} = Pu4{1-0}; 1802fe6060f1SDimitry Andric bits <5> Rd32; 1803fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 1804fe6060f1SDimitry Andric} 18055ffd83dbSDimitry Andricclass Enc_831a7d : OpcodeHexagon { 18065ffd83dbSDimitry Andric bits <5> Rss32; 18075ffd83dbSDimitry Andric let Inst{20-16} = Rss32{4-0}; 18085ffd83dbSDimitry Andric bits <5> Rtt32; 18095ffd83dbSDimitry Andric let Inst{12-8} = Rtt32{4-0}; 18105ffd83dbSDimitry Andric bits <5> Rxx32; 18115ffd83dbSDimitry Andric let Inst{4-0} = Rxx32{4-0}; 18125ffd83dbSDimitry Andric bits <2> Pe4; 18135ffd83dbSDimitry Andric let Inst{6-5} = Pe4{1-0}; 18145ffd83dbSDimitry Andric} 1815fe6060f1SDimitry Andricclass Enc_83ee64 : OpcodeHexagon { 1816fe6060f1SDimitry Andric bits <5> Ii; 1817fe6060f1SDimitry Andric let Inst{12-8} = Ii{4-0}; 1818fe6060f1SDimitry Andric bits <5> Rs32; 1819fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 1820fe6060f1SDimitry Andric bits <2> Pd4; 1821fe6060f1SDimitry Andric let Inst{1-0} = Pd4{1-0}; 1822fe6060f1SDimitry Andric} 1823fe6060f1SDimitry Andricclass Enc_84b2cd : OpcodeHexagon { 1824fe6060f1SDimitry Andric bits <8> Ii; 1825fe6060f1SDimitry Andric let Inst{12-7} = Ii{7-2}; 1826fe6060f1SDimitry Andric bits <5> II; 1827fe6060f1SDimitry Andric let Inst{4-0} = II{4-0}; 1828fe6060f1SDimitry Andric bits <5> Rs32; 1829fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 1830fe6060f1SDimitry Andric} 1831fe6060f1SDimitry Andricclass Enc_84bff1 : OpcodeHexagon { 1832fe6060f1SDimitry Andric bits <2> Ii; 1833fe6060f1SDimitry Andric let Inst{13-13} = Ii{1-1}; 1834fe6060f1SDimitry Andric let Inst{7-7} = Ii{0-0}; 1835fe6060f1SDimitry Andric bits <5> Rs32; 1836fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 1837fe6060f1SDimitry Andric bits <5> Rt32; 1838fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 1839fe6060f1SDimitry Andric bits <5> Rdd32; 1840fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 1841fe6060f1SDimitry Andric} 1842fe6060f1SDimitry Andricclass Enc_84d359 : OpcodeHexagon { 1843fe6060f1SDimitry Andric bits <4> Ii; 1844fe6060f1SDimitry Andric let Inst{3-0} = Ii{3-0}; 1845fe6060f1SDimitry Andric bits <4> Rs16; 1846fe6060f1SDimitry Andric let Inst{7-4} = Rs16{3-0}; 1847fe6060f1SDimitry Andric} 1848fe6060f1SDimitry Andricclass Enc_85bf58 : OpcodeHexagon { 1849fe6060f1SDimitry Andric bits <7> Ii; 1850fe6060f1SDimitry Andric let Inst{6-3} = Ii{6-3}; 1851fe6060f1SDimitry Andric bits <5> Rtt32; 1852fe6060f1SDimitry Andric let Inst{12-8} = Rtt32{4-0}; 1853fe6060f1SDimitry Andric bits <5> Rx32; 1854fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 1855fe6060f1SDimitry Andric} 1856fe6060f1SDimitry Andricclass Enc_864a5a : OpcodeHexagon { 1857fe6060f1SDimitry Andric bits <9> Ii; 1858fe6060f1SDimitry Andric let Inst{12-8} = Ii{8-4}; 1859fe6060f1SDimitry Andric let Inst{4-3} = Ii{3-2}; 1860fe6060f1SDimitry Andric bits <5> Rs32; 1861fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 1862fe6060f1SDimitry Andric} 1863fe6060f1SDimitry Andricclass Enc_865390 : OpcodeHexagon { 1864fe6060f1SDimitry Andric bits <3> Ii; 1865fe6060f1SDimitry Andric let Inst{10-8} = Ii{2-0}; 1866fe6060f1SDimitry Andric bits <2> Pv4; 1867fe6060f1SDimitry Andric let Inst{12-11} = Pv4{1-0}; 1868fe6060f1SDimitry Andric bits <5> Vs32; 1869fe6060f1SDimitry Andric let Inst{4-0} = Vs32{4-0}; 1870fe6060f1SDimitry Andric bits <5> Rx32; 1871fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 1872fe6060f1SDimitry Andric} 1873fe6060f1SDimitry Andricclass Enc_86a14b : OpcodeHexagon { 1874fe6060f1SDimitry Andric bits <8> Ii; 1875fe6060f1SDimitry Andric let Inst{7-3} = Ii{7-3}; 1876fe6060f1SDimitry Andric bits <3> Rdd8; 1877fe6060f1SDimitry Andric let Inst{2-0} = Rdd8{2-0}; 1878fe6060f1SDimitry Andric} 1879fe6060f1SDimitry Andricclass Enc_87c142 : OpcodeHexagon { 1880fe6060f1SDimitry Andric bits <7> Ii; 1881fe6060f1SDimitry Andric let Inst{8-4} = Ii{6-2}; 1882fe6060f1SDimitry Andric bits <4> Rt16; 1883fe6060f1SDimitry Andric let Inst{3-0} = Rt16{3-0}; 1884fe6060f1SDimitry Andric} 1885fe6060f1SDimitry Andricclass Enc_88c16c : OpcodeHexagon { 1886fe6060f1SDimitry Andric bits <5> Rss32; 1887fe6060f1SDimitry Andric let Inst{20-16} = Rss32{4-0}; 1888fe6060f1SDimitry Andric bits <5> Rtt32; 1889fe6060f1SDimitry Andric let Inst{12-8} = Rtt32{4-0}; 1890fe6060f1SDimitry Andric bits <5> Rxx32; 1891fe6060f1SDimitry Andric let Inst{4-0} = Rxx32{4-0}; 1892fe6060f1SDimitry Andric} 1893fe6060f1SDimitry Andricclass Enc_88d4d9 : OpcodeHexagon { 1894fe6060f1SDimitry Andric bits <2> Pu4; 1895fe6060f1SDimitry Andric let Inst{9-8} = Pu4{1-0}; 1896fe6060f1SDimitry Andric bits <5> Rs32; 1897fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 1898fe6060f1SDimitry Andric} 1899fe6060f1SDimitry Andricclass Enc_890909 : OpcodeHexagon { 1900fe6060f1SDimitry Andric bits <5> Rs32; 1901fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 1902fe6060f1SDimitry Andric bits <5> Rd32; 1903fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 1904fe6060f1SDimitry Andric bits <2> Pe4; 1905fe6060f1SDimitry Andric let Inst{6-5} = Pe4{1-0}; 1906fe6060f1SDimitry Andric} 1907fe6060f1SDimitry Andricclass Enc_895bd9 : OpcodeHexagon { 1908fe6060f1SDimitry Andric bits <2> Qu4; 1909fe6060f1SDimitry Andric let Inst{9-8} = Qu4{1-0}; 1910fe6060f1SDimitry Andric bits <5> Rt32; 1911fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 1912fe6060f1SDimitry Andric bits <5> Vx32; 1913fe6060f1SDimitry Andric let Inst{4-0} = Vx32{4-0}; 1914fe6060f1SDimitry Andric} 1915fe6060f1SDimitry Andricclass Enc_8b8927 : OpcodeHexagon { 1916fe6060f1SDimitry Andric bits <5> Rt32; 1917fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 1918fe6060f1SDimitry Andric bits <1> Mu2; 1919fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 1920fe6060f1SDimitry Andric bits <5> Vv32; 1921fe6060f1SDimitry Andric let Inst{4-0} = Vv32{4-0}; 1922fe6060f1SDimitry Andric} 1923fe6060f1SDimitry Andricclass Enc_8b8d61 : OpcodeHexagon { 1924fe6060f1SDimitry Andric bits <6> Ii; 1925fe6060f1SDimitry Andric let Inst{22-21} = Ii{5-4}; 1926fe6060f1SDimitry Andric let Inst{13-13} = Ii{3-3}; 1927fe6060f1SDimitry Andric let Inst{7-5} = Ii{2-0}; 1928fe6060f1SDimitry Andric bits <5> Rs32; 1929fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 1930fe6060f1SDimitry Andric bits <5> Ru32; 1931fe6060f1SDimitry Andric let Inst{4-0} = Ru32{4-0}; 1932fe6060f1SDimitry Andric bits <5> Rd32; 1933fe6060f1SDimitry Andric let Inst{12-8} = Rd32{4-0}; 1934fe6060f1SDimitry Andric} 1935fe6060f1SDimitry Andricclass Enc_8bcba4 : OpcodeHexagon { 1936fe6060f1SDimitry Andric bits <6> II; 1937fe6060f1SDimitry Andric let Inst{5-0} = II{5-0}; 1938fe6060f1SDimitry Andric bits <5> Rt32; 1939fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 1940fe6060f1SDimitry Andric bits <5> Re32; 1941fe6060f1SDimitry Andric let Inst{20-16} = Re32{4-0}; 1942fe6060f1SDimitry Andric} 1943fe6060f1SDimitry Andricclass Enc_8c2412 : OpcodeHexagon { 1944fe6060f1SDimitry Andric bits <2> Ps4; 1945fe6060f1SDimitry Andric let Inst{6-5} = Ps4{1-0}; 1946fe6060f1SDimitry Andric bits <5> Vu32; 1947fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 1948fe6060f1SDimitry Andric bits <5> Vv32; 1949fe6060f1SDimitry Andric let Inst{20-16} = Vv32{4-0}; 1950fe6060f1SDimitry Andric bits <5> Vdd32; 1951fe6060f1SDimitry Andric let Inst{4-0} = Vdd32{4-0}; 1952fe6060f1SDimitry Andric} 1953fe6060f1SDimitry Andricclass Enc_8c6530 : OpcodeHexagon { 1954fe6060f1SDimitry Andric bits <5> Rtt32; 1955fe6060f1SDimitry Andric let Inst{12-8} = Rtt32{4-0}; 1956fe6060f1SDimitry Andric bits <5> Rss32; 1957fe6060f1SDimitry Andric let Inst{20-16} = Rss32{4-0}; 1958fe6060f1SDimitry Andric bits <2> Pu4; 1959fe6060f1SDimitry Andric let Inst{6-5} = Pu4{1-0}; 1960fe6060f1SDimitry Andric bits <5> Rdd32; 1961fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 1962fe6060f1SDimitry Andric} 1963fe6060f1SDimitry Andricclass Enc_8d8a30 : OpcodeHexagon { 1964fe6060f1SDimitry Andric bits <4> Ii; 1965fe6060f1SDimitry Andric let Inst{13-13} = Ii{3-3}; 1966fe6060f1SDimitry Andric let Inst{10-8} = Ii{2-0}; 1967fe6060f1SDimitry Andric bits <2> Pv4; 1968fe6060f1SDimitry Andric let Inst{12-11} = Pv4{1-0}; 1969fe6060f1SDimitry Andric bits <5> Rt32; 1970fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 1971fe6060f1SDimitry Andric bits <5> Vd32; 1972fe6060f1SDimitry Andric let Inst{4-0} = Vd32{4-0}; 1973fe6060f1SDimitry Andric} 1974fe6060f1SDimitry Andricclass Enc_8dbdfe : OpcodeHexagon { 1975fe6060f1SDimitry Andric bits <8> Ii; 1976fe6060f1SDimitry Andric let Inst{13-13} = Ii{7-7}; 1977fe6060f1SDimitry Andric let Inst{7-3} = Ii{6-2}; 1978fe6060f1SDimitry Andric bits <2> Pv4; 1979fe6060f1SDimitry Andric let Inst{1-0} = Pv4{1-0}; 1980fe6060f1SDimitry Andric bits <5> Rs32; 1981fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 1982fe6060f1SDimitry Andric bits <3> Nt8; 1983fe6060f1SDimitry Andric let Inst{10-8} = Nt8{2-0}; 1984fe6060f1SDimitry Andric} 1985fe6060f1SDimitry Andricclass Enc_8dbe85 : OpcodeHexagon { 1986fe6060f1SDimitry Andric bits <1> Mu2; 1987fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 1988fe6060f1SDimitry Andric bits <3> Nt8; 1989fe6060f1SDimitry Andric let Inst{10-8} = Nt8{2-0}; 1990fe6060f1SDimitry Andric bits <5> Rx32; 1991fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 1992fe6060f1SDimitry Andric} 1993fe6060f1SDimitry Andricclass Enc_8dec2e : OpcodeHexagon { 1994fe6060f1SDimitry Andric bits <5> Ii; 1995fe6060f1SDimitry Andric let Inst{12-8} = Ii{4-0}; 1996fe6060f1SDimitry Andric bits <5> Rss32; 1997fe6060f1SDimitry Andric let Inst{20-16} = Rss32{4-0}; 1998fe6060f1SDimitry Andric bits <5> Rd32; 1999fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 2000fe6060f1SDimitry Andric} 2001fe6060f1SDimitry Andricclass Enc_8df4be : OpcodeHexagon { 2002fe6060f1SDimitry Andric bits <17> Ii; 2003fe6060f1SDimitry Andric let Inst{26-25} = Ii{16-15}; 2004fe6060f1SDimitry Andric let Inst{20-16} = Ii{14-10}; 2005fe6060f1SDimitry Andric let Inst{13-5} = Ii{9-1}; 2006fe6060f1SDimitry Andric bits <5> Rd32; 2007fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 2008fe6060f1SDimitry Andric} 2009fe6060f1SDimitry Andricclass Enc_8e583a : OpcodeHexagon { 2010fe6060f1SDimitry Andric bits <11> Ii; 2011fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 2012fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 2013fe6060f1SDimitry Andric bits <4> Rs16; 2014fe6060f1SDimitry Andric let Inst{19-16} = Rs16{3-0}; 2015fe6060f1SDimitry Andric bits <5> n1; 2016fe6060f1SDimitry Andric let Inst{28-28} = n1{4-4}; 2017fe6060f1SDimitry Andric let Inst{25-23} = n1{3-1}; 2018fe6060f1SDimitry Andric let Inst{13-13} = n1{0-0}; 2019fe6060f1SDimitry Andric} 2020349cc55cSDimitry Andricclass Enc_8f7633 : OpcodeHexagon { 2021349cc55cSDimitry Andric bits <5> Rs32; 2022349cc55cSDimitry Andric let Inst{20-16} = Rs32{4-0}; 2023349cc55cSDimitry Andric bits <7> Sd128; 2024349cc55cSDimitry Andric let Inst{6-0} = Sd128{6-0}; 2025349cc55cSDimitry Andric} 2026fe6060f1SDimitry Andricclass Enc_90cd8b : OpcodeHexagon { 2027fe6060f1SDimitry Andric bits <5> Rss32; 2028fe6060f1SDimitry Andric let Inst{20-16} = Rss32{4-0}; 2029fe6060f1SDimitry Andric bits <5> Rd32; 2030fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 2031fe6060f1SDimitry Andric} 2032fe6060f1SDimitry Andricclass Enc_91b9fe : OpcodeHexagon { 2033fe6060f1SDimitry Andric bits <5> Ii; 2034fe6060f1SDimitry Andric let Inst{6-3} = Ii{4-1}; 2035fe6060f1SDimitry Andric bits <1> Mu2; 2036fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 2037fe6060f1SDimitry Andric bits <3> Nt8; 2038fe6060f1SDimitry Andric let Inst{10-8} = Nt8{2-0}; 2039fe6060f1SDimitry Andric bits <5> Rx32; 2040fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 2041fe6060f1SDimitry Andric} 2042fe6060f1SDimitry Andricclass Enc_927852 : OpcodeHexagon { 2043fe6060f1SDimitry Andric bits <5> Rss32; 2044fe6060f1SDimitry Andric let Inst{20-16} = Rss32{4-0}; 2045fe6060f1SDimitry Andric bits <5> Rt32; 2046fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 2047fe6060f1SDimitry Andric bits <5> Rdd32; 2048fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 2049fe6060f1SDimitry Andric} 2050fe6060f1SDimitry Andricclass Enc_928ca1 : OpcodeHexagon { 2051fe6060f1SDimitry Andric bits <1> Mu2; 2052fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 2053fe6060f1SDimitry Andric bits <5> Rtt32; 2054fe6060f1SDimitry Andric let Inst{12-8} = Rtt32{4-0}; 2055fe6060f1SDimitry Andric bits <5> Rx32; 2056fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 2057fe6060f1SDimitry Andric} 2058fe6060f1SDimitry Andricclass Enc_935d9b : OpcodeHexagon { 2059fe6060f1SDimitry Andric bits <5> Ii; 2060fe6060f1SDimitry Andric let Inst{6-3} = Ii{4-1}; 2061fe6060f1SDimitry Andric bits <1> Mu2; 2062fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 2063fe6060f1SDimitry Andric bits <5> Rt32; 2064fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 2065fe6060f1SDimitry Andric bits <5> Rx32; 2066fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 2067fe6060f1SDimitry Andric} 2068fe6060f1SDimitry Andricclass Enc_93af4c : OpcodeHexagon { 2069fe6060f1SDimitry Andric bits <7> Ii; 2070fe6060f1SDimitry Andric let Inst{10-4} = Ii{6-0}; 2071fe6060f1SDimitry Andric bits <4> Rx16; 2072fe6060f1SDimitry Andric let Inst{3-0} = Rx16{3-0}; 2073fe6060f1SDimitry Andric} 2074fe6060f1SDimitry Andricclass Enc_95441f : OpcodeHexagon { 2075fe6060f1SDimitry Andric bits <5> Vu32; 2076fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 2077fe6060f1SDimitry Andric bits <5> Vv32; 2078fe6060f1SDimitry Andric let Inst{20-16} = Vv32{4-0}; 2079fe6060f1SDimitry Andric bits <2> Qd4; 2080fe6060f1SDimitry Andric let Inst{1-0} = Qd4{1-0}; 2081fe6060f1SDimitry Andric} 2082fe6060f1SDimitry Andricclass Enc_96ce4f : OpcodeHexagon { 2083fe6060f1SDimitry Andric bits <4> Ii; 2084fe6060f1SDimitry Andric let Inst{6-3} = Ii{3-0}; 2085fe6060f1SDimitry Andric bits <1> Mu2; 2086fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 2087fe6060f1SDimitry Andric bits <3> Nt8; 2088fe6060f1SDimitry Andric let Inst{10-8} = Nt8{2-0}; 2089fe6060f1SDimitry Andric bits <5> Rx32; 2090fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 2091fe6060f1SDimitry Andric} 2092fe6060f1SDimitry Andricclass Enc_97d666 : OpcodeHexagon { 2093fe6060f1SDimitry Andric bits <4> Rs16; 2094fe6060f1SDimitry Andric let Inst{7-4} = Rs16{3-0}; 2095fe6060f1SDimitry Andric bits <4> Rd16; 2096fe6060f1SDimitry Andric let Inst{3-0} = Rd16{3-0}; 2097fe6060f1SDimitry Andric} 2098fe6060f1SDimitry Andricclass Enc_989021 : OpcodeHexagon { 2099fe6060f1SDimitry Andric bits <5> Rt32; 2100fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 2101fe6060f1SDimitry Andric bits <5> Vy32; 2102fe6060f1SDimitry Andric let Inst{12-8} = Vy32{4-0}; 2103fe6060f1SDimitry Andric bits <5> Vx32; 2104fe6060f1SDimitry Andric let Inst{4-0} = Vx32{4-0}; 2105fe6060f1SDimitry Andric} 2106fe6060f1SDimitry Andricclass Enc_98c0b8 : OpcodeHexagon { 2107fe6060f1SDimitry Andric bits <2> Ii; 2108fe6060f1SDimitry Andric let Inst{13-13} = Ii{1-1}; 2109fe6060f1SDimitry Andric let Inst{7-7} = Ii{0-0}; 2110fe6060f1SDimitry Andric bits <2> Pv4; 2111fe6060f1SDimitry Andric let Inst{6-5} = Pv4{1-0}; 2112fe6060f1SDimitry Andric bits <5> Rs32; 2113fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2114fe6060f1SDimitry Andric bits <5> Rt32; 2115fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 2116fe6060f1SDimitry Andric bits <5> Rdd32; 2117fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 2118fe6060f1SDimitry Andric} 2119fe6060f1SDimitry Andricclass Enc_9a33d5 : OpcodeHexagon { 2120fe6060f1SDimitry Andric bits <7> Ii; 2121fe6060f1SDimitry Andric let Inst{6-3} = Ii{6-3}; 2122fe6060f1SDimitry Andric bits <2> Pv4; 2123fe6060f1SDimitry Andric let Inst{1-0} = Pv4{1-0}; 2124fe6060f1SDimitry Andric bits <5> Rtt32; 2125fe6060f1SDimitry Andric let Inst{12-8} = Rtt32{4-0}; 2126fe6060f1SDimitry Andric bits <5> Rx32; 2127fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 2128fe6060f1SDimitry Andric} 2129fe6060f1SDimitry Andricclass Enc_9ac432 : OpcodeHexagon { 2130fe6060f1SDimitry Andric bits <2> Ps4; 2131fe6060f1SDimitry Andric let Inst{17-16} = Ps4{1-0}; 2132fe6060f1SDimitry Andric bits <2> Pt4; 2133fe6060f1SDimitry Andric let Inst{9-8} = Pt4{1-0}; 2134fe6060f1SDimitry Andric bits <2> Pu4; 2135fe6060f1SDimitry Andric let Inst{7-6} = Pu4{1-0}; 2136fe6060f1SDimitry Andric bits <2> Pd4; 2137fe6060f1SDimitry Andric let Inst{1-0} = Pd4{1-0}; 2138fe6060f1SDimitry Andric} 2139fe6060f1SDimitry Andricclass Enc_9b0bc1 : OpcodeHexagon { 2140fe6060f1SDimitry Andric bits <2> Pu4; 2141fe6060f1SDimitry Andric let Inst{6-5} = Pu4{1-0}; 2142fe6060f1SDimitry Andric bits <5> Rt32; 2143fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 2144fe6060f1SDimitry Andric bits <5> Rs32; 2145fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2146fe6060f1SDimitry Andric bits <5> Rd32; 2147fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 2148fe6060f1SDimitry Andric} 2149fe6060f1SDimitry Andricclass Enc_9be1de : OpcodeHexagon { 2150fe6060f1SDimitry Andric bits <2> Qs4; 2151fe6060f1SDimitry Andric let Inst{6-5} = Qs4{1-0}; 2152fe6060f1SDimitry Andric bits <5> Rt32; 2153fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 2154fe6060f1SDimitry Andric bits <1> Mu2; 2155fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 2156fe6060f1SDimitry Andric bits <5> Vv32; 2157fe6060f1SDimitry Andric let Inst{12-8} = Vv32{4-0}; 2158fe6060f1SDimitry Andric bits <5> Vw32; 2159fe6060f1SDimitry Andric let Inst{4-0} = Vw32{4-0}; 2160fe6060f1SDimitry Andric} 2161fe6060f1SDimitry Andricclass Enc_9cdba7 : OpcodeHexagon { 2162fe6060f1SDimitry Andric bits <8> Ii; 2163fe6060f1SDimitry Andric let Inst{12-5} = Ii{7-0}; 2164fe6060f1SDimitry Andric bits <5> Rs32; 2165fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2166fe6060f1SDimitry Andric bits <5> Rdd32; 2167fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 2168fe6060f1SDimitry Andric} 2169fe6060f1SDimitry Andricclass Enc_9d1247 : OpcodeHexagon { 2170fe6060f1SDimitry Andric bits <7> Ii; 2171fe6060f1SDimitry Andric let Inst{8-5} = Ii{6-3}; 2172fe6060f1SDimitry Andric bits <2> Pt4; 2173fe6060f1SDimitry Andric let Inst{10-9} = Pt4{1-0}; 2174fe6060f1SDimitry Andric bits <5> Rdd32; 2175fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 2176fe6060f1SDimitry Andric bits <5> Rx32; 2177fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 2178fe6060f1SDimitry Andric} 2179fe6060f1SDimitry Andricclass Enc_9e2e1c : OpcodeHexagon { 2180fe6060f1SDimitry Andric bits <5> Ii; 2181fe6060f1SDimitry Andric let Inst{8-5} = Ii{4-1}; 2182fe6060f1SDimitry Andric bits <1> Mu2; 2183fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 2184fe6060f1SDimitry Andric bits <5> Ryy32; 2185fe6060f1SDimitry Andric let Inst{4-0} = Ryy32{4-0}; 2186fe6060f1SDimitry Andric bits <5> Rx32; 2187fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 2188fe6060f1SDimitry Andric} 2189fe6060f1SDimitry Andricclass Enc_9e4c3f : OpcodeHexagon { 2190fe6060f1SDimitry Andric bits <6> II; 2191fe6060f1SDimitry Andric let Inst{13-8} = II{5-0}; 2192fe6060f1SDimitry Andric bits <11> Ii; 2193fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 2194fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 2195fe6060f1SDimitry Andric bits <4> Rd16; 2196fe6060f1SDimitry Andric let Inst{19-16} = Rd16{3-0}; 2197fe6060f1SDimitry Andric} 2198fe6060f1SDimitry Andricclass Enc_9ea4cf : OpcodeHexagon { 2199fe6060f1SDimitry Andric bits <2> Ii; 2200fe6060f1SDimitry Andric let Inst{13-13} = Ii{1-1}; 2201fe6060f1SDimitry Andric let Inst{6-6} = Ii{0-0}; 2202fe6060f1SDimitry Andric bits <6> II; 2203fe6060f1SDimitry Andric let Inst{5-0} = II{5-0}; 2204fe6060f1SDimitry Andric bits <5> Ru32; 2205fe6060f1SDimitry Andric let Inst{20-16} = Ru32{4-0}; 2206fe6060f1SDimitry Andric bits <5> Rt32; 2207fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 2208fe6060f1SDimitry Andric} 2209fe6060f1SDimitry Andricclass Enc_9fae8a : OpcodeHexagon { 2210fe6060f1SDimitry Andric bits <6> Ii; 2211fe6060f1SDimitry Andric let Inst{13-8} = Ii{5-0}; 2212fe6060f1SDimitry Andric bits <5> Rs32; 2213fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2214fe6060f1SDimitry Andric bits <5> Rd32; 2215fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 2216fe6060f1SDimitry Andric} 2217fe6060f1SDimitry Andricclass Enc_a05677 : OpcodeHexagon { 2218fe6060f1SDimitry Andric bits <5> Ii; 2219fe6060f1SDimitry Andric let Inst{12-8} = Ii{4-0}; 2220fe6060f1SDimitry Andric bits <5> Rs32; 2221fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2222fe6060f1SDimitry Andric bits <5> Rd32; 2223fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 2224fe6060f1SDimitry Andric} 2225fe6060f1SDimitry Andricclass Enc_a1640c : OpcodeHexagon { 2226fe6060f1SDimitry Andric bits <6> Ii; 2227fe6060f1SDimitry Andric let Inst{13-8} = Ii{5-0}; 2228fe6060f1SDimitry Andric bits <5> Rss32; 2229fe6060f1SDimitry Andric let Inst{20-16} = Rss32{4-0}; 2230fe6060f1SDimitry Andric bits <5> Rd32; 2231fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 2232fe6060f1SDimitry Andric} 2233fe6060f1SDimitry Andricclass Enc_a198f6 : OpcodeHexagon { 2234fe6060f1SDimitry Andric bits <7> Ii; 2235fe6060f1SDimitry Andric let Inst{10-5} = Ii{6-1}; 2236fe6060f1SDimitry Andric bits <2> Pt4; 2237fe6060f1SDimitry Andric let Inst{12-11} = Pt4{1-0}; 2238fe6060f1SDimitry Andric bits <5> Rs32; 2239fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2240fe6060f1SDimitry Andric bits <5> Rd32; 2241fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 2242fe6060f1SDimitry Andric} 2243fe6060f1SDimitry Andricclass Enc_a1e29d : OpcodeHexagon { 2244fe6060f1SDimitry Andric bits <5> Ii; 2245fe6060f1SDimitry Andric let Inst{12-8} = Ii{4-0}; 2246fe6060f1SDimitry Andric bits <5> II; 2247fe6060f1SDimitry Andric let Inst{22-21} = II{4-3}; 2248fe6060f1SDimitry Andric let Inst{7-5} = II{2-0}; 2249fe6060f1SDimitry Andric bits <5> Rs32; 2250fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2251fe6060f1SDimitry Andric bits <5> Rx32; 2252fe6060f1SDimitry Andric let Inst{4-0} = Rx32{4-0}; 2253fe6060f1SDimitry Andric} 2254fe6060f1SDimitry Andricclass Enc_a21d47 : OpcodeHexagon { 2255fe6060f1SDimitry Andric bits <6> Ii; 2256fe6060f1SDimitry Andric let Inst{10-5} = Ii{5-0}; 2257fe6060f1SDimitry Andric bits <2> Pt4; 2258fe6060f1SDimitry Andric let Inst{12-11} = Pt4{1-0}; 2259fe6060f1SDimitry Andric bits <5> Rs32; 2260fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2261fe6060f1SDimitry Andric bits <5> Rd32; 2262fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 2263fe6060f1SDimitry Andric} 2264fe6060f1SDimitry Andricclass Enc_a255dc : OpcodeHexagon { 2265fe6060f1SDimitry Andric bits <3> Ii; 2266fe6060f1SDimitry Andric let Inst{10-8} = Ii{2-0}; 2267fe6060f1SDimitry Andric bits <5> Vd32; 2268fe6060f1SDimitry Andric let Inst{4-0} = Vd32{4-0}; 2269fe6060f1SDimitry Andric bits <5> Rx32; 2270fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 2271fe6060f1SDimitry Andric} 2272fe6060f1SDimitry Andricclass Enc_a27588 : OpcodeHexagon { 2273fe6060f1SDimitry Andric bits <11> Ii; 2274fe6060f1SDimitry Andric let Inst{26-25} = Ii{10-9}; 2275fe6060f1SDimitry Andric let Inst{13-5} = Ii{8-0}; 2276fe6060f1SDimitry Andric bits <5> Rs32; 2277fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2278fe6060f1SDimitry Andric bits <5> Ryy32; 2279fe6060f1SDimitry Andric let Inst{4-0} = Ryy32{4-0}; 2280fe6060f1SDimitry Andric} 2281fe6060f1SDimitry Andricclass Enc_a30110 : OpcodeHexagon { 2282fe6060f1SDimitry Andric bits <5> Vu32; 2283fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 2284fe6060f1SDimitry Andric bits <5> Vv32; 2285fe6060f1SDimitry Andric let Inst{23-19} = Vv32{4-0}; 2286fe6060f1SDimitry Andric bits <3> Rt8; 2287fe6060f1SDimitry Andric let Inst{18-16} = Rt8{2-0}; 2288fe6060f1SDimitry Andric bits <5> Vd32; 2289fe6060f1SDimitry Andric let Inst{4-0} = Vd32{4-0}; 2290fe6060f1SDimitry Andric} 22910eae32dcSDimitry Andricclass Enc_a33d04 : OpcodeHexagon { 22920eae32dcSDimitry Andric bits <5> Vuu32; 22930eae32dcSDimitry Andric let Inst{12-8} = Vuu32{4-0}; 22940eae32dcSDimitry Andric bits <5> Vd32; 22950eae32dcSDimitry Andric let Inst{4-0} = Vd32{4-0}; 22960eae32dcSDimitry Andric} 2297fe6060f1SDimitry Andricclass Enc_a42857 : OpcodeHexagon { 2298fe6060f1SDimitry Andric bits <11> Ii; 2299fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 2300fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 2301fe6060f1SDimitry Andric bits <4> Rs16; 2302fe6060f1SDimitry Andric let Inst{19-16} = Rs16{3-0}; 2303fe6060f1SDimitry Andric bits <5> n1; 2304fe6060f1SDimitry Andric let Inst{28-28} = n1{4-4}; 2305fe6060f1SDimitry Andric let Inst{24-22} = n1{3-1}; 2306fe6060f1SDimitry Andric let Inst{8-8} = n1{0-0}; 2307fe6060f1SDimitry Andric} 2308fe6060f1SDimitry Andricclass Enc_a4ef14 : OpcodeHexagon { 2309fe6060f1SDimitry Andric bits <5> Rd32; 2310fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 2311fe6060f1SDimitry Andric} 2312fe6060f1SDimitry Andricclass Enc_a51a9a : OpcodeHexagon { 2313fe6060f1SDimitry Andric bits <8> Ii; 2314fe6060f1SDimitry Andric let Inst{12-8} = Ii{7-3}; 2315fe6060f1SDimitry Andric let Inst{4-2} = Ii{2-0}; 2316fe6060f1SDimitry Andric} 2317fe6060f1SDimitry Andricclass Enc_a56825 : OpcodeHexagon { 2318fe6060f1SDimitry Andric bits <5> Rss32; 2319fe6060f1SDimitry Andric let Inst{20-16} = Rss32{4-0}; 2320fe6060f1SDimitry Andric bits <5> Rtt32; 2321fe6060f1SDimitry Andric let Inst{12-8} = Rtt32{4-0}; 2322fe6060f1SDimitry Andric bits <5> Rdd32; 2323fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 2324fe6060f1SDimitry Andric} 2325fe6060f1SDimitry Andricclass Enc_a568d4 : OpcodeHexagon { 2326fe6060f1SDimitry Andric bits <5> Rt32; 2327fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 2328fe6060f1SDimitry Andric bits <5> Rs32; 2329fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2330fe6060f1SDimitry Andric bits <5> Rx32; 2331fe6060f1SDimitry Andric let Inst{4-0} = Rx32{4-0}; 2332fe6060f1SDimitry Andric} 2333fe6060f1SDimitry Andricclass Enc_a5ed8a : OpcodeHexagon { 2334fe6060f1SDimitry Andric bits <5> Rt32; 2335fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 2336fe6060f1SDimitry Andric bits <5> Vd32; 2337fe6060f1SDimitry Andric let Inst{4-0} = Vd32{4-0}; 2338fe6060f1SDimitry Andric} 2339fe6060f1SDimitry Andricclass Enc_a641d0 : OpcodeHexagon { 2340fe6060f1SDimitry Andric bits <5> Rt32; 2341fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 2342fe6060f1SDimitry Andric bits <1> Mu2; 2343fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 2344fe6060f1SDimitry Andric bits <5> Vvv32; 2345fe6060f1SDimitry Andric let Inst{12-8} = Vvv32{4-0}; 2346fe6060f1SDimitry Andric bits <5> Vw32; 2347fe6060f1SDimitry Andric let Inst{4-0} = Vw32{4-0}; 2348fe6060f1SDimitry Andric} 2349fe6060f1SDimitry Andricclass Enc_a6853f : OpcodeHexagon { 2350fe6060f1SDimitry Andric bits <11> Ii; 2351fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 2352fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 2353fe6060f1SDimitry Andric bits <3> Ns8; 2354fe6060f1SDimitry Andric let Inst{18-16} = Ns8{2-0}; 2355fe6060f1SDimitry Andric bits <6> n1; 2356fe6060f1SDimitry Andric let Inst{29-29} = n1{5-5}; 2357fe6060f1SDimitry Andric let Inst{26-25} = n1{4-3}; 2358fe6060f1SDimitry Andric let Inst{23-22} = n1{2-1}; 2359fe6060f1SDimitry Andric let Inst{13-13} = n1{0-0}; 2360fe6060f1SDimitry Andric} 2361fe6060f1SDimitry Andricclass Enc_a6ce9c : OpcodeHexagon { 2362fe6060f1SDimitry Andric bits <6> Ii; 2363fe6060f1SDimitry Andric let Inst{3-0} = Ii{5-2}; 2364fe6060f1SDimitry Andric bits <4> Rs16; 2365fe6060f1SDimitry Andric let Inst{7-4} = Rs16{3-0}; 2366fe6060f1SDimitry Andric} 2367349cc55cSDimitry Andricclass Enc_a705fc : OpcodeHexagon { 2368349cc55cSDimitry Andric bits <5> Rss32; 2369349cc55cSDimitry Andric let Inst{20-16} = Rss32{4-0}; 2370349cc55cSDimitry Andric bits <7> Sdd128; 2371349cc55cSDimitry Andric let Inst{6-0} = Sdd128{6-0}; 2372349cc55cSDimitry Andric} 2373fe6060f1SDimitry Andricclass Enc_a7341a : OpcodeHexagon { 2374fe6060f1SDimitry Andric bits <5> Vu32; 2375fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 2376fe6060f1SDimitry Andric bits <5> Vv32; 2377fe6060f1SDimitry Andric let Inst{20-16} = Vv32{4-0}; 2378fe6060f1SDimitry Andric bits <5> Vx32; 2379fe6060f1SDimitry Andric let Inst{4-0} = Vx32{4-0}; 2380fe6060f1SDimitry Andric} 2381fe6060f1SDimitry Andricclass Enc_a75aa6 : OpcodeHexagon { 2382fe6060f1SDimitry Andric bits <5> Rs32; 2383fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2384fe6060f1SDimitry Andric bits <5> Rt32; 2385fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 2386fe6060f1SDimitry Andric bits <1> Mu2; 2387fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 2388fe6060f1SDimitry Andric} 2389fe6060f1SDimitry Andricclass Enc_a7b8e8 : OpcodeHexagon { 2390fe6060f1SDimitry Andric bits <6> Ii; 2391fe6060f1SDimitry Andric let Inst{22-21} = Ii{5-4}; 2392fe6060f1SDimitry Andric let Inst{13-13} = Ii{3-3}; 2393fe6060f1SDimitry Andric let Inst{7-5} = Ii{2-0}; 2394fe6060f1SDimitry Andric bits <5> Rs32; 2395fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2396fe6060f1SDimitry Andric bits <5> Rt32; 2397fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 2398fe6060f1SDimitry Andric bits <5> Rd32; 2399fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 2400fe6060f1SDimitry Andric} 2401fe6060f1SDimitry Andricclass Enc_a803e0 : OpcodeHexagon { 2402fe6060f1SDimitry Andric bits <7> Ii; 2403fe6060f1SDimitry Andric let Inst{12-7} = Ii{6-1}; 2404fe6060f1SDimitry Andric bits <8> II; 2405fe6060f1SDimitry Andric let Inst{13-13} = II{7-7}; 2406fe6060f1SDimitry Andric let Inst{6-0} = II{6-0}; 2407fe6060f1SDimitry Andric bits <5> Rs32; 2408fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2409fe6060f1SDimitry Andric} 2410fe6060f1SDimitry Andricclass Enc_a90628 : OpcodeHexagon { 2411fe6060f1SDimitry Andric bits <2> Qv4; 2412fe6060f1SDimitry Andric let Inst{23-22} = Qv4{1-0}; 2413fe6060f1SDimitry Andric bits <5> Vu32; 2414fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 2415fe6060f1SDimitry Andric bits <5> Vx32; 2416fe6060f1SDimitry Andric let Inst{4-0} = Vx32{4-0}; 2417fe6060f1SDimitry Andric} 2418fe6060f1SDimitry Andricclass Enc_a94f3b : OpcodeHexagon { 2419fe6060f1SDimitry Andric bits <5> Rs32; 2420fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2421fe6060f1SDimitry Andric bits <5> Rt32; 2422fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 2423fe6060f1SDimitry Andric bits <5> Rd32; 2424fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 2425fe6060f1SDimitry Andric bits <2> Pe4; 2426fe6060f1SDimitry Andric let Inst{6-5} = Pe4{1-0}; 2427fe6060f1SDimitry Andric} 2428fe6060f1SDimitry Andricclass Enc_aad80c : OpcodeHexagon { 2429fe6060f1SDimitry Andric bits <5> Vuu32; 2430fe6060f1SDimitry Andric let Inst{12-8} = Vuu32{4-0}; 2431fe6060f1SDimitry Andric bits <5> Rt32; 2432fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 2433fe6060f1SDimitry Andric bits <5> Vdd32; 2434fe6060f1SDimitry Andric let Inst{4-0} = Vdd32{4-0}; 2435fe6060f1SDimitry Andric} 2436fe6060f1SDimitry Andricclass Enc_acd6ed : OpcodeHexagon { 2437fe6060f1SDimitry Andric bits <9> Ii; 2438fe6060f1SDimitry Andric let Inst{10-5} = Ii{8-3}; 2439fe6060f1SDimitry Andric bits <2> Pt4; 2440fe6060f1SDimitry Andric let Inst{12-11} = Pt4{1-0}; 2441fe6060f1SDimitry Andric bits <5> Rs32; 2442fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2443fe6060f1SDimitry Andric bits <5> Rdd32; 2444fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 2445fe6060f1SDimitry Andric} 2446fe6060f1SDimitry Andricclass Enc_ad1831 : OpcodeHexagon { 2447fe6060f1SDimitry Andric bits <16> Ii; 2448fe6060f1SDimitry Andric let Inst{26-25} = Ii{15-14}; 2449fe6060f1SDimitry Andric let Inst{20-16} = Ii{13-9}; 2450fe6060f1SDimitry Andric let Inst{13-13} = Ii{8-8}; 2451fe6060f1SDimitry Andric let Inst{7-0} = Ii{7-0}; 2452fe6060f1SDimitry Andric bits <3> Nt8; 2453fe6060f1SDimitry Andric let Inst{10-8} = Nt8{2-0}; 2454fe6060f1SDimitry Andric} 2455fe6060f1SDimitry Andricclass Enc_ad1c74 : OpcodeHexagon { 2456fe6060f1SDimitry Andric bits <11> Ii; 2457fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 2458fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 2459fe6060f1SDimitry Andric bits <4> Rs16; 2460fe6060f1SDimitry Andric let Inst{19-16} = Rs16{3-0}; 2461fe6060f1SDimitry Andric} 2462fe6060f1SDimitry Andricclass Enc_ad9bef : OpcodeHexagon { 2463fe6060f1SDimitry Andric bits <5> Vu32; 2464fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 2465fe6060f1SDimitry Andric bits <5> Rtt32; 2466fe6060f1SDimitry Andric let Inst{20-16} = Rtt32{4-0}; 2467fe6060f1SDimitry Andric bits <5> Vxx32; 2468fe6060f1SDimitry Andric let Inst{4-0} = Vxx32{4-0}; 2469fe6060f1SDimitry Andric} 2470fe6060f1SDimitry Andricclass Enc_adf111 : OpcodeHexagon { 2471fe6060f1SDimitry Andric bits <5> Vu32; 2472fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 2473fe6060f1SDimitry Andric bits <5> Rt32; 2474fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 2475fe6060f1SDimitry Andric bits <2> Qx4; 2476fe6060f1SDimitry Andric let Inst{1-0} = Qx4{1-0}; 2477fe6060f1SDimitry Andric} 2478fe6060f1SDimitry Andricclass Enc_b00112 : OpcodeHexagon { 2479fe6060f1SDimitry Andric bits <5> Rss32; 2480fe6060f1SDimitry Andric let Inst{20-16} = Rss32{4-0}; 2481fe6060f1SDimitry Andric bits <5> Rtt32; 2482fe6060f1SDimitry Andric let Inst{12-8} = Rtt32{4-0}; 2483fe6060f1SDimitry Andric} 2484fe6060f1SDimitry Andricclass Enc_b05839 : OpcodeHexagon { 2485fe6060f1SDimitry Andric bits <7> Ii; 2486fe6060f1SDimitry Andric let Inst{8-5} = Ii{6-3}; 2487fe6060f1SDimitry Andric bits <1> Mu2; 2488fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 2489fe6060f1SDimitry Andric bits <5> Rdd32; 2490fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 2491fe6060f1SDimitry Andric bits <5> Rx32; 2492fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 2493fe6060f1SDimitry Andric} 2494fe6060f1SDimitry Andricclass Enc_b087ac : OpcodeHexagon { 2495fe6060f1SDimitry Andric bits <5> Vu32; 2496fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 2497fe6060f1SDimitry Andric bits <5> Rt32; 2498fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 2499fe6060f1SDimitry Andric bits <5> Vd32; 2500fe6060f1SDimitry Andric let Inst{4-0} = Vd32{4-0}; 2501fe6060f1SDimitry Andric} 2502fe6060f1SDimitry Andricclass Enc_b0e9d8 : OpcodeHexagon { 2503fe6060f1SDimitry Andric bits <10> Ii; 2504fe6060f1SDimitry Andric let Inst{21-21} = Ii{9-9}; 2505fe6060f1SDimitry Andric let Inst{13-5} = Ii{8-0}; 2506fe6060f1SDimitry Andric bits <5> Rs32; 2507fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2508fe6060f1SDimitry Andric bits <5> Rx32; 2509fe6060f1SDimitry Andric let Inst{4-0} = Rx32{4-0}; 2510fe6060f1SDimitry Andric} 2511fe6060f1SDimitry Andricclass Enc_b15941 : OpcodeHexagon { 2512fe6060f1SDimitry Andric bits <4> Ii; 2513fe6060f1SDimitry Andric let Inst{6-3} = Ii{3-0}; 2514fe6060f1SDimitry Andric bits <1> Mu2; 2515fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 2516fe6060f1SDimitry Andric bits <5> Rt32; 2517fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 2518fe6060f1SDimitry Andric bits <5> Rx32; 2519fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 2520fe6060f1SDimitry Andric} 2521fe6060f1SDimitry Andricclass Enc_b1e1fb : OpcodeHexagon { 2522fe6060f1SDimitry Andric bits <11> Ii; 2523fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 2524fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 2525fe6060f1SDimitry Andric bits <4> Rs16; 2526fe6060f1SDimitry Andric let Inst{19-16} = Rs16{3-0}; 2527fe6060f1SDimitry Andric bits <5> n1; 2528fe6060f1SDimitry Andric let Inst{28-28} = n1{4-4}; 2529fe6060f1SDimitry Andric let Inst{25-23} = n1{3-1}; 2530fe6060f1SDimitry Andric let Inst{8-8} = n1{0-0}; 2531fe6060f1SDimitry Andric} 2532fe6060f1SDimitry Andricclass Enc_b388cf : OpcodeHexagon { 2533fe6060f1SDimitry Andric bits <5> Ii; 2534fe6060f1SDimitry Andric let Inst{12-8} = Ii{4-0}; 2535fe6060f1SDimitry Andric bits <5> II; 2536fe6060f1SDimitry Andric let Inst{22-21} = II{4-3}; 2537fe6060f1SDimitry Andric let Inst{7-5} = II{2-0}; 2538fe6060f1SDimitry Andric bits <5> Rs32; 2539fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2540fe6060f1SDimitry Andric bits <5> Rd32; 2541fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 2542fe6060f1SDimitry Andric} 2543fe6060f1SDimitry Andricclass Enc_b38ffc : OpcodeHexagon { 2544fe6060f1SDimitry Andric bits <4> Ii; 2545fe6060f1SDimitry Andric let Inst{11-8} = Ii{3-0}; 2546fe6060f1SDimitry Andric bits <4> Rs16; 2547fe6060f1SDimitry Andric let Inst{7-4} = Rs16{3-0}; 2548fe6060f1SDimitry Andric bits <4> Rt16; 2549fe6060f1SDimitry Andric let Inst{3-0} = Rt16{3-0}; 2550fe6060f1SDimitry Andric} 2551fe6060f1SDimitry Andricclass Enc_b43b67 : OpcodeHexagon { 2552fe6060f1SDimitry Andric bits <5> Vu32; 2553fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 2554fe6060f1SDimitry Andric bits <5> Vv32; 2555fe6060f1SDimitry Andric let Inst{20-16} = Vv32{4-0}; 2556fe6060f1SDimitry Andric bits <5> Vd32; 2557fe6060f1SDimitry Andric let Inst{4-0} = Vd32{4-0}; 2558fe6060f1SDimitry Andric bits <2> Qx4; 2559fe6060f1SDimitry Andric let Inst{6-5} = Qx4{1-0}; 2560fe6060f1SDimitry Andric} 2561fe6060f1SDimitry Andricclass Enc_b4e6cf : OpcodeHexagon { 2562fe6060f1SDimitry Andric bits <10> Ii; 2563fe6060f1SDimitry Andric let Inst{21-21} = Ii{9-9}; 2564fe6060f1SDimitry Andric let Inst{13-5} = Ii{8-0}; 2565fe6060f1SDimitry Andric bits <5> Ru32; 2566fe6060f1SDimitry Andric let Inst{4-0} = Ru32{4-0}; 2567fe6060f1SDimitry Andric bits <5> Rx32; 2568fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 2569fe6060f1SDimitry Andric} 2570fe6060f1SDimitry Andricclass Enc_b62ef7 : OpcodeHexagon { 2571fe6060f1SDimitry Andric bits <3> Ii; 2572fe6060f1SDimitry Andric let Inst{10-8} = Ii{2-0}; 2573fe6060f1SDimitry Andric bits <5> Vs32; 2574fe6060f1SDimitry Andric let Inst{4-0} = Vs32{4-0}; 2575fe6060f1SDimitry Andric bits <5> Rx32; 2576fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 2577fe6060f1SDimitry Andric} 2578fe6060f1SDimitry Andricclass Enc_b72622 : OpcodeHexagon { 2579fe6060f1SDimitry Andric bits <2> Ii; 2580fe6060f1SDimitry Andric let Inst{13-13} = Ii{1-1}; 2581fe6060f1SDimitry Andric let Inst{5-5} = Ii{0-0}; 2582fe6060f1SDimitry Andric bits <5> Rss32; 2583fe6060f1SDimitry Andric let Inst{20-16} = Rss32{4-0}; 2584fe6060f1SDimitry Andric bits <5> Rt32; 2585fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 2586fe6060f1SDimitry Andric bits <5> Rxx32; 2587fe6060f1SDimitry Andric let Inst{4-0} = Rxx32{4-0}; 2588fe6060f1SDimitry Andric} 2589fe6060f1SDimitry Andricclass Enc_b78edd : OpcodeHexagon { 2590fe6060f1SDimitry Andric bits <11> Ii; 2591fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 2592fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 2593fe6060f1SDimitry Andric bits <4> Rs16; 2594fe6060f1SDimitry Andric let Inst{19-16} = Rs16{3-0}; 2595fe6060f1SDimitry Andric bits <4> n1; 2596fe6060f1SDimitry Andric let Inst{28-28} = n1{3-3}; 2597fe6060f1SDimitry Andric let Inst{24-23} = n1{2-1}; 2598fe6060f1SDimitry Andric let Inst{8-8} = n1{0-0}; 2599fe6060f1SDimitry Andric} 2600fe6060f1SDimitry Andricclass Enc_b7fad3 : OpcodeHexagon { 2601fe6060f1SDimitry Andric bits <2> Pv4; 2602fe6060f1SDimitry Andric let Inst{9-8} = Pv4{1-0}; 2603fe6060f1SDimitry Andric bits <5> Rs32; 2604fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2605fe6060f1SDimitry Andric bits <5> Rdd32; 2606fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 2607fe6060f1SDimitry Andric} 2608fe6060f1SDimitry Andricclass Enc_b8309d : OpcodeHexagon { 2609fe6060f1SDimitry Andric bits <9> Ii; 2610fe6060f1SDimitry Andric let Inst{8-3} = Ii{8-3}; 2611fe6060f1SDimitry Andric bits <3> Rtt8; 2612fe6060f1SDimitry Andric let Inst{2-0} = Rtt8{2-0}; 2613fe6060f1SDimitry Andric} 2614fe6060f1SDimitry Andricclass Enc_b84c4c : OpcodeHexagon { 2615fe6060f1SDimitry Andric bits <6> Ii; 2616fe6060f1SDimitry Andric let Inst{13-8} = Ii{5-0}; 2617fe6060f1SDimitry Andric bits <6> II; 2618fe6060f1SDimitry Andric let Inst{23-21} = II{5-3}; 2619fe6060f1SDimitry Andric let Inst{7-5} = II{2-0}; 2620fe6060f1SDimitry Andric bits <5> Rss32; 2621fe6060f1SDimitry Andric let Inst{20-16} = Rss32{4-0}; 2622fe6060f1SDimitry Andric bits <5> Rdd32; 2623fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 2624fe6060f1SDimitry Andric} 2625fe6060f1SDimitry Andricclass Enc_b886fd : OpcodeHexagon { 2626fe6060f1SDimitry Andric bits <5> Ii; 2627fe6060f1SDimitry Andric let Inst{6-3} = Ii{4-1}; 2628fe6060f1SDimitry Andric bits <2> Pv4; 2629fe6060f1SDimitry Andric let Inst{1-0} = Pv4{1-0}; 2630fe6060f1SDimitry Andric bits <5> Rt32; 2631fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 2632fe6060f1SDimitry Andric bits <5> Rx32; 2633fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 2634fe6060f1SDimitry Andric} 2635fe6060f1SDimitry Andricclass Enc_b8c967 : OpcodeHexagon { 2636fe6060f1SDimitry Andric bits <8> Ii; 2637fe6060f1SDimitry Andric let Inst{12-5} = Ii{7-0}; 2638fe6060f1SDimitry Andric bits <5> Rs32; 2639fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2640fe6060f1SDimitry Andric bits <5> Rd32; 2641fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 2642fe6060f1SDimitry Andric} 2643fe6060f1SDimitry Andricclass Enc_b909d2 : OpcodeHexagon { 2644fe6060f1SDimitry Andric bits <11> Ii; 2645fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 2646fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 2647fe6060f1SDimitry Andric bits <4> Rs16; 2648fe6060f1SDimitry Andric let Inst{19-16} = Rs16{3-0}; 2649fe6060f1SDimitry Andric bits <7> n1; 2650fe6060f1SDimitry Andric let Inst{28-28} = n1{6-6}; 2651fe6060f1SDimitry Andric let Inst{25-22} = n1{5-2}; 2652fe6060f1SDimitry Andric let Inst{13-13} = n1{1-1}; 2653fe6060f1SDimitry Andric let Inst{8-8} = n1{0-0}; 2654fe6060f1SDimitry Andric} 2655fe6060f1SDimitry Andricclass Enc_b91167 : OpcodeHexagon { 2656fe6060f1SDimitry Andric bits <2> Ii; 2657fe6060f1SDimitry Andric let Inst{6-5} = Ii{1-0}; 2658fe6060f1SDimitry Andric bits <5> Vuu32; 2659fe6060f1SDimitry Andric let Inst{12-8} = Vuu32{4-0}; 2660fe6060f1SDimitry Andric bits <5> Vvv32; 2661fe6060f1SDimitry Andric let Inst{20-16} = Vvv32{4-0}; 2662fe6060f1SDimitry Andric bits <5> Vdd32; 2663fe6060f1SDimitry Andric let Inst{4-0} = Vdd32{4-0}; 2664fe6060f1SDimitry Andric} 2665fe6060f1SDimitry Andricclass Enc_b97f71 : OpcodeHexagon { 2666fe6060f1SDimitry Andric bits <6> Ii; 2667fe6060f1SDimitry Andric let Inst{8-5} = Ii{5-2}; 2668fe6060f1SDimitry Andric bits <2> Pt4; 2669fe6060f1SDimitry Andric let Inst{10-9} = Pt4{1-0}; 2670fe6060f1SDimitry Andric bits <5> Rd32; 2671fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 2672fe6060f1SDimitry Andric bits <5> Rx32; 2673fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 2674fe6060f1SDimitry Andric} 2675fe6060f1SDimitry Andricclass Enc_b9c5fb : OpcodeHexagon { 2676fe6060f1SDimitry Andric bits <5> Rss32; 2677fe6060f1SDimitry Andric let Inst{20-16} = Rss32{4-0}; 2678fe6060f1SDimitry Andric bits <5> Rdd32; 2679fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 2680fe6060f1SDimitry Andric} 2681fe6060f1SDimitry Andricclass Enc_bc03e5 : OpcodeHexagon { 2682fe6060f1SDimitry Andric bits <17> Ii; 2683fe6060f1SDimitry Andric let Inst{26-25} = Ii{16-15}; 2684fe6060f1SDimitry Andric let Inst{20-16} = Ii{14-10}; 2685fe6060f1SDimitry Andric let Inst{13-13} = Ii{9-9}; 2686fe6060f1SDimitry Andric let Inst{7-0} = Ii{8-1}; 2687fe6060f1SDimitry Andric bits <3> Nt8; 2688fe6060f1SDimitry Andric let Inst{10-8} = Nt8{2-0}; 2689fe6060f1SDimitry Andric} 2690fe6060f1SDimitry Andricclass Enc_bd0b33 : OpcodeHexagon { 2691fe6060f1SDimitry Andric bits <10> Ii; 2692fe6060f1SDimitry Andric let Inst{21-21} = Ii{9-9}; 2693fe6060f1SDimitry Andric let Inst{13-5} = Ii{8-0}; 2694fe6060f1SDimitry Andric bits <5> Rs32; 2695fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2696fe6060f1SDimitry Andric bits <2> Pd4; 2697fe6060f1SDimitry Andric let Inst{1-0} = Pd4{1-0}; 2698fe6060f1SDimitry Andric} 2699fe6060f1SDimitry Andricclass Enc_bd1cbc : OpcodeHexagon { 2700fe6060f1SDimitry Andric bits <5> Ii; 2701fe6060f1SDimitry Andric let Inst{8-5} = Ii{4-1}; 2702fe6060f1SDimitry Andric bits <5> Ryy32; 2703fe6060f1SDimitry Andric let Inst{4-0} = Ryy32{4-0}; 2704fe6060f1SDimitry Andric bits <5> Rx32; 2705fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 2706fe6060f1SDimitry Andric} 2707fe6060f1SDimitry Andricclass Enc_bd6011 : OpcodeHexagon { 2708fe6060f1SDimitry Andric bits <5> Rt32; 2709fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 2710fe6060f1SDimitry Andric bits <5> Rs32; 2711fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2712fe6060f1SDimitry Andric bits <5> Rd32; 2713fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 2714fe6060f1SDimitry Andric} 2715fe6060f1SDimitry Andricclass Enc_bd811a : OpcodeHexagon { 2716fe6060f1SDimitry Andric bits <5> Rs32; 2717fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2718fe6060f1SDimitry Andric bits <5> Cd32; 2719fe6060f1SDimitry Andric let Inst{4-0} = Cd32{4-0}; 2720fe6060f1SDimitry Andric} 2721fe6060f1SDimitry Andricclass Enc_bddee3 : OpcodeHexagon { 2722fe6060f1SDimitry Andric bits <5> Vu32; 2723fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 2724fe6060f1SDimitry Andric bits <5> Vyyyy32; 2725fe6060f1SDimitry Andric let Inst{4-0} = Vyyyy32{4-0}; 2726fe6060f1SDimitry Andric bits <3> Rx8; 2727fe6060f1SDimitry Andric let Inst{18-16} = Rx8{2-0}; 2728fe6060f1SDimitry Andric} 2729fe6060f1SDimitry Andricclass Enc_be32a5 : OpcodeHexagon { 2730fe6060f1SDimitry Andric bits <5> Rs32; 2731fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2732fe6060f1SDimitry Andric bits <5> Rt32; 2733fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 2734fe6060f1SDimitry Andric bits <5> Rdd32; 2735fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 2736fe6060f1SDimitry Andric} 2737fe6060f1SDimitry Andricclass Enc_bfbf03 : OpcodeHexagon { 2738fe6060f1SDimitry Andric bits <2> Qs4; 2739fe6060f1SDimitry Andric let Inst{9-8} = Qs4{1-0}; 2740fe6060f1SDimitry Andric bits <2> Qd4; 2741fe6060f1SDimitry Andric let Inst{1-0} = Qd4{1-0}; 2742fe6060f1SDimitry Andric} 2743fe6060f1SDimitry Andricclass Enc_c0cdde : OpcodeHexagon { 2744fe6060f1SDimitry Andric bits <9> Ii; 2745fe6060f1SDimitry Andric let Inst{13-5} = Ii{8-0}; 2746fe6060f1SDimitry Andric bits <5> Rs32; 2747fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2748fe6060f1SDimitry Andric bits <2> Pd4; 2749fe6060f1SDimitry Andric let Inst{1-0} = Pd4{1-0}; 2750fe6060f1SDimitry Andric} 2751fe6060f1SDimitry Andricclass Enc_c175d0 : OpcodeHexagon { 2752fe6060f1SDimitry Andric bits <4> Ii; 2753fe6060f1SDimitry Andric let Inst{11-8} = Ii{3-0}; 2754fe6060f1SDimitry Andric bits <4> Rs16; 2755fe6060f1SDimitry Andric let Inst{7-4} = Rs16{3-0}; 2756fe6060f1SDimitry Andric bits <4> Rd16; 2757fe6060f1SDimitry Andric let Inst{3-0} = Rd16{3-0}; 2758fe6060f1SDimitry Andric} 2759fe6060f1SDimitry Andricclass Enc_c1d806 : OpcodeHexagon { 2760fe6060f1SDimitry Andric bits <5> Vu32; 2761fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 2762fe6060f1SDimitry Andric bits <5> Vv32; 2763fe6060f1SDimitry Andric let Inst{20-16} = Vv32{4-0}; 2764fe6060f1SDimitry Andric bits <5> Vd32; 2765fe6060f1SDimitry Andric let Inst{4-0} = Vd32{4-0}; 2766fe6060f1SDimitry Andric bits <2> Qe4; 2767fe6060f1SDimitry Andric let Inst{6-5} = Qe4{1-0}; 2768fe6060f1SDimitry Andric} 2769fe6060f1SDimitry Andricclass Enc_c2b48e : OpcodeHexagon { 2770fe6060f1SDimitry Andric bits <5> Rs32; 2771fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2772fe6060f1SDimitry Andric bits <5> Rt32; 2773fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 2774fe6060f1SDimitry Andric bits <2> Pd4; 2775fe6060f1SDimitry Andric let Inst{1-0} = Pd4{1-0}; 2776fe6060f1SDimitry Andric} 2777fe6060f1SDimitry Andricclass Enc_c31910 : OpcodeHexagon { 2778fe6060f1SDimitry Andric bits <8> Ii; 2779fe6060f1SDimitry Andric let Inst{23-21} = Ii{7-5}; 2780fe6060f1SDimitry Andric let Inst{13-13} = Ii{4-4}; 2781fe6060f1SDimitry Andric let Inst{7-5} = Ii{3-1}; 2782fe6060f1SDimitry Andric let Inst{3-3} = Ii{0-0}; 2783fe6060f1SDimitry Andric bits <5> II; 2784fe6060f1SDimitry Andric let Inst{12-8} = II{4-0}; 2785fe6060f1SDimitry Andric bits <5> Rx32; 2786fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 2787fe6060f1SDimitry Andric} 2788fe6060f1SDimitry Andricclass Enc_c4dc92 : OpcodeHexagon { 2789fe6060f1SDimitry Andric bits <2> Qv4; 2790fe6060f1SDimitry Andric let Inst{23-22} = Qv4{1-0}; 2791fe6060f1SDimitry Andric bits <5> Vu32; 2792fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 2793fe6060f1SDimitry Andric bits <5> Vd32; 2794fe6060f1SDimitry Andric let Inst{4-0} = Vd32{4-0}; 2795fe6060f1SDimitry Andric} 2796fe6060f1SDimitry Andricclass Enc_c6220b : OpcodeHexagon { 2797fe6060f1SDimitry Andric bits <2> Ii; 2798fe6060f1SDimitry Andric let Inst{13-13} = Ii{1-1}; 2799fe6060f1SDimitry Andric let Inst{7-7} = Ii{0-0}; 2800fe6060f1SDimitry Andric bits <5> Rs32; 2801fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2802fe6060f1SDimitry Andric bits <5> Ru32; 2803fe6060f1SDimitry Andric let Inst{12-8} = Ru32{4-0}; 2804fe6060f1SDimitry Andric bits <3> Nt8; 2805fe6060f1SDimitry Andric let Inst{2-0} = Nt8{2-0}; 2806fe6060f1SDimitry Andric} 2807fe6060f1SDimitry Andricclass Enc_c7a204 : OpcodeHexagon { 2808fe6060f1SDimitry Andric bits <6> II; 2809fe6060f1SDimitry Andric let Inst{5-0} = II{5-0}; 2810fe6060f1SDimitry Andric bits <5> Rtt32; 2811fe6060f1SDimitry Andric let Inst{12-8} = Rtt32{4-0}; 2812fe6060f1SDimitry Andric bits <5> Re32; 2813fe6060f1SDimitry Andric let Inst{20-16} = Re32{4-0}; 2814fe6060f1SDimitry Andric} 2815fe6060f1SDimitry Andricclass Enc_c7cd90 : OpcodeHexagon { 2816fe6060f1SDimitry Andric bits <4> Ii; 2817fe6060f1SDimitry Andric let Inst{6-3} = Ii{3-0}; 2818fe6060f1SDimitry Andric bits <3> Nt8; 2819fe6060f1SDimitry Andric let Inst{10-8} = Nt8{2-0}; 2820fe6060f1SDimitry Andric bits <5> Rx32; 2821fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 2822fe6060f1SDimitry Andric} 2823fe6060f1SDimitry Andricclass Enc_c85e2a : OpcodeHexagon { 2824fe6060f1SDimitry Andric bits <5> Ii; 2825fe6060f1SDimitry Andric let Inst{12-8} = Ii{4-0}; 2826fe6060f1SDimitry Andric bits <5> II; 2827fe6060f1SDimitry Andric let Inst{22-21} = II{4-3}; 2828fe6060f1SDimitry Andric let Inst{7-5} = II{2-0}; 2829fe6060f1SDimitry Andric bits <5> Rd32; 2830fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 2831fe6060f1SDimitry Andric} 2832fe6060f1SDimitry Andricclass Enc_c90aca : OpcodeHexagon { 2833fe6060f1SDimitry Andric bits <8> Ii; 2834fe6060f1SDimitry Andric let Inst{12-5} = Ii{7-0}; 2835fe6060f1SDimitry Andric bits <5> Rs32; 2836fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2837fe6060f1SDimitry Andric bits <5> Rx32; 2838fe6060f1SDimitry Andric let Inst{4-0} = Rx32{4-0}; 2839fe6060f1SDimitry Andric} 2840fe6060f1SDimitry Andricclass Enc_c9a18e : OpcodeHexagon { 2841fe6060f1SDimitry Andric bits <11> Ii; 2842fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 2843fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 2844fe6060f1SDimitry Andric bits <3> Ns8; 2845fe6060f1SDimitry Andric let Inst{18-16} = Ns8{2-0}; 2846fe6060f1SDimitry Andric bits <5> Rt32; 2847fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 2848fe6060f1SDimitry Andric} 2849fe6060f1SDimitry Andricclass Enc_c9e3bc : OpcodeHexagon { 2850fe6060f1SDimitry Andric bits <4> Ii; 2851fe6060f1SDimitry Andric let Inst{13-13} = Ii{3-3}; 2852fe6060f1SDimitry Andric let Inst{10-8} = Ii{2-0}; 2853fe6060f1SDimitry Andric bits <5> Rt32; 2854fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 2855fe6060f1SDimitry Andric bits <5> Vs32; 2856fe6060f1SDimitry Andric let Inst{4-0} = Vs32{4-0}; 2857fe6060f1SDimitry Andric} 2858fe6060f1SDimitry Andricclass Enc_ca3887 : OpcodeHexagon { 2859fe6060f1SDimitry Andric bits <5> Rs32; 2860fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2861fe6060f1SDimitry Andric bits <5> Rt32; 2862fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 2863fe6060f1SDimitry Andric} 2864fe6060f1SDimitry Andricclass Enc_cb4b4e : OpcodeHexagon { 2865fe6060f1SDimitry Andric bits <2> Pu4; 2866fe6060f1SDimitry Andric let Inst{6-5} = Pu4{1-0}; 2867fe6060f1SDimitry Andric bits <5> Rs32; 2868fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2869fe6060f1SDimitry Andric bits <5> Rt32; 2870fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 2871fe6060f1SDimitry Andric bits <5> Rdd32; 2872fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 2873fe6060f1SDimitry Andric} 2874fe6060f1SDimitry Andricclass Enc_cb785b : OpcodeHexagon { 2875fe6060f1SDimitry Andric bits <5> Vu32; 2876fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 2877fe6060f1SDimitry Andric bits <5> Rtt32; 2878fe6060f1SDimitry Andric let Inst{20-16} = Rtt32{4-0}; 2879fe6060f1SDimitry Andric bits <5> Vdd32; 2880fe6060f1SDimitry Andric let Inst{4-0} = Vdd32{4-0}; 2881fe6060f1SDimitry Andric} 2882fe6060f1SDimitry Andricclass Enc_cb9321 : OpcodeHexagon { 2883fe6060f1SDimitry Andric bits <16> Ii; 2884fe6060f1SDimitry Andric let Inst{27-21} = Ii{15-9}; 2885fe6060f1SDimitry Andric let Inst{13-5} = Ii{8-0}; 2886fe6060f1SDimitry Andric bits <5> Rs32; 2887fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2888fe6060f1SDimitry Andric bits <5> Rd32; 2889fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 2890fe6060f1SDimitry Andric} 2891fe6060f1SDimitry Andricclass Enc_cc449f : OpcodeHexagon { 2892fe6060f1SDimitry Andric bits <4> Ii; 2893fe6060f1SDimitry Andric let Inst{6-3} = Ii{3-0}; 2894fe6060f1SDimitry Andric bits <2> Pv4; 2895fe6060f1SDimitry Andric let Inst{1-0} = Pv4{1-0}; 2896fe6060f1SDimitry Andric bits <5> Rt32; 2897fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 2898fe6060f1SDimitry Andric bits <5> Rx32; 2899fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 2900fe6060f1SDimitry Andric} 2901fe6060f1SDimitry Andricclass Enc_cc857d : OpcodeHexagon { 2902fe6060f1SDimitry Andric bits <5> Vuu32; 2903fe6060f1SDimitry Andric let Inst{12-8} = Vuu32{4-0}; 2904fe6060f1SDimitry Andric bits <5> Rt32; 2905fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 2906fe6060f1SDimitry Andric bits <5> Vx32; 2907fe6060f1SDimitry Andric let Inst{4-0} = Vx32{4-0}; 2908fe6060f1SDimitry Andric} 2909fe6060f1SDimitry Andricclass Enc_cd4705 : OpcodeHexagon { 2910fe6060f1SDimitry Andric bits <3> Ii; 2911fe6060f1SDimitry Andric let Inst{7-5} = Ii{2-0}; 2912fe6060f1SDimitry Andric bits <5> Vu32; 2913fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 2914fe6060f1SDimitry Andric bits <5> Vv32; 2915fe6060f1SDimitry Andric let Inst{20-16} = Vv32{4-0}; 2916fe6060f1SDimitry Andric bits <5> Vx32; 2917fe6060f1SDimitry Andric let Inst{4-0} = Vx32{4-0}; 2918fe6060f1SDimitry Andric} 2919fe6060f1SDimitry Andricclass Enc_cd82bc : OpcodeHexagon { 2920fe6060f1SDimitry Andric bits <4> Ii; 2921fe6060f1SDimitry Andric let Inst{21-21} = Ii{3-3}; 2922fe6060f1SDimitry Andric let Inst{7-5} = Ii{2-0}; 2923fe6060f1SDimitry Andric bits <6> II; 2924fe6060f1SDimitry Andric let Inst{13-8} = II{5-0}; 2925fe6060f1SDimitry Andric bits <5> Rs32; 2926fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2927fe6060f1SDimitry Andric bits <5> Rx32; 2928fe6060f1SDimitry Andric let Inst{4-0} = Rx32{4-0}; 2929fe6060f1SDimitry Andric} 2930fe6060f1SDimitry Andricclass Enc_cda00a : OpcodeHexagon { 2931fe6060f1SDimitry Andric bits <12> Ii; 2932fe6060f1SDimitry Andric let Inst{19-16} = Ii{11-8}; 2933fe6060f1SDimitry Andric let Inst{12-5} = Ii{7-0}; 2934fe6060f1SDimitry Andric bits <2> Pu4; 2935fe6060f1SDimitry Andric let Inst{22-21} = Pu4{1-0}; 2936fe6060f1SDimitry Andric bits <5> Rd32; 2937fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 2938fe6060f1SDimitry Andric} 2939fe6060f1SDimitry Andricclass Enc_ce6828 : OpcodeHexagon { 2940fe6060f1SDimitry Andric bits <14> Ii; 2941fe6060f1SDimitry Andric let Inst{26-25} = Ii{13-12}; 2942fe6060f1SDimitry Andric let Inst{13-13} = Ii{11-11}; 2943fe6060f1SDimitry Andric let Inst{7-0} = Ii{10-3}; 2944fe6060f1SDimitry Andric bits <5> Rs32; 2945fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 2946fe6060f1SDimitry Andric bits <5> Rtt32; 2947fe6060f1SDimitry Andric let Inst{12-8} = Rtt32{4-0}; 2948fe6060f1SDimitry Andric} 2949fe6060f1SDimitry Andricclass Enc_cf1927 : OpcodeHexagon { 2950fe6060f1SDimitry Andric bits <1> Mu2; 2951fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 2952fe6060f1SDimitry Andric bits <3> Os8; 2953fe6060f1SDimitry Andric let Inst{2-0} = Os8{2-0}; 2954fe6060f1SDimitry Andric bits <5> Rx32; 2955fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 2956fe6060f1SDimitry Andric} 2957fe6060f1SDimitry Andricclass Enc_d15d19 : OpcodeHexagon { 2958fe6060f1SDimitry Andric bits <1> Mu2; 2959fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 2960fe6060f1SDimitry Andric bits <5> Vs32; 2961fe6060f1SDimitry Andric let Inst{4-0} = Vs32{4-0}; 2962fe6060f1SDimitry Andric bits <5> Rx32; 2963fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 2964fe6060f1SDimitry Andric} 29655ffd83dbSDimitry Andricclass Enc_d2216a : OpcodeHexagon { 29665ffd83dbSDimitry Andric bits <5> Rss32; 29675ffd83dbSDimitry Andric let Inst{20-16} = Rss32{4-0}; 29685ffd83dbSDimitry Andric bits <5> Rtt32; 29695ffd83dbSDimitry Andric let Inst{12-8} = Rtt32{4-0}; 29705ffd83dbSDimitry Andric bits <5> Rd32; 29715ffd83dbSDimitry Andric let Inst{4-0} = Rd32{4-0}; 29725ffd83dbSDimitry Andric} 29735ffd83dbSDimitry Andricclass Enc_d2c7f1 : OpcodeHexagon { 29745ffd83dbSDimitry Andric bits <5> Rtt32; 29755ffd83dbSDimitry Andric let Inst{12-8} = Rtt32{4-0}; 29765ffd83dbSDimitry Andric bits <5> Rss32; 29775ffd83dbSDimitry Andric let Inst{20-16} = Rss32{4-0}; 29785ffd83dbSDimitry Andric bits <5> Rdd32; 29795ffd83dbSDimitry Andric let Inst{4-0} = Rdd32{4-0}; 29805ffd83dbSDimitry Andric bits <2> Pe4; 29815ffd83dbSDimitry Andric let Inst{6-5} = Pe4{1-0}; 29825ffd83dbSDimitry Andric} 29835ffd83dbSDimitry Andricclass Enc_d44e31 : OpcodeHexagon { 29845ffd83dbSDimitry Andric bits <6> Ii; 29855ffd83dbSDimitry Andric let Inst{12-7} = Ii{5-0}; 29865ffd83dbSDimitry Andric bits <5> Rs32; 29875ffd83dbSDimitry Andric let Inst{20-16} = Rs32{4-0}; 29885ffd83dbSDimitry Andric bits <5> Rt32; 29895ffd83dbSDimitry Andric let Inst{4-0} = Rt32{4-0}; 29905ffd83dbSDimitry Andric} 2991fe6060f1SDimitry Andricclass Enc_d483b9 : OpcodeHexagon { 2992fe6060f1SDimitry Andric bits <1> Ii; 2993fe6060f1SDimitry Andric let Inst{5-5} = Ii{0-0}; 2994fe6060f1SDimitry Andric bits <5> Vuu32; 2995fe6060f1SDimitry Andric let Inst{12-8} = Vuu32{4-0}; 29965ffd83dbSDimitry Andric bits <5> Rt32; 2997fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 2998fe6060f1SDimitry Andric bits <5> Vxx32; 2999fe6060f1SDimitry Andric let Inst{4-0} = Vxx32{4-0}; 30005ffd83dbSDimitry Andric} 3001fe6060f1SDimitry Andricclass Enc_d50cd3 : OpcodeHexagon { 3002fe6060f1SDimitry Andric bits <3> Ii; 3003fe6060f1SDimitry Andric let Inst{7-5} = Ii{2-0}; 3004fe6060f1SDimitry Andric bits <5> Rss32; 3005fe6060f1SDimitry Andric let Inst{20-16} = Rss32{4-0}; 3006fe6060f1SDimitry Andric bits <5> Rtt32; 3007fe6060f1SDimitry Andric let Inst{12-8} = Rtt32{4-0}; 3008fe6060f1SDimitry Andric bits <5> Rdd32; 3009fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 3010fe6060f1SDimitry Andric} 3011fe6060f1SDimitry Andricclass Enc_d5c73f : OpcodeHexagon { 3012fe6060f1SDimitry Andric bits <1> Mu2; 3013fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 30145ffd83dbSDimitry Andric bits <5> Rt32; 3015fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 3016fe6060f1SDimitry Andric bits <5> Rx32; 3017fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 30185ffd83dbSDimitry Andric} 3019fe6060f1SDimitry Andricclass Enc_d6990d : OpcodeHexagon { 3020fe6060f1SDimitry Andric bits <5> Vuu32; 3021fe6060f1SDimitry Andric let Inst{12-8} = Vuu32{4-0}; 3022fe6060f1SDimitry Andric bits <5> Rt32; 3023fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 3024fe6060f1SDimitry Andric bits <5> Vxx32; 3025fe6060f1SDimitry Andric let Inst{4-0} = Vxx32{4-0}; 3026fe6060f1SDimitry Andric} 3027fe6060f1SDimitry Andricclass Enc_d7a65e : OpcodeHexagon { 30285ffd83dbSDimitry Andric bits <6> Ii; 30295ffd83dbSDimitry Andric let Inst{12-7} = Ii{5-0}; 3030fe6060f1SDimitry Andric bits <6> II; 3031fe6060f1SDimitry Andric let Inst{13-13} = II{5-5}; 30325ffd83dbSDimitry Andric let Inst{4-0} = II{4-0}; 3033fe6060f1SDimitry Andric bits <2> Pv4; 3034fe6060f1SDimitry Andric let Inst{6-5} = Pv4{1-0}; 30355ffd83dbSDimitry Andric bits <5> Rs32; 30365ffd83dbSDimitry Andric let Inst{20-16} = Rs32{4-0}; 30375ffd83dbSDimitry Andric} 3038fe6060f1SDimitry Andricclass Enc_d7bc34 : OpcodeHexagon { 3039fe6060f1SDimitry Andric bits <5> Vu32; 3040fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 3041fe6060f1SDimitry Andric bits <3> Rt8; 3042fe6060f1SDimitry Andric let Inst{18-16} = Rt8{2-0}; 3043fe6060f1SDimitry Andric bits <5> Vyyyy32; 3044fe6060f1SDimitry Andric let Inst{4-0} = Vyyyy32{4-0}; 3045fe6060f1SDimitry Andric} 3046fe6060f1SDimitry Andricclass Enc_d7dc10 : OpcodeHexagon { 30475ffd83dbSDimitry Andric bits <5> Rs32; 30485ffd83dbSDimitry Andric let Inst{20-16} = Rs32{4-0}; 3049fe6060f1SDimitry Andric bits <5> Rtt32; 3050fe6060f1SDimitry Andric let Inst{12-8} = Rtt32{4-0}; 3051fe6060f1SDimitry Andric bits <2> Pd4; 3052fe6060f1SDimitry Andric let Inst{1-0} = Pd4{1-0}; 30535ffd83dbSDimitry Andric} 30545ffd83dbSDimitry Andricclass Enc_da664b : OpcodeHexagon { 30555ffd83dbSDimitry Andric bits <2> Ii; 30565ffd83dbSDimitry Andric let Inst{13-13} = Ii{1-1}; 30575ffd83dbSDimitry Andric let Inst{7-7} = Ii{0-0}; 30585ffd83dbSDimitry Andric bits <5> Rs32; 30595ffd83dbSDimitry Andric let Inst{20-16} = Rs32{4-0}; 30605ffd83dbSDimitry Andric bits <5> Rt32; 30615ffd83dbSDimitry Andric let Inst{12-8} = Rt32{4-0}; 30625ffd83dbSDimitry Andric bits <5> Rd32; 30635ffd83dbSDimitry Andric let Inst{4-0} = Rd32{4-0}; 30640b57cec5SDimitry Andric} 30655ffd83dbSDimitry Andricclass Enc_da8d43 : OpcodeHexagon { 30665ffd83dbSDimitry Andric bits <6> Ii; 30675ffd83dbSDimitry Andric let Inst{13-13} = Ii{5-5}; 30685ffd83dbSDimitry Andric let Inst{7-3} = Ii{4-0}; 30695ffd83dbSDimitry Andric bits <2> Pv4; 30705ffd83dbSDimitry Andric let Inst{1-0} = Pv4{1-0}; 30715ffd83dbSDimitry Andric bits <5> Rs32; 30725ffd83dbSDimitry Andric let Inst{20-16} = Rs32{4-0}; 30735ffd83dbSDimitry Andric bits <5> Rt32; 30745ffd83dbSDimitry Andric let Inst{12-8} = Rt32{4-0}; 30755ffd83dbSDimitry Andric} 3076fe6060f1SDimitry Andricclass Enc_daea09 : OpcodeHexagon { 3077fe6060f1SDimitry Andric bits <17> Ii; 3078fe6060f1SDimitry Andric let Inst{23-22} = Ii{16-15}; 3079fe6060f1SDimitry Andric let Inst{20-16} = Ii{14-10}; 3080fe6060f1SDimitry Andric let Inst{13-13} = Ii{9-9}; 3081fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 3082fe6060f1SDimitry Andric bits <2> Pu4; 3083fe6060f1SDimitry Andric let Inst{9-8} = Pu4{1-0}; 3084fe6060f1SDimitry Andric} 3085fe6060f1SDimitry Andricclass Enc_db40cd : OpcodeHexagon { 3086fe6060f1SDimitry Andric bits <6> Ii; 3087fe6060f1SDimitry Andric let Inst{6-3} = Ii{5-2}; 30885ffd83dbSDimitry Andric bits <5> Rt32; 30895ffd83dbSDimitry Andric let Inst{12-8} = Rt32{4-0}; 30900b57cec5SDimitry Andric bits <5> Rx32; 30910b57cec5SDimitry Andric let Inst{20-16} = Rx32{4-0}; 30920b57cec5SDimitry Andric} 3093fe6060f1SDimitry Andricclass Enc_dbd70c : OpcodeHexagon { 3094fe6060f1SDimitry Andric bits <5> Rss32; 3095fe6060f1SDimitry Andric let Inst{20-16} = Rss32{4-0}; 3096fe6060f1SDimitry Andric bits <5> Rtt32; 3097fe6060f1SDimitry Andric let Inst{12-8} = Rtt32{4-0}; 3098fe6060f1SDimitry Andric bits <2> Pu4; 3099fe6060f1SDimitry Andric let Inst{6-5} = Pu4{1-0}; 3100fe6060f1SDimitry Andric bits <5> Rdd32; 3101fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 3102fe6060f1SDimitry Andric} 3103fe6060f1SDimitry Andricclass Enc_dd766a : OpcodeHexagon { 3104fe6060f1SDimitry Andric bits <5> Vu32; 3105fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 3106fe6060f1SDimitry Andric bits <5> Vdd32; 3107fe6060f1SDimitry Andric let Inst{4-0} = Vdd32{4-0}; 3108fe6060f1SDimitry Andric} 3109fe6060f1SDimitry Andricclass Enc_de0214 : OpcodeHexagon { 3110fe6060f1SDimitry Andric bits <12> Ii; 3111fe6060f1SDimitry Andric let Inst{26-25} = Ii{11-10}; 3112fe6060f1SDimitry Andric let Inst{13-5} = Ii{9-1}; 31130b57cec5SDimitry Andric bits <5> Rs32; 31140b57cec5SDimitry Andric let Inst{20-16} = Rs32{4-0}; 3115fe6060f1SDimitry Andric bits <5> Rd32; 3116fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 31170b57cec5SDimitry Andric} 31180eae32dcSDimitry Andricclass Enc_de5ea0 : OpcodeHexagon { 31190eae32dcSDimitry Andric bits <5> Vuu32; 31200eae32dcSDimitry Andric let Inst{12-8} = Vuu32{4-0}; 31210eae32dcSDimitry Andric bits <5> Vv32; 31220eae32dcSDimitry Andric let Inst{20-16} = Vv32{4-0}; 31230eae32dcSDimitry Andric bits <5> Vd32; 31240eae32dcSDimitry Andric let Inst{4-0} = Vd32{4-0}; 31250eae32dcSDimitry Andric} 3126fe6060f1SDimitry Andricclass Enc_e07374 : OpcodeHexagon { 3127fe6060f1SDimitry Andric bits <5> Rs32; 3128fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 3129fe6060f1SDimitry Andric bits <5> Rtt32; 3130fe6060f1SDimitry Andric let Inst{12-8} = Rtt32{4-0}; 3131fe6060f1SDimitry Andric bits <5> Rd32; 3132fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 3133fe6060f1SDimitry Andric} 3134fe6060f1SDimitry Andricclass Enc_e0820b : OpcodeHexagon { 3135fe6060f1SDimitry Andric bits <5> Vu32; 3136fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 3137fe6060f1SDimitry Andric bits <5> Vv32; 3138fe6060f1SDimitry Andric let Inst{20-16} = Vv32{4-0}; 3139fe6060f1SDimitry Andric bits <2> Qs4; 3140fe6060f1SDimitry Andric let Inst{6-5} = Qs4{1-0}; 3141fe6060f1SDimitry Andric bits <5> Vd32; 3142fe6060f1SDimitry Andric let Inst{4-0} = Vd32{4-0}; 3143fe6060f1SDimitry Andric} 3144fe6060f1SDimitry Andricclass Enc_e0a47a : OpcodeHexagon { 31455ffd83dbSDimitry Andric bits <4> Ii; 3146fe6060f1SDimitry Andric let Inst{8-5} = Ii{3-0}; 3147fe6060f1SDimitry Andric bits <1> Mu2; 3148fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 3149fe6060f1SDimitry Andric bits <5> Rd32; 3150fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 3151fe6060f1SDimitry Andric bits <5> Rx32; 3152fe6060f1SDimitry Andric let Inst{20-16} = Rx32{4-0}; 3153fe6060f1SDimitry Andric} 3154fe6060f1SDimitry Andricclass Enc_e26546 : OpcodeHexagon { 3155fe6060f1SDimitry Andric bits <5> Ii; 3156fe6060f1SDimitry Andric let Inst{6-3} = Ii{4-1}; 31575ffd83dbSDimitry Andric bits <3> Nt8; 31585ffd83dbSDimitry Andric let Inst{10-8} = Nt8{2-0}; 31595ffd83dbSDimitry Andric bits <5> Rx32; 31605ffd83dbSDimitry Andric let Inst{20-16} = Rx32{4-0}; 31615ffd83dbSDimitry Andric} 3162349cc55cSDimitry Andricclass Enc_e32517 : OpcodeHexagon { 3163349cc55cSDimitry Andric bits <7> Sss128; 3164349cc55cSDimitry Andric let Inst{22-16} = Sss128{6-0}; 3165349cc55cSDimitry Andric bits <5> Rdd32; 3166349cc55cSDimitry Andric let Inst{4-0} = Rdd32{4-0}; 3167349cc55cSDimitry Andric} 3168fe6060f1SDimitry Andricclass Enc_e38e1f : OpcodeHexagon { 3169fe6060f1SDimitry Andric bits <8> Ii; 3170fe6060f1SDimitry Andric let Inst{12-5} = Ii{7-0}; 3171fe6060f1SDimitry Andric bits <2> Pu4; 3172fe6060f1SDimitry Andric let Inst{22-21} = Pu4{1-0}; 3173fe6060f1SDimitry Andric bits <5> Rs32; 3174fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 3175fe6060f1SDimitry Andric bits <5> Rd32; 3176fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 3177fe6060f1SDimitry Andric} 3178fe6060f1SDimitry Andricclass Enc_e39bb2 : OpcodeHexagon { 3179fe6060f1SDimitry Andric bits <6> Ii; 3180fe6060f1SDimitry Andric let Inst{9-4} = Ii{5-0}; 3181fe6060f1SDimitry Andric bits <4> Rd16; 3182fe6060f1SDimitry Andric let Inst{3-0} = Rd16{3-0}; 3183fe6060f1SDimitry Andric} 3184fe6060f1SDimitry Andricclass Enc_e3b0c4 : OpcodeHexagon { 3185fe6060f1SDimitry Andric 3186fe6060f1SDimitry Andric} 3187fe6060f1SDimitry Andricclass Enc_e66a97 : OpcodeHexagon { 3188fe6060f1SDimitry Andric bits <7> Ii; 3189fe6060f1SDimitry Andric let Inst{12-7} = Ii{6-1}; 3190fe6060f1SDimitry Andric bits <5> II; 3191fe6060f1SDimitry Andric let Inst{4-0} = II{4-0}; 3192fe6060f1SDimitry Andric bits <5> Rs32; 3193fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 3194fe6060f1SDimitry Andric} 3195fe6060f1SDimitry Andricclass Enc_e6abcf : OpcodeHexagon { 31965ffd83dbSDimitry Andric bits <5> Rs32; 31975ffd83dbSDimitry Andric let Inst{20-16} = Rs32{4-0}; 31985ffd83dbSDimitry Andric bits <5> Rtt32; 31995ffd83dbSDimitry Andric let Inst{12-8} = Rtt32{4-0}; 32005ffd83dbSDimitry Andric} 3201fe6060f1SDimitry Andricclass Enc_e6c957 : OpcodeHexagon { 3202fe6060f1SDimitry Andric bits <10> Ii; 3203fe6060f1SDimitry Andric let Inst{21-21} = Ii{9-9}; 3204fe6060f1SDimitry Andric let Inst{13-5} = Ii{8-0}; 3205fe6060f1SDimitry Andric bits <5> Rdd32; 3206fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 3207fe6060f1SDimitry Andric} 3208fe6060f1SDimitry Andricclass Enc_e7581c : OpcodeHexagon { 3209fe6060f1SDimitry Andric bits <5> Vu32; 3210fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 3211fe6060f1SDimitry Andric bits <5> Vd32; 3212fe6060f1SDimitry Andric let Inst{4-0} = Vd32{4-0}; 3213fe6060f1SDimitry Andric} 3214fe6060f1SDimitry Andricclass Enc_e83554 : OpcodeHexagon { 3215fe6060f1SDimitry Andric bits <5> Ii; 3216fe6060f1SDimitry Andric let Inst{8-5} = Ii{4-1}; 3217fe6060f1SDimitry Andric bits <1> Mu2; 3218fe6060f1SDimitry Andric let Inst{13-13} = Mu2{0-0}; 3219fe6060f1SDimitry Andric bits <5> Rd32; 3220fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 32215ffd83dbSDimitry Andric bits <5> Rx32; 32225ffd83dbSDimitry Andric let Inst{20-16} = Rx32{4-0}; 32235ffd83dbSDimitry Andric} 32245ffd83dbSDimitry Andricclass Enc_e8c45e : OpcodeHexagon { 32255ffd83dbSDimitry Andric bits <7> Ii; 32265ffd83dbSDimitry Andric let Inst{13-13} = Ii{6-6}; 32275ffd83dbSDimitry Andric let Inst{7-3} = Ii{5-1}; 32285ffd83dbSDimitry Andric bits <2> Pv4; 32295ffd83dbSDimitry Andric let Inst{1-0} = Pv4{1-0}; 32300b57cec5SDimitry Andric bits <5> Rs32; 32310b57cec5SDimitry Andric let Inst{20-16} = Rs32{4-0}; 32320b57cec5SDimitry Andric bits <5> Rt32; 32335ffd83dbSDimitry Andric let Inst{12-8} = Rt32{4-0}; 32345ffd83dbSDimitry Andric} 3235fe6060f1SDimitry Andricclass Enc_e90a15 : OpcodeHexagon { 32360b57cec5SDimitry Andric bits <11> Ii; 3237fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 3238fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 3239fe6060f1SDimitry Andric bits <3> Ns8; 3240fe6060f1SDimitry Andric let Inst{18-16} = Ns8{2-0}; 3241fe6060f1SDimitry Andric bits <4> n1; 3242fe6060f1SDimitry Andric let Inst{29-29} = n1{3-3}; 3243fe6060f1SDimitry Andric let Inst{26-25} = n1{2-1}; 3244fe6060f1SDimitry Andric let Inst{22-22} = n1{0-0}; 32450b57cec5SDimitry Andric} 32460b57cec5SDimitry Andricclass Enc_e957fb : OpcodeHexagon { 32470b57cec5SDimitry Andric bits <12> Ii; 32480b57cec5SDimitry Andric let Inst{26-25} = Ii{11-10}; 32490b57cec5SDimitry Andric let Inst{13-13} = Ii{9-9}; 32500b57cec5SDimitry Andric let Inst{7-0} = Ii{8-1}; 32510b57cec5SDimitry Andric bits <5> Rs32; 32520b57cec5SDimitry Andric let Inst{20-16} = Rs32{4-0}; 32530b57cec5SDimitry Andric bits <5> Rt32; 32540b57cec5SDimitry Andric let Inst{12-8} = Rt32{4-0}; 32550b57cec5SDimitry Andric} 3256fe6060f1SDimitry Andricclass Enc_ea23e4 : OpcodeHexagon { 32575ffd83dbSDimitry Andric bits <5> Rtt32; 32585ffd83dbSDimitry Andric let Inst{12-8} = Rtt32{4-0}; 32595ffd83dbSDimitry Andric bits <5> Rss32; 32605ffd83dbSDimitry Andric let Inst{20-16} = Rss32{4-0}; 32615ffd83dbSDimitry Andric bits <5> Rdd32; 32625ffd83dbSDimitry Andric let Inst{4-0} = Rdd32{4-0}; 32635ffd83dbSDimitry Andric} 3264fe6060f1SDimitry Andricclass Enc_ea4c54 : OpcodeHexagon { 32655ffd83dbSDimitry Andric bits <2> Pu4; 32665ffd83dbSDimitry Andric let Inst{6-5} = Pu4{1-0}; 32675ffd83dbSDimitry Andric bits <5> Rs32; 32685ffd83dbSDimitry Andric let Inst{20-16} = Rs32{4-0}; 3269fe6060f1SDimitry Andric bits <5> Rt32; 3270fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 32715ffd83dbSDimitry Andric bits <5> Rd32; 3272fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 32735ffd83dbSDimitry Andric} 3274fe6060f1SDimitry Andricclass Enc_eaa9f8 : OpcodeHexagon { 3275fe6060f1SDimitry Andric bits <5> Vu32; 3276fe6060f1SDimitry Andric let Inst{12-8} = Vu32{4-0}; 3277fe6060f1SDimitry Andric bits <5> Vv32; 3278fe6060f1SDimitry Andric let Inst{20-16} = Vv32{4-0}; 3279fe6060f1SDimitry Andric bits <2> Qx4; 3280fe6060f1SDimitry Andric let Inst{1-0} = Qx4{1-0}; 3281fe6060f1SDimitry Andric} 3282fe6060f1SDimitry Andricclass Enc_eafd18 : OpcodeHexagon { 32835ffd83dbSDimitry Andric bits <5> II; 32845ffd83dbSDimitry Andric let Inst{12-8} = II{4-0}; 3285fe6060f1SDimitry Andric bits <11> Ii; 3286fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 3287fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 3288fe6060f1SDimitry Andric bits <3> Ns8; 3289fe6060f1SDimitry Andric let Inst{18-16} = Ns8{2-0}; 32905ffd83dbSDimitry Andric} 3291fe6060f1SDimitry Andricclass Enc_eca7c8 : OpcodeHexagon { 32920b57cec5SDimitry Andric bits <2> Ii; 32930b57cec5SDimitry Andric let Inst{13-13} = Ii{1-1}; 32940b57cec5SDimitry Andric let Inst{7-7} = Ii{0-0}; 32950b57cec5SDimitry Andric bits <5> Rs32; 32960b57cec5SDimitry Andric let Inst{20-16} = Rs32{4-0}; 32970b57cec5SDimitry Andric bits <5> Ru32; 32980b57cec5SDimitry Andric let Inst{12-8} = Ru32{4-0}; 32990b57cec5SDimitry Andric bits <5> Rt32; 33000b57cec5SDimitry Andric let Inst{4-0} = Rt32{4-0}; 33010b57cec5SDimitry Andric} 3302fe6060f1SDimitry Andricclass Enc_ecbcc8 : OpcodeHexagon { 3303fe6060f1SDimitry Andric bits <5> Rs32; 3304fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 33050b57cec5SDimitry Andric} 3306fe6060f1SDimitry Andricclass Enc_ed48be : OpcodeHexagon { 33070b57cec5SDimitry Andric bits <2> Ii; 3308fe6060f1SDimitry Andric let Inst{6-5} = Ii{1-0}; 3309fe6060f1SDimitry Andric bits <3> Rdd8; 3310fe6060f1SDimitry Andric let Inst{2-0} = Rdd8{2-0}; 3311fe6060f1SDimitry Andric} 3312fe6060f1SDimitry Andricclass Enc_ed5027 : OpcodeHexagon { 3313fe6060f1SDimitry Andric bits <5> Rss32; 3314fe6060f1SDimitry Andric let Inst{20-16} = Rss32{4-0}; 3315fe6060f1SDimitry Andric bits <5> Gdd32; 3316fe6060f1SDimitry Andric let Inst{4-0} = Gdd32{4-0}; 3317fe6060f1SDimitry Andric} 3318fe6060f1SDimitry Andricclass Enc_ee5ed0 : OpcodeHexagon { 3319fe6060f1SDimitry Andric bits <4> Rs16; 3320fe6060f1SDimitry Andric let Inst{7-4} = Rs16{3-0}; 3321fe6060f1SDimitry Andric bits <4> Rd16; 3322fe6060f1SDimitry Andric let Inst{3-0} = Rd16{3-0}; 3323fe6060f1SDimitry Andric bits <2> n1; 3324fe6060f1SDimitry Andric let Inst{9-8} = n1{1-0}; 3325fe6060f1SDimitry Andric} 3326fe6060f1SDimitry Andricclass Enc_ef601b : OpcodeHexagon { 3327fe6060f1SDimitry Andric bits <4> Ii; 3328fe6060f1SDimitry Andric let Inst{13-13} = Ii{3-3}; 3329fe6060f1SDimitry Andric let Inst{10-8} = Ii{2-0}; 33300b57cec5SDimitry Andric bits <2> Pv4; 3331fe6060f1SDimitry Andric let Inst{12-11} = Pv4{1-0}; 3332fe6060f1SDimitry Andric bits <5> Rt32; 3333fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 33340b57cec5SDimitry Andric} 3335fe6060f1SDimitry Andricclass Enc_efaed8 : OpcodeHexagon { 3336fe6060f1SDimitry Andric bits <1> Ii; 3337fe6060f1SDimitry Andric let Inst{8-8} = Ii{0-0}; 33380b57cec5SDimitry Andric} 3339fe6060f1SDimitry Andricclass Enc_f0cca7 : OpcodeHexagon { 3340fe6060f1SDimitry Andric bits <8> Ii; 3341fe6060f1SDimitry Andric let Inst{12-5} = Ii{7-0}; 33425ffd83dbSDimitry Andric bits <6> II; 3343fe6060f1SDimitry Andric let Inst{20-16} = II{5-1}; 3344fe6060f1SDimitry Andric let Inst{13-13} = II{0-0}; 3345fe6060f1SDimitry Andric bits <5> Rdd32; 3346fe6060f1SDimitry Andric let Inst{4-0} = Rdd32{4-0}; 33470b57cec5SDimitry Andric} 33480b57cec5SDimitry Andricclass Enc_f20719 : OpcodeHexagon { 33490b57cec5SDimitry Andric bits <7> Ii; 33500b57cec5SDimitry Andric let Inst{12-7} = Ii{6-1}; 33510b57cec5SDimitry Andric bits <6> II; 33520b57cec5SDimitry Andric let Inst{13-13} = II{5-5}; 33530b57cec5SDimitry Andric let Inst{4-0} = II{4-0}; 33540b57cec5SDimitry Andric bits <2> Pv4; 33550b57cec5SDimitry Andric let Inst{6-5} = Pv4{1-0}; 33560b57cec5SDimitry Andric bits <5> Rs32; 33570b57cec5SDimitry Andric let Inst{20-16} = Rs32{4-0}; 33580b57cec5SDimitry Andric} 33595ffd83dbSDimitry Andricclass Enc_f37377 : OpcodeHexagon { 33605ffd83dbSDimitry Andric bits <8> Ii; 33615ffd83dbSDimitry Andric let Inst{12-7} = Ii{7-2}; 33625ffd83dbSDimitry Andric bits <8> II; 33635ffd83dbSDimitry Andric let Inst{13-13} = II{7-7}; 33645ffd83dbSDimitry Andric let Inst{6-0} = II{6-0}; 33650b57cec5SDimitry Andric bits <5> Rs32; 33660b57cec5SDimitry Andric let Inst{20-16} = Rs32{4-0}; 33670b57cec5SDimitry Andric} 3368fe6060f1SDimitry Andricclass Enc_f394d3 : OpcodeHexagon { 33690b57cec5SDimitry Andric bits <6> II; 3370fe6060f1SDimitry Andric let Inst{11-8} = II{5-2}; 3371fe6060f1SDimitry Andric let Inst{6-5} = II{1-0}; 3372fe6060f1SDimitry Andric bits <5> Ryy32; 3373fe6060f1SDimitry Andric let Inst{4-0} = Ryy32{4-0}; 33745ffd83dbSDimitry Andric bits <5> Re32; 33755ffd83dbSDimitry Andric let Inst{20-16} = Re32{4-0}; 33760b57cec5SDimitry Andric} 33775ffd83dbSDimitry Andricclass Enc_f3f408 : OpcodeHexagon { 33785ffd83dbSDimitry Andric bits <4> Ii; 33795ffd83dbSDimitry Andric let Inst{13-13} = Ii{3-3}; 33805ffd83dbSDimitry Andric let Inst{10-8} = Ii{2-0}; 33815ffd83dbSDimitry Andric bits <5> Rt32; 33825ffd83dbSDimitry Andric let Inst{20-16} = Rt32{4-0}; 33835ffd83dbSDimitry Andric bits <5> Vd32; 33845ffd83dbSDimitry Andric let Inst{4-0} = Vd32{4-0}; 33855ffd83dbSDimitry Andric} 3386fe6060f1SDimitry Andricclass Enc_f4413a : OpcodeHexagon { 33875ffd83dbSDimitry Andric bits <4> Ii; 3388fe6060f1SDimitry Andric let Inst{8-5} = Ii{3-0}; 3389fe6060f1SDimitry Andric bits <2> Pt4; 3390fe6060f1SDimitry Andric let Inst{10-9} = Pt4{1-0}; 3391fe6060f1SDimitry Andric bits <5> Rd32; 3392fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 33935ffd83dbSDimitry Andric bits <5> Rx32; 33945ffd83dbSDimitry Andric let Inst{20-16} = Rx32{4-0}; 33955ffd83dbSDimitry Andric} 3396fe6060f1SDimitry Andricclass Enc_f44229 : OpcodeHexagon { 3397fe6060f1SDimitry Andric bits <7> Ii; 3398fe6060f1SDimitry Andric let Inst{13-13} = Ii{6-6}; 3399fe6060f1SDimitry Andric let Inst{7-3} = Ii{5-1}; 34005ffd83dbSDimitry Andric bits <2> Pv4; 3401fe6060f1SDimitry Andric let Inst{1-0} = Pv4{1-0}; 3402fe6060f1SDimitry Andric bits <5> Rs32; 3403fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 3404fe6060f1SDimitry Andric bits <3> Nt8; 3405fe6060f1SDimitry Andric let Inst{10-8} = Nt8{2-0}; 34065ffd83dbSDimitry Andric} 3407fe6060f1SDimitry Andricclass Enc_f4f57b : OpcodeHexagon { 3408fe6060f1SDimitry Andric bits <2> Ii; 3409fe6060f1SDimitry Andric let Inst{6-5} = Ii{1-0}; 3410fe6060f1SDimitry Andric bits <5> Vuu32; 3411fe6060f1SDimitry Andric let Inst{12-8} = Vuu32{4-0}; 3412fe6060f1SDimitry Andric bits <5> Vvv32; 3413fe6060f1SDimitry Andric let Inst{20-16} = Vvv32{4-0}; 3414fe6060f1SDimitry Andric bits <5> Vxx32; 3415fe6060f1SDimitry Andric let Inst{4-0} = Vxx32{4-0}; 34165ffd83dbSDimitry Andric} 3417fe6060f1SDimitry Andricclass Enc_f55a0c : OpcodeHexagon { 3418fe6060f1SDimitry Andric bits <6> Ii; 3419fe6060f1SDimitry Andric let Inst{11-8} = Ii{5-2}; 3420fe6060f1SDimitry Andric bits <4> Rs16; 3421fe6060f1SDimitry Andric let Inst{7-4} = Rs16{3-0}; 3422fe6060f1SDimitry Andric bits <4> Rt16; 3423fe6060f1SDimitry Andric let Inst{3-0} = Rt16{3-0}; 34245ffd83dbSDimitry Andric} 3425fe6060f1SDimitry Andricclass Enc_f5e933 : OpcodeHexagon { 3426fe6060f1SDimitry Andric bits <2> Ps4; 3427fe6060f1SDimitry Andric let Inst{17-16} = Ps4{1-0}; 3428fe6060f1SDimitry Andric bits <5> Rd32; 3429fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 34305ffd83dbSDimitry Andric} 3431fe6060f1SDimitry Andricclass Enc_f6fe0b : OpcodeHexagon { 3432fe6060f1SDimitry Andric bits <11> Ii; 3433fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 3434fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 3435fe6060f1SDimitry Andric bits <4> Rs16; 3436fe6060f1SDimitry Andric let Inst{19-16} = Rs16{3-0}; 3437fe6060f1SDimitry Andric bits <6> n1; 3438fe6060f1SDimitry Andric let Inst{28-28} = n1{5-5}; 3439fe6060f1SDimitry Andric let Inst{24-22} = n1{4-2}; 3440fe6060f1SDimitry Andric let Inst{13-13} = n1{1-1}; 3441fe6060f1SDimitry Andric let Inst{8-8} = n1{0-0}; 34425ffd83dbSDimitry Andric} 34435ffd83dbSDimitry Andricclass Enc_f7430e : OpcodeHexagon { 34445ffd83dbSDimitry Andric bits <4> Ii; 34455ffd83dbSDimitry Andric let Inst{13-13} = Ii{3-3}; 34465ffd83dbSDimitry Andric let Inst{10-8} = Ii{2-0}; 34475ffd83dbSDimitry Andric bits <2> Pv4; 34485ffd83dbSDimitry Andric let Inst{12-11} = Pv4{1-0}; 34495ffd83dbSDimitry Andric bits <5> Rt32; 34505ffd83dbSDimitry Andric let Inst{20-16} = Rt32{4-0}; 34515ffd83dbSDimitry Andric bits <3> Os8; 34525ffd83dbSDimitry Andric let Inst{2-0} = Os8{2-0}; 34535ffd83dbSDimitry Andric} 3454fe6060f1SDimitry Andricclass Enc_f77fbc : OpcodeHexagon { 34555ffd83dbSDimitry Andric bits <4> Ii; 34565ffd83dbSDimitry Andric let Inst{13-13} = Ii{3-3}; 34575ffd83dbSDimitry Andric let Inst{10-8} = Ii{2-0}; 34585ffd83dbSDimitry Andric bits <5> Rt32; 34595ffd83dbSDimitry Andric let Inst{20-16} = Rt32{4-0}; 3460fe6060f1SDimitry Andric bits <3> Os8; 3461fe6060f1SDimitry Andric let Inst{2-0} = Os8{2-0}; 34625ffd83dbSDimitry Andric} 3463fe6060f1SDimitry Andricclass Enc_f79415 : OpcodeHexagon { 3464fe6060f1SDimitry Andric bits <2> Ii; 3465fe6060f1SDimitry Andric let Inst{13-13} = Ii{1-1}; 3466fe6060f1SDimitry Andric let Inst{6-6} = Ii{0-0}; 3467fe6060f1SDimitry Andric bits <6> II; 3468fe6060f1SDimitry Andric let Inst{5-0} = II{5-0}; 3469fe6060f1SDimitry Andric bits <5> Ru32; 3470fe6060f1SDimitry Andric let Inst{20-16} = Ru32{4-0}; 3471fe6060f1SDimitry Andric bits <5> Rtt32; 3472fe6060f1SDimitry Andric let Inst{12-8} = Rtt32{4-0}; 34735ffd83dbSDimitry Andric} 3474fe6060f1SDimitry Andricclass Enc_f7ea77 : OpcodeHexagon { 3475fe6060f1SDimitry Andric bits <11> Ii; 3476fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 3477fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 3478fe6060f1SDimitry Andric bits <3> Ns8; 3479fe6060f1SDimitry Andric let Inst{18-16} = Ns8{2-0}; 3480fe6060f1SDimitry Andric bits <4> n1; 3481fe6060f1SDimitry Andric let Inst{29-29} = n1{3-3}; 3482fe6060f1SDimitry Andric let Inst{26-25} = n1{2-1}; 3483fe6060f1SDimitry Andric let Inst{13-13} = n1{0-0}; 3484fe6060f1SDimitry Andric} 3485fe6060f1SDimitry Andricclass Enc_f82302 : OpcodeHexagon { 3486fe6060f1SDimitry Andric bits <11> Ii; 3487fe6060f1SDimitry Andric let Inst{21-20} = Ii{10-9}; 3488fe6060f1SDimitry Andric let Inst{7-1} = Ii{8-2}; 3489fe6060f1SDimitry Andric bits <3> Ns8; 3490fe6060f1SDimitry Andric let Inst{18-16} = Ns8{2-0}; 3491fe6060f1SDimitry Andric bits <4> n1; 3492fe6060f1SDimitry Andric let Inst{29-29} = n1{3-3}; 3493fe6060f1SDimitry Andric let Inst{26-25} = n1{2-1}; 3494fe6060f1SDimitry Andric let Inst{23-23} = n1{0-0}; 3495fe6060f1SDimitry Andric} 3496fe6060f1SDimitry Andricclass Enc_f82eaf : OpcodeHexagon { 3497fe6060f1SDimitry Andric bits <8> Ii; 3498fe6060f1SDimitry Andric let Inst{10-5} = Ii{7-2}; 3499fe6060f1SDimitry Andric bits <2> Pt4; 3500fe6060f1SDimitry Andric let Inst{12-11} = Pt4{1-0}; 3501fe6060f1SDimitry Andric bits <5> Rs32; 3502fe6060f1SDimitry Andric let Inst{20-16} = Rs32{4-0}; 3503fe6060f1SDimitry Andric bits <5> Rd32; 3504fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 3505fe6060f1SDimitry Andric} 3506fe6060f1SDimitry Andricclass Enc_f8c1c4 : OpcodeHexagon { 3507fe6060f1SDimitry Andric bits <2> Pv4; 3508fe6060f1SDimitry Andric let Inst{12-11} = Pv4{1-0}; 35095ffd83dbSDimitry Andric bits <1> Mu2; 35105ffd83dbSDimitry Andric let Inst{13-13} = Mu2{0-0}; 3511fe6060f1SDimitry Andric bits <5> Vd32; 3512fe6060f1SDimitry Andric let Inst{4-0} = Vd32{4-0}; 35135ffd83dbSDimitry Andric bits <5> Rx32; 35145ffd83dbSDimitry Andric let Inst{20-16} = Rx32{4-0}; 35155ffd83dbSDimitry Andric} 35165ffd83dbSDimitry Andricclass Enc_f8ecf9 : OpcodeHexagon { 35175ffd83dbSDimitry Andric bits <5> Vuu32; 35185ffd83dbSDimitry Andric let Inst{12-8} = Vuu32{4-0}; 35195ffd83dbSDimitry Andric bits <5> Vvv32; 35205ffd83dbSDimitry Andric let Inst{20-16} = Vvv32{4-0}; 35215ffd83dbSDimitry Andric bits <5> Vdd32; 35225ffd83dbSDimitry Andric let Inst{4-0} = Vdd32{4-0}; 35235ffd83dbSDimitry Andric} 3524fe6060f1SDimitry Andricclass Enc_fa3ba4 : OpcodeHexagon { 35255ffd83dbSDimitry Andric bits <14> Ii; 3526fe6060f1SDimitry Andric let Inst{26-25} = Ii{13-12}; 3527fe6060f1SDimitry Andric let Inst{13-5} = Ii{11-3}; 35285ffd83dbSDimitry Andric bits <5> Rs32; 35295ffd83dbSDimitry Andric let Inst{20-16} = Rs32{4-0}; 35305ffd83dbSDimitry Andric bits <5> Rdd32; 35315ffd83dbSDimitry Andric let Inst{4-0} = Rdd32{4-0}; 35325ffd83dbSDimitry Andric} 3533fe6060f1SDimitry Andricclass Enc_fb6577 : OpcodeHexagon { 3534fe6060f1SDimitry Andric bits <2> Pu4; 3535fe6060f1SDimitry Andric let Inst{9-8} = Pu4{1-0}; 35365ffd83dbSDimitry Andric bits <5> Rs32; 35375ffd83dbSDimitry Andric let Inst{20-16} = Rs32{4-0}; 3538fe6060f1SDimitry Andric bits <5> Rd32; 3539fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 35405ffd83dbSDimitry Andric} 3541fe6060f1SDimitry Andricclass Enc_fcf7a7 : OpcodeHexagon { 35425ffd83dbSDimitry Andric bits <5> Rss32; 35435ffd83dbSDimitry Andric let Inst{20-16} = Rss32{4-0}; 35445ffd83dbSDimitry Andric bits <5> Rtt32; 35455ffd83dbSDimitry Andric let Inst{12-8} = Rtt32{4-0}; 3546fe6060f1SDimitry Andric bits <2> Pd4; 3547fe6060f1SDimitry Andric let Inst{1-0} = Pd4{1-0}; 35485ffd83dbSDimitry Andric} 3549fe6060f1SDimitry Andricclass Enc_fda92c : OpcodeHexagon { 3550fe6060f1SDimitry Andric bits <17> Ii; 3551fe6060f1SDimitry Andric let Inst{26-25} = Ii{16-15}; 3552fe6060f1SDimitry Andric let Inst{20-16} = Ii{14-10}; 3553fe6060f1SDimitry Andric let Inst{13-13} = Ii{9-9}; 3554fe6060f1SDimitry Andric let Inst{7-0} = Ii{8-1}; 3555fe6060f1SDimitry Andric bits <5> Rt32; 3556fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 3557fe6060f1SDimitry Andric} 3558fe6060f1SDimitry Andricclass Enc_fef969 : OpcodeHexagon { 3559fe6060f1SDimitry Andric bits <6> Ii; 3560fe6060f1SDimitry Andric let Inst{20-16} = Ii{5-1}; 3561fe6060f1SDimitry Andric let Inst{5-5} = Ii{0-0}; 3562fe6060f1SDimitry Andric bits <5> Rt32; 3563fe6060f1SDimitry Andric let Inst{12-8} = Rt32{4-0}; 3564fe6060f1SDimitry Andric bits <5> Rd32; 3565fe6060f1SDimitry Andric let Inst{4-0} = Rd32{4-0}; 3566fe6060f1SDimitry Andric} 3567fe6060f1SDimitry Andricclass Enc_ff3442 : OpcodeHexagon { 3568fe6060f1SDimitry Andric bits <4> Ii; 3569fe6060f1SDimitry Andric let Inst{13-13} = Ii{3-3}; 3570fe6060f1SDimitry Andric let Inst{10-8} = Ii{2-0}; 3571fe6060f1SDimitry Andric bits <5> Rt32; 3572fe6060f1SDimitry Andric let Inst{20-16} = Rt32{4-0}; 35735ffd83dbSDimitry Andric} 3574