1 //===-- HexagonISelDAGToDAG.h -----------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // Hexagon specific code to select Hexagon machine instructions for 9 // SelectionDAG operations. 10 //===----------------------------------------------------------------------===// 11 12 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H 13 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H 14 15 #include "HexagonSubtarget.h" 16 #include "HexagonTargetMachine.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/CodeGen/SelectionDAG.h" 19 #include "llvm/CodeGen/SelectionDAGISel.h" 20 #include "llvm/Support/CodeGen.h" 21 22 #include <vector> 23 24 namespace llvm { 25 class MachineFunction; 26 class HexagonInstrInfo; 27 class HexagonRegisterInfo; 28 29 class HexagonDAGToDAGISel : public SelectionDAGISel { 30 const HexagonSubtarget *HST; 31 const HexagonInstrInfo *HII; 32 const HexagonRegisterInfo *HRI; 33 public: 34 static char ID; 35 36 HexagonDAGToDAGISel() = delete; 37 38 explicit HexagonDAGToDAGISel(HexagonTargetMachine &tm, 39 CodeGenOpt::Level OptLevel) 40 : SelectionDAGISel(ID, tm, OptLevel), HST(nullptr), HII(nullptr), 41 HRI(nullptr) {} 42 43 bool runOnMachineFunction(MachineFunction &MF) override { 44 // Reset the subtarget each time through. 45 HST = &MF.getSubtarget<HexagonSubtarget>(); 46 HII = HST->getInstrInfo(); 47 HRI = HST->getRegisterInfo(); 48 SelectionDAGISel::runOnMachineFunction(MF); 49 updateAligna(); 50 return true; 51 } 52 53 bool ComplexPatternFuncMutatesDAG() const override { 54 return true; 55 } 56 void PreprocessISelDAG() override; 57 void emitFunctionEntryCode() override; 58 59 void Select(SDNode *N) override; 60 61 // Complex Pattern Selectors. 62 inline bool SelectAddrGA(SDValue &N, SDValue &R); 63 inline bool SelectAddrGP(SDValue &N, SDValue &R); 64 inline bool SelectAnyImm(SDValue &N, SDValue &R); 65 inline bool SelectAnyInt(SDValue &N, SDValue &R); 66 bool SelectAnyImmediate(SDValue &N, SDValue &R, Align Alignment); 67 bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP, Align Alignment); 68 bool SelectAddrFI(SDValue &N, SDValue &R); 69 bool DetectUseSxtw(SDValue &N, SDValue &R); 70 71 inline bool SelectAnyImm0(SDValue &N, SDValue &R); 72 inline bool SelectAnyImm1(SDValue &N, SDValue &R); 73 inline bool SelectAnyImm2(SDValue &N, SDValue &R); 74 inline bool SelectAnyImm3(SDValue &N, SDValue &R); 75 76 // Generate a machine instruction node corresponding to the circ/brev 77 // load intrinsic. 78 MachineSDNode *LoadInstrForLoadIntrinsic(SDNode *IntN); 79 // Given the circ/brev load intrinsic and the already generated machine 80 // instruction, generate the appropriate store (that is a part of the 81 // intrinsic's functionality). 82 SDNode *StoreInstrForLoadIntrinsic(MachineSDNode *LoadN, SDNode *IntN); 83 84 void SelectFrameIndex(SDNode *N); 85 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for 86 /// inline asm expressions. 87 bool SelectInlineAsmMemoryOperand(const SDValue &Op, 88 unsigned ConstraintID, 89 std::vector<SDValue> &OutOps) override; 90 bool tryLoadOfLoadIntrinsic(LoadSDNode *N); 91 bool SelectBrevLdIntrinsic(SDNode *IntN); 92 bool SelectNewCircIntrinsic(SDNode *IntN); 93 void SelectLoad(SDNode *N); 94 void SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl); 95 void SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl); 96 void SelectStore(SDNode *N); 97 void SelectSHL(SDNode *N); 98 void SelectIntrinsicWChain(SDNode *N); 99 void SelectIntrinsicWOChain(SDNode *N); 100 void SelectExtractSubvector(SDNode *N); 101 void SelectConstant(SDNode *N); 102 void SelectConstantFP(SDNode *N); 103 void SelectV65Gather(SDNode *N); 104 void SelectV65GatherPred(SDNode *N); 105 void SelectHVXDualOutput(SDNode *N); 106 void SelectAddSubCarry(SDNode *N); 107 void SelectVAlign(SDNode *N); 108 void SelectVAlignAddr(SDNode *N); 109 void SelectTypecast(SDNode *N); 110 void SelectP2D(SDNode *N); 111 void SelectD2P(SDNode *N); 112 void SelectQ2V(SDNode *N); 113 void SelectV2Q(SDNode *N); 114 115 // Include the declarations autogenerated from the selection patterns. 116 #define GET_DAGISEL_DECL 117 #include "HexagonGenDAGISel.inc" 118 119 private: 120 // This is really only to get access to ReplaceNode (which is a protected 121 // member). Any other members used by HvxSelector can be moved around to 122 // make them accessible). 123 friend struct HvxSelector; 124 125 SDValue selectUndef(const SDLoc &dl, MVT ResTy) { 126 SDNode *U = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy); 127 return SDValue(U, 0); 128 } 129 130 bool keepsLowBits(const SDValue &Val, unsigned NumBits, SDValue &Src); 131 bool isAlignedMemNode(const MemSDNode *N) const; 132 bool isSmallStackStore(const StoreSDNode *N) const; 133 bool isPositiveHalfWord(const SDNode *N) const; 134 bool hasOneUse(const SDNode *N) const; 135 136 // DAG preprocessing functions. 137 void PreprocessHvxISelDAG(); 138 void ppSimplifyOrSelect0(std::vector<SDNode*> &&Nodes); 139 void ppAddrReorderAddShl(std::vector<SDNode*> &&Nodes); 140 void ppAddrRewriteAndSrl(std::vector<SDNode*> &&Nodes); 141 void ppHoistZextI1(std::vector<SDNode*> &&Nodes); 142 void ppHvxShuffleOfShuffle(std::vector<SDNode*> &&Nodes); 143 144 void SelectHvxExtractSubvector(SDNode *N); 145 void SelectHvxShuffle(SDNode *N); 146 void SelectHvxRor(SDNode *N); 147 void SelectHvxVAlign(SDNode *N); 148 149 // Function postprocessing. 150 void updateAligna(); 151 152 SmallDenseMap<SDNode *,int> RootWeights; 153 SmallDenseMap<SDNode *,int> RootHeights; 154 SmallDenseMap<const Value *,int> GAUsesInFunction; 155 int getWeight(SDNode *N); 156 int getHeight(SDNode *N); 157 SDValue getMultiplierForSHL(SDNode *N); 158 SDValue factorOutPowerOf2(SDValue V, unsigned Power); 159 unsigned getUsesInFunction(const Value *V); 160 SDValue balanceSubTree(SDNode *N, bool Factorize = false); 161 void rebalanceAddressTrees(); 162 }; // end HexagonDAGToDAGISel 163 } 164 165 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H 166