1//===-- HexagonRegisterInfo.td - Hexagon Register defs -----*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Declarations that describe the Hexagon register file. 11//===----------------------------------------------------------------------===// 12 13let Namespace = "Hexagon" in { 14 15 class HexagonReg<bits<5> num, string n, list<string> alt = [], 16 list<Register> alias = []> : Register<n, alt> { 17 let Aliases = alias; 18 let HWEncoding{4-0} = num; 19 } 20 21 // These registers are used to preserve a distinction between 22 // vector register pairs of differing order. 23 class HexagonFakeReg<string n> : Register<n> { 24 let isArtificial = 1; 25 } 26 27 class HexagonDoubleReg<bits<5> num, string n, list<Register> subregs, 28 list<string> alt = []> : 29 RegisterWithSubRegs<n, subregs> { 30 let AltNames = alt; 31 let HWEncoding{4-0} = num; 32 } 33 34 class HexagonSys<bits<7> num, string n, list<string> alt = [], 35 list<Register> alias = []> : Register<n, alt> { 36 let Aliases = alias; 37 let HWEncoding{6-0} = num; 38 } 39 40 class HexagonDoubleSys<bits<7> num, string n, list<Register> subregs, 41 list<string> alt = []> : 42 RegisterWithSubRegs<n, subregs> { 43 let AltNames = alt; 44 let HWEncoding{6-0} = num; 45 } 46 47 // Registers are identified with 5-bit ID numbers. 48 // Ri - 32-bit integer registers. 49 class Ri<bits<5> num, string n, list<string> alt = []> : 50 HexagonReg<num, n, alt>; 51 52 // Rp - false/pseudo registers. These registers are used 53 // to provide a distinct set of aliases for both styles of vector 54 // register pairs without encountering subregister indexing constraints. 55 class R_fake<string n> : 56 HexagonFakeReg<n>; 57 58 59 // Rf - 32-bit floating-point registers. 60 class Rf<bits<5> num, string n> : HexagonReg<num, n>; 61 62 // Rd - 64-bit registers. 63 class Rd<bits<5> num, string n, list<Register> subregs, 64 list<string> alt = []> : 65 HexagonDoubleReg<num, n, subregs, alt> { 66 let SubRegs = subregs; 67 } 68 69 // Rp - predicate registers 70 class Rp<bits<5> num, string n> : HexagonReg<num, n>; 71 72 73 // Rq - vector predicate registers 74 class Rq<bits<3> num, string n> : Register<n, []> { 75 let HWEncoding{2-0} = num; 76 } 77 78 // Rc - control registers 79 class Rc<bits<5> num, string n, 80 list<string> alt = [], list<Register> alias = []> : 81 HexagonReg<num, n, alt, alias>; 82 83 // Rcc - 64-bit control registers. 84 class Rcc<bits<5> num, string n, list<Register> subregs, 85 list<string> alt = []> : 86 HexagonDoubleReg<num, n, subregs, alt> { 87 let SubRegs = subregs; 88 } 89 90 // Rs - system registers 91 class Rs<bits<7> num, string n, 92 list<string> alt = [], list<Register> alias = []> : 93 HexagonSys<num, n, alt, alias>; 94 95 // Rss - 64-bit system registers. 96 class Rss<bits<7> num, string n, list<Register> subregs, 97 list<string> alt = []> : 98 HexagonDoubleSys<num, n, subregs, alt> { 99 let SubRegs = subregs; 100 } 101 102 // Mx - address modifier registers 103 class Mx<bits<1> num, string n> : Register<n, []> { 104 let HWEncoding{0} = num; 105 } 106 107 // Rg - Guest/Hypervisor registers 108 class Rg<bits<5> num, string n, 109 list<string> alt = [], list<Register> alias = []> : 110 HexagonReg<num, n, alt, alias>; 111 112 // Rgg - 64-bit Guest/Hypervisor registers 113 class Rgg<bits<5> num, string n, list<Register> subregs> : 114 HexagonDoubleReg<num, n, subregs> { 115 let SubRegs = subregs; 116 } 117 118 def isub_lo : SubRegIndex<32>; 119 def isub_hi : SubRegIndex<32, 32>; 120 def vsub_lo : SubRegIndex<-1, -1>; 121 def vsub_hi : SubRegIndex<-1, -1>; 122 def vsub_fake: SubRegIndex<-1, -1>; 123 def wsub_lo : SubRegIndex<-1, -1>; 124 def wsub_hi : SubRegIndex<-1, -1>; 125 def subreg_overflow : SubRegIndex<1, 0>; 126 127 // Integer registers. 128 foreach i = 0-28 in { 129 def R#i : Ri<i, "r"#i>, DwarfRegNum<[i]>; 130 } 131 def R29 : Ri<29, "r29", ["sp"]>, DwarfRegNum<[29]>; 132 def R30 : Ri<30, "r30", ["fp"]>, DwarfRegNum<[30]>; 133 def R31 : Ri<31, "r31", ["lr"]>, DwarfRegNum<[31]>; 134 135 // Aliases of the R* registers used to hold 64-bit int values (doubles). 136 let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in { 137 def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>; 138 def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>; 139 def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>; 140 def D3 : Rd< 6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>; 141 def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>; 142 def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>; 143 def D6 : Rd<12, "r13:12", [R12, R13]>, DwarfRegNum<[44]>; 144 def D7 : Rd<14, "r15:14", [R14, R15]>, DwarfRegNum<[46]>; 145 def D8 : Rd<16, "r17:16", [R16, R17]>, DwarfRegNum<[48]>; 146 def D9 : Rd<18, "r19:18", [R18, R19]>, DwarfRegNum<[50]>; 147 def D10 : Rd<20, "r21:20", [R20, R21]>, DwarfRegNum<[52]>; 148 def D11 : Rd<22, "r23:22", [R22, R23]>, DwarfRegNum<[54]>; 149 def D12 : Rd<24, "r25:24", [R24, R25]>, DwarfRegNum<[56]>; 150 def D13 : Rd<26, "r27:26", [R26, R27]>, DwarfRegNum<[58]>; 151 def D14 : Rd<28, "r29:28", [R28, R29]>, DwarfRegNum<[60]>; 152 def D15 : Rd<30, "r31:30", [R30, R31], ["lr:fp"]>, DwarfRegNum<[62]>; 153 } 154 155 // Predicate registers. 156 def P0 : Rp<0, "p0">, DwarfRegNum<[63]>; 157 def P1 : Rp<1, "p1">, DwarfRegNum<[64]>; 158 def P2 : Rp<2, "p2">, DwarfRegNum<[65]>; 159 def P3 : Rp<3, "p3">, DwarfRegNum<[66]>; 160 161 // Fake register to represent USR.OVF bit. Arithmetic/saturating instruc- 162 // tions modify this bit, and multiple such instructions are allowed in the 163 // same packet. We need to ignore output dependencies on this bit, but not 164 // on the entire USR. 165 def USR_OVF : Rc<?, "usr.ovf">; 166 167 def USR : Rc<8, "usr", ["c8"]>, DwarfRegNum<[75]> { 168 let SubRegIndices = [subreg_overflow]; 169 let SubRegs = [USR_OVF]; 170 } 171 172 // Control registers. 173 def SA0: Rc<0, "sa0", ["c0"]>, DwarfRegNum<[67]>; 174 def LC0: Rc<1, "lc0", ["c1"]>, DwarfRegNum<[68]>; 175 def SA1: Rc<2, "sa1", ["c2"]>, DwarfRegNum<[69]>; 176 def LC1: Rc<3, "lc1", ["c3"]>, DwarfRegNum<[70]>; 177 def P3_0: Rc<4, "p3:0", ["c4"], [P0, P1, P2, P3]>, 178 DwarfRegNum<[71]>; 179 // When defining more Cn registers, make sure to explicitly mark them 180 // as reserved in HexagonRegisterInfo.cpp. 181 def C5: Rc<5, "c5", ["c5"]>, DwarfRegNum<[72]>; 182 def M0: Rc<6, "m0", ["c6"]>, DwarfRegNum<[73]>; 183 def M1: Rc<7, "m1", ["c7"]>, DwarfRegNum<[74]>; 184 // Define C8 separately and make it aliased with USR. 185 // The problem is that USR has subregisters (e.g. overflow). If USR was 186 // specified as a subregister of C9_8, it would imply that subreg_overflow 187 // and isub_lo can be composed, which leads to all kinds of issues 188 // with lane masks. 189 def C8: Rc<8, "c8", [], [USR]>, DwarfRegNum<[75]>; 190 def PC: Rc<9, "pc", ["c9"]>, DwarfRegNum<[76]>; 191 def UGP: Rc<10, "ugp", ["c10"]>, DwarfRegNum<[77]>; 192 def GP: Rc<11, "gp", ["c11"]>, DwarfRegNum<[78]>; 193 def CS0: Rc<12, "cs0", ["c12"]>, DwarfRegNum<[79]>; 194 def CS1: Rc<13, "cs1", ["c13"]>, DwarfRegNum<[80]>; 195 def UPCYCLELO: Rc<14, "upcyclelo", ["c14"]>, DwarfRegNum<[81]>; 196 def UPCYCLEHI: Rc<15, "upcyclehi", ["c15"]>, DwarfRegNum<[82]>; 197 def FRAMELIMIT: Rc<16, "framelimit", ["c16"]>, DwarfRegNum<[83]>; 198 def FRAMEKEY: Rc<17, "framekey", ["c17"]>, DwarfRegNum<[84]>; 199 def PKTCOUNTLO: Rc<18, "pktcountlo", ["c18"]>, DwarfRegNum<[85]>; 200 def PKTCOUNTHI: Rc<19, "pktcounthi", ["c19"]>, DwarfRegNum<[86]>; 201 def UTIMERLO: Rc<30, "utimerlo", ["c30"]>, DwarfRegNum<[97]>; 202 def UTIMERHI: Rc<31, "utimerhi", ["c31"]>, DwarfRegNum<[98]>; 203 204 // Control registers pairs. 205 let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in { 206 def C1_0 : Rcc<0, "c1:0", [SA0, LC0], ["lc0:sa0"]>, DwarfRegNum<[67]>; 207 def C3_2 : Rcc<2, "c3:2", [SA1, LC1], ["lc1:sa1"]>, DwarfRegNum<[69]>; 208 def C5_4 : Rcc<4, "c5:4", [P3_0, C5]>, DwarfRegNum<[71]>; 209 def C7_6 : Rcc<6, "c7:6", [M0, M1], ["m1:0"]>, DwarfRegNum<[72]>; 210 // Use C8 instead of USR as a subregister of C9_8. 211 def C9_8 : Rcc<8, "c9:8", [C8, PC]>, DwarfRegNum<[74]>; 212 def C11_10 : Rcc<10, "c11:10", [UGP, GP]>, DwarfRegNum<[76]>; 213 def CS : Rcc<12, "c13:12", [CS0, CS1], ["cs1:0"]>, DwarfRegNum<[78]>; 214 def UPCYCLE: Rcc<14, "c15:14", [UPCYCLELO, UPCYCLEHI], ["upcycle"]>, 215 DwarfRegNum<[80]>; 216 def C17_16 : Rcc<16, "c17:16", [FRAMELIMIT, FRAMEKEY]>, DwarfRegNum<[83]>; 217 def PKTCOUNT : Rcc<18, "c19:18", [PKTCOUNTLO, PKTCOUNTHI], ["pktcount"]>, 218 DwarfRegNum<[85]>; 219 def UTIMER : Rcc<30, "c31:30", [UTIMERLO, UTIMERHI], ["utimer"]>, 220 DwarfRegNum<[97]>; 221 } 222 223 foreach i = 0-31 in { 224 def V#i : Ri<i, "v"#i>, DwarfRegNum<[!add(i, 99)]>; 225 def VF#i : R_fake<"__"#!add(i,999999)>, DwarfRegNum<[!add(i, 999999)]>; 226 def VFR#i : R_fake<"__"#!add(i,9999999)>, DwarfRegNum<[!add(i, 9999999)]>; 227 } 228 def VTMP : Ri<0, "vtmp">, DwarfRegNum<[131]>; 229 230 // Aliases of the V* registers used to hold double vec values. 231 let SubRegIndices = [vsub_lo, vsub_hi, vsub_fake], CoveredBySubRegs = 1 in { 232 def W0 : Rd< 0, "v1:0", [V0, V1, VF0]>, DwarfRegNum<[99]>; 233 def W1 : Rd< 2, "v3:2", [V2, V3, VF1]>, DwarfRegNum<[101]>; 234 def W2 : Rd< 4, "v5:4", [V4, V5, VF2]>, DwarfRegNum<[103]>; 235 def W3 : Rd< 6, "v7:6", [V6, V7, VF3]>, DwarfRegNum<[105]>; 236 def W4 : Rd< 8, "v9:8", [V8, V9, VF4]>, DwarfRegNum<[107]>; 237 def W5 : Rd<10, "v11:10", [V10, V11, VF5]>, DwarfRegNum<[109]>; 238 def W6 : Rd<12, "v13:12", [V12, V13, VF6]>, DwarfRegNum<[111]>; 239 def W7 : Rd<14, "v15:14", [V14, V15, VF7]>, DwarfRegNum<[113]>; 240 def W8 : Rd<16, "v17:16", [V16, V17, VF8]>, DwarfRegNum<[115]>; 241 def W9 : Rd<18, "v19:18", [V18, V19, VF9]>, DwarfRegNum<[117]>; 242 def W10 : Rd<20, "v21:20", [V20, V21, VF10]>, DwarfRegNum<[119]>; 243 def W11 : Rd<22, "v23:22", [V22, V23, VF11]>, DwarfRegNum<[121]>; 244 def W12 : Rd<24, "v25:24", [V24, V25, VF12]>, DwarfRegNum<[123]>; 245 def W13 : Rd<26, "v27:26", [V26, V27, VF13]>, DwarfRegNum<[125]>; 246 def W14 : Rd<28, "v29:28", [V28, V29, VF14]>, DwarfRegNum<[127]>; 247 def W15 : Rd<30, "v31:30", [V30, V31, VF15]>, DwarfRegNum<[129]>; 248 } 249 250 // Reverse Aliases of the V* registers used to hold double vec values. 251 let SubRegIndices = [vsub_lo, vsub_hi, vsub_fake], CoveredBySubRegs = 1 in { 252 def WR0 : Rd< 1, "v0:1", [V0, V1, VFR0]>, DwarfRegNum<[161]>; 253 def WR1 : Rd< 3, "v2:3", [V2, V3, VFR1]>, DwarfRegNum<[162]>; 254 def WR2 : Rd< 5, "v4:5", [V4, V5, VFR2]>, DwarfRegNum<[163]>; 255 def WR3 : Rd< 7, "v6:7", [V6, V7, VFR3]>, DwarfRegNum<[164]>; 256 def WR4 : Rd< 9, "v8:9", [V8, V9, VFR4]>, DwarfRegNum<[165]>; 257 def WR5 : Rd<11, "v10:11", [V10, V11, VFR5]>, DwarfRegNum<[166]>; 258 def WR6 : Rd<13, "v12:13", [V12, V13, VFR6]>, DwarfRegNum<[167]>; 259 def WR7 : Rd<15, "v14:15", [V14, V15, VFR7]>, DwarfRegNum<[168]>; 260 def WR8 : Rd<17, "v16:17", [V16, V17, VFR8]>, DwarfRegNum<[169]>; 261 def WR9 : Rd<19, "v18:19", [V18, V19, VFR9]>, DwarfRegNum<[170]>; 262 def WR10: Rd<21, "v20:21", [V20, V21, VFR10]>, DwarfRegNum<[171]>; 263 def WR11: Rd<23, "v22:23", [V22, V23, VFR11]>, DwarfRegNum<[172]>; 264 def WR12: Rd<25, "v24:25", [V24, V25, VFR12]>, DwarfRegNum<[173]>; 265 def WR13: Rd<27, "v26:27", [V26, V27, VFR13]>, DwarfRegNum<[174]>; 266 def WR14: Rd<29, "v28:29", [V28, V29, VFR14]>, DwarfRegNum<[175]>; 267 def WR15: Rd<31, "v30:31", [V30, V31, VFR15]>, DwarfRegNum<[176]>; 268 } 269 270 // Aliases of the V* registers used to hold quad vec values. 271 let SubRegIndices = [wsub_lo, wsub_hi], CoveredBySubRegs = 1 in { 272 def VQ0 : Rd< 0, "v3:0", [W0, W1]>, DwarfRegNum<[252]>; 273 def VQ1 : Rd< 4, "v7:4", [W2, W3]>, DwarfRegNum<[253]>; 274 def VQ2 : Rd< 8, "v11:8", [W4, W5]>, DwarfRegNum<[254]>; 275 def VQ3 : Rd<12, "v15:12", [W6, W7]>, DwarfRegNum<[255]>; 276 def VQ4 : Rd<16, "v19:16", [W8, W9]>, DwarfRegNum<[256]>; 277 def VQ5 : Rd<20, "v23:20", [W10, W11]>, DwarfRegNum<[257]>; 278 def VQ6 : Rd<24, "v27:24", [W12, W13]>, DwarfRegNum<[258]>; 279 def VQ7 : Rd<28, "v31:28", [W14, W15]>, DwarfRegNum<[259]>; 280 } 281 282 // Vector Predicate registers. 283 def Q0 : Rq<0, "q0">, DwarfRegNum<[131]>; 284 def Q1 : Rq<1, "q1">, DwarfRegNum<[132]>; 285 def Q2 : Rq<2, "q2">, DwarfRegNum<[133]>; 286 def Q3 : Rq<3, "q3">, DwarfRegNum<[134]>; 287 288 // System registers. 289 def SGP0 : Rs<0, "sgp0", ["s0"]>, DwarfRegNum<[144]>; 290 def SGP1 : Rs<1, "sgp1", ["s1"]>, DwarfRegNum<[145]>; 291 def STID : Rs<2, "stid", ["s2"]>, DwarfRegNum<[146]>; 292 def ELR : Rs<3, "elr", ["s3"]>, DwarfRegNum<[147]>; 293 def BADVA0 : Rs<4, "badva0", ["s4"]>, DwarfRegNum<[148]>; 294 def BADVA1 : Rs<5, "badva1", ["s5"]>, DwarfRegNum<[149]>; 295 def SSR : Rs<6, "ssr", ["s6"]>, DwarfRegNum<[150]>; 296 def CCR : Rs<7, "ccr", ["s7"]>, DwarfRegNum<[151]>; 297 def HTID : Rs<8, "htid", ["s8"]>, DwarfRegNum<[152]>; 298 def BADVA : Rs<9, "badva", ["s9"]>, DwarfRegNum<[153]>; 299 def IMASK : Rs<10, "imask", ["s10"]>, DwarfRegNum<[154]>; 300 def S11 : Rs<11, "s11">, DwarfRegNum<[155]>; 301 def S12 : Rs<12, "s12">, DwarfRegNum<[156]>; 302 def S13 : Rs<13, "s13">, DwarfRegNum<[157]>; 303 def S14 : Rs<14, "s14">, DwarfRegNum<[158]>; 304 def S15 : Rs<15, "s15">, DwarfRegNum<[159]>; 305 def EVB : Rs<16, "evb", ["s16"]>, DwarfRegNum<[160]>; 306 def MODECTL : Rs<17, "modectl", ["s17"]>, DwarfRegNum<[161]>; 307 def SYSCFG : Rs<18, "syscfg", ["s18"]>, DwarfRegNum<[162]>; 308 def S19 : Rs<19, "s19", ["s19"]>, DwarfRegNum<[163]>; 309 def S20 : Rs<20, "s20", ["s20"]>, DwarfRegNum<[164]>; 310 def VID : Rs<21, "vid", ["s21"]>, DwarfRegNum<[165]>; 311 def S22 : Rs<22, "s22", ["s22"]>, DwarfRegNum<[166]>; 312 def S23 : Rs<23, "s23">, DwarfRegNum<[167]>; 313 def S24 : Rs<24, "s24">, DwarfRegNum<[168]>; 314 def S25 : Rs<25, "s25">, DwarfRegNum<[169]>; 315 def S26 : Rs<26, "s26">, DwarfRegNum<[170]>; 316 def CFGBASE : Rs<27, "cfgbase", ["s27"]>, DwarfRegNum<[171]>; 317 def DIAG : Rs<28, "diag", ["s28"]>, DwarfRegNum<[172]>; 318 def REV : Rs<29, "rev", ["s29"]>, DwarfRegNum<[173]>; 319 def PCYCLELO : Rs<30, "pcyclelo", ["s30"]>, DwarfRegNum<[174]>; 320 def PCYCLEHI : Rs<31, "pcyclehi", ["s31"]>, DwarfRegNum<[175]>; 321 def ISDBST : Rs<32, "isdbst", ["s32"]>, DwarfRegNum<[176]>; 322 def ISDBCFG0 : Rs<33, "isdbcfg0", ["s33"]>, DwarfRegNum<[177]>; 323 def ISDBCFG1 : Rs<34, "isdbcfg1", ["s34"]>, DwarfRegNum<[178]>; 324 def S35 : Rs<35, "s35">, DwarfRegNum<[179]>; 325 def BRKPTPC0 : Rs<36, "brkptpc0", ["s36"]>, DwarfRegNum<[180]>; 326 def BRKPTCFG0: Rs<37, "brkptcfg0", ["s37"]>, DwarfRegNum<[181]>; 327 def BRKPTPC1 : Rs<38, "brkptpc1", ["s38"]>, DwarfRegNum<[182]>; 328 def BRKPTCFG1: Rs<39, "brkptcfg1", ["s39"]>, DwarfRegNum<[183]>; 329 def ISDBMBXIN: Rs<40, "isdbmbxin", ["s40"]>, DwarfRegNum<[184]>; 330 def ISDBMBXOUT: Rs<41, "isdbmbxout", ["s41"]>, DwarfRegNum<[185]>; 331 def ISDBEN: Rs<42, "isdben", ["s42"]>, DwarfRegNum<[186]>; 332 def ISDBGPR: Rs<43, "isdbgpr", ["s43"]>, DwarfRegNum<[187]>; 333 def S44: Rs<44, "s44">, DwarfRegNum<[188]>; 334 def S45: Rs<45, "s45">, DwarfRegNum<[189]>; 335 def S46: Rs<46, "s46">, DwarfRegNum<[190]>; 336 def S47: Rs<47, "s47">, DwarfRegNum<[191]>; 337 def PMUCNT0: Rs<48, "pmucnt0", ["s48"]>, DwarfRegNum<[192]>; 338 def PMUCNT1: Rs<49, "pmucnt1", ["s49"]>, DwarfRegNum<[193]>; 339 def PMUCNT2: Rs<50, "pmucnt2", ["s50"]>, DwarfRegNum<[194]>; 340 def PMUCNT3: Rs<51, "pmucnt3", ["s51"]>, DwarfRegNum<[195]>; 341 def PMUEVTCFG: Rs<52, "pmuevtcfg", ["s52"]>, DwarfRegNum<[196]>; 342 def PMUCFG: Rs<53, "pmucfg", ["s53"]>, DwarfRegNum<[197]>; 343 def S54: Rs<54, "s54">, DwarfRegNum<[198]>; 344 def S55: Rs<55, "s55">, DwarfRegNum<[199]>; 345 def S56: Rs<56, "s56">, DwarfRegNum<[200]>; 346 def S57: Rs<57, "s57">, DwarfRegNum<[201]>; 347 def S58: Rs<58, "s58">, DwarfRegNum<[202]>; 348 def S59: Rs<59, "s59">, DwarfRegNum<[203]>; 349 def S60: Rs<60, "s60">, DwarfRegNum<[204]>; 350 def S61: Rs<61, "s61">, DwarfRegNum<[205]>; 351 def S62: Rs<62, "s62">, DwarfRegNum<[206]>; 352 def S63: Rs<63, "s63">, DwarfRegNum<[207]>; 353 def S64: Rs<64, "s64">, DwarfRegNum<[208]>; 354 def S65: Rs<65, "s65">, DwarfRegNum<[209]>; 355 def S66: Rs<66, "s66">, DwarfRegNum<[210]>; 356 def S67: Rs<67, "s67">, DwarfRegNum<[211]>; 357 def S68: Rs<68, "s68">, DwarfRegNum<[212]>; 358 def S69: Rs<69, "s69">, DwarfRegNum<[213]>; 359 def S70: Rs<70, "s70">, DwarfRegNum<[214]>; 360 def S71: Rs<71, "s71">, DwarfRegNum<[215]>; 361 def S72: Rs<72, "s72">, DwarfRegNum<[216]>; 362 def S73: Rs<73, "s73">, DwarfRegNum<[217]>; 363 def S74: Rs<74, "s74">, DwarfRegNum<[218]>; 364 def S75: Rs<75, "s75">, DwarfRegNum<[219]>; 365 def S76: Rs<76, "s76">, DwarfRegNum<[220]>; 366 def S77: Rs<77, "s77">, DwarfRegNum<[221]>; 367 def S78: Rs<78, "s78">, DwarfRegNum<[222]>; 368 def S79: Rs<79, "s79">, DwarfRegNum<[223]>; 369 def S80: Rs<80, "s80">, DwarfRegNum<[224]>; 370 371 // System Register Pair 372 let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in { 373 def SGP1_0 : Rss<0, "s1:0", [SGP0, SGP1], ["sgp1:0"]>, DwarfRegNum<[144]>; 374 def S3_2 : Rss<2, "s3:2", [STID, ELR]>, DwarfRegNum<[146]>; 375 def S5_4 : Rss<4, "s5:4", [BADVA0, BADVA1], ["badva1:0"]>, 376 DwarfRegNum<[148]>; 377 def S7_6 : Rss<6, "s7:6", [SSR, CCR], ["ccr:ssr"]>, DwarfRegNum<[150]>; 378 def S9_8 : Rss<8, "s9:8", [HTID, BADVA]>, DwarfRegNum<[152]>; 379 def S11_10 : Rss<10, "s11:10", [IMASK, S11]>, DwarfRegNum<[154]>; 380 def S13_12 : Rss<12, "s13:12", [S12, S13]>, DwarfRegNum<[156]>; 381 def S15_14 : Rss<14, "s15:14", [S14, S15]>, DwarfRegNum<[158]>; 382 def S17_16 : Rss<16, "s17:16", [EVB, MODECTL]>, DwarfRegNum<[160]>; 383 def S19_18 : Rss<18, "s19:18", [SYSCFG, S19]>, DwarfRegNum<[162]>; 384 def S21_20 : Rss<20, "s21:20", [S20, VID]>, DwarfRegNum<[164]>; 385 def S23_22 : Rss<22, "s23:22", [S22, S23]>, DwarfRegNum<[166]>; 386 def S25_24 : Rss<24, "s25:24", [S24, S25]>, DwarfRegNum<[168]>; 387 def S27_26 : Rss<26, "s27:26", [S26, CFGBASE]>, DwarfRegNum<[170]>; 388 def S29_28 : Rss<28, "s29:28", [DIAG, REV]>, DwarfRegNum<[172]>; 389 def S31_30 : Rss<30, "s31:30", [PCYCLELO, PCYCLEHI], ["pcycle"]>, DwarfRegNum<[174]>; 390 def S33_32 : Rss<32, "s33:32", [ISDBST, ISDBCFG0]>, DwarfRegNum<[176]>; 391 def S35_34 : Rss<34, "s35:34", [ISDBCFG1, S35]>, DwarfRegNum<[178]>; 392 def S37_36 : Rss<36, "s37:36", [BRKPTPC0, BRKPTCFG0]>, DwarfRegNum<[180]>; 393 def S39_38 : Rss<38, "s39:38", [BRKPTPC1, BRKPTCFG1]>, DwarfRegNum<[182]>; 394 def S41_40 : Rss<40, "s41:40", [ISDBMBXIN, ISDBMBXOUT]>, DwarfRegNum<[184]>; 395 def S43_42 : Rss<42, "s43:42", [ISDBEN, ISDBGPR]>, DwarfRegNum<[186]>; 396 def S45_44 : Rss<44, "s45:44", [S44, S45]>, DwarfRegNum<[188]>; 397 def S47_46 : Rss<46, "s47:46", [S46, S47]>, DwarfRegNum<[190]>; 398 def S49_48 : Rss<48, "s49:48", [PMUCNT0, PMUCNT1]>, DwarfRegNum<[192]>; 399 def S51_50 : Rss<50, "s51:50", [PMUCNT2, PMUCNT3]>, DwarfRegNum<[194]>; 400 def S53_52 : Rss<52, "s53:52", [PMUEVTCFG, PMUCFG]>, DwarfRegNum<[196]>; 401 def S55_54 : Rss<54, "s55:54", [S54, S55]>, DwarfRegNum<[198]>; 402 def S57_56 : Rss<56, "s57:56", [S56, S57]>, DwarfRegNum<[200]>; 403 def S59_58 : Rss<58, "s59:58", [S58, S59]>, DwarfRegNum<[202]>; 404 def S61_60 : Rss<60, "s61:60", [S60, S61]>, DwarfRegNum<[204]>; 405 def S63_62 : Rss<62, "s63:62", [S62, S63]>, DwarfRegNum<[206]>; 406 def S65_64 : Rss<64, "s65:64", [S64, S65]>, DwarfRegNum<[208]>; 407 def S67_66 : Rss<66, "s67:66", [S66, S67]>, DwarfRegNum<[210]>; 408 def S69_68 : Rss<68, "s69:68", [S68, S69]>, DwarfRegNum<[212]>; 409 def S71_70 : Rss<70, "s71:70", [S70, S71]>, DwarfRegNum<[214]>; 410 def S73_72 : Rss<72, "s73:72", [S72, S73]>, DwarfRegNum<[216]>; 411 def S75_74 : Rss<74, "s75:74", [S74, S75]>, DwarfRegNum<[218]>; 412 def S77_76 : Rss<76, "s77:76", [S77, S76]>, DwarfRegNum<[219]>; 413 def S79_78 : Rss<78, "s79:78", [S79, S78]>, DwarfRegNum<[220]>; 414 } 415 416 // Guest Registers 417 def GELR: Rg<0, "gelr", ["g0"]>, DwarfRegNum<[220]>; 418 def GSR: Rg<1, "gsr", ["g1"]>, DwarfRegNum<[221]>; 419 def GOSP: Rg<2, "gosp", ["g2"]>, DwarfRegNum<[222]>; 420 def G3: Rg<3, "gbadva", ["g3"]>, DwarfRegNum<[223]>; 421 def G4: Rg<4, "g4">, DwarfRegNum<[224]>; 422 def G5: Rg<5, "g5">, DwarfRegNum<[225]>; 423 def G6: Rg<6, "g6">, DwarfRegNum<[226]>; 424 def G7: Rg<7, "g7">, DwarfRegNum<[227]>; 425 def G8: Rg<8, "g8">, DwarfRegNum<[228]>; 426 def G9: Rg<9, "g9">, DwarfRegNum<[229]>; 427 def G10: Rg<10, "g10">, DwarfRegNum<[230]>; 428 def G11: Rg<11, "g11">, DwarfRegNum<[231]>; 429 def G12: Rg<12, "g12">, DwarfRegNum<[232]>; 430 def G13: Rg<13, "g13">, DwarfRegNum<[233]>; 431 def G14: Rg<14, "g14">, DwarfRegNum<[234]>; 432 def G15: Rg<15, "g15">, DwarfRegNum<[235]>; 433 def GPMUCNT4: Rg<16, "gpmucnt4", ["g16"]>, DwarfRegNum<[236]>; 434 def GPMUCNT5: Rg<17, "gpmucnt5", ["g17"]>, DwarfRegNum<[237]>; 435 def GPMUCNT6: Rg<18, "gpmucnt6", ["g18"]>, DwarfRegNum<[238]>; 436 def GPMUCNT7: Rg<19, "gpmucnt7", ["g19"]>, DwarfRegNum<[239]>; 437 def G20: Rg<20, "g20">, DwarfRegNum<[240]>; 438 def G21: Rg<21, "g21">, DwarfRegNum<[241]>; 439 def G22: Rg<22, "g22">, DwarfRegNum<[242]>; 440 def G23: Rg<23, "g23">, DwarfRegNum<[243]>; 441 def GPCYCLELO: Rg<24, "gpcyclelo", ["g24"]>, DwarfRegNum<[244]>; 442 def GPCYCLEHI: Rg<25, "gpcyclehi", ["g25"]>, DwarfRegNum<[245]>; 443 def GPMUCNT0: Rg<26, "gpmucnt0", ["g26"]>, DwarfRegNum<[246]>; 444 def GPMUCNT1: Rg<27, "gpmucnt1", ["g27"]>, DwarfRegNum<[247]>; 445 def GPMUCNT2: Rg<28, "gpmucnt2", ["g28"]>, DwarfRegNum<[248]>; 446 def GPMUCNT3: Rg<29, "gpmucnt3", ["g29"]>, DwarfRegNum<[249]>; 447 def G30: Rg<30, "g30">, DwarfRegNum<[250]>; 448 def G31: Rg<31, "g31">, DwarfRegNum<[251]>; 449 450 // Guest Register Pairs 451 let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in { 452 def G1_0 : Rgg<0, "g1:0", [GELR, GSR]>, DwarfRegNum<[220]>; 453 def G3_2 : Rgg<2, "g3:2", [GOSP, G3]>, DwarfRegNum<[222]>; 454 def G5_4 : Rgg<4, "g5:4", [G4, G5]>, DwarfRegNum<[224]>; 455 def G7_6 : Rgg<6, "g7:6", [G6, G7]>, DwarfRegNum<[226]>; 456 def G9_8 : Rgg<8, "g9:8", [G8, G9]>, DwarfRegNum<[228]>; 457 def G11_10 : Rgg<10, "g11:10", [G10, G11]>, DwarfRegNum<[230]>; 458 def G13_12 : Rgg<12, "g13:12", [G12, G13]>, DwarfRegNum<[232]>; 459 def G15_14 : Rgg<14, "g15:14", [G14, G15]>, DwarfRegNum<[234]>; 460 def G17_16 : Rgg<16, "g17:16", [GPMUCNT4, GPMUCNT5]>, DwarfRegNum<[236]>; 461 def G19_18 : Rgg<18, "g19:18", [GPMUCNT6, GPMUCNT7]>, DwarfRegNum<[238]>; 462 def G21_20 : Rgg<20, "g21:20", [G20, G21]>, DwarfRegNum<[240]>; 463 def G23_22 : Rgg<22, "g23:22", [G22, G23]>, DwarfRegNum<[242]>; 464 def G25_24 : Rgg<24, "g25:24", [GPCYCLELO, GPCYCLEHI]>, DwarfRegNum<[244]>; 465 def G27_26 : Rgg<26, "g27:26", [GPMUCNT0, GPMUCNT1]>, DwarfRegNum<[246]>; 466 def G29_28 : Rgg<28, "g29:28", [GPMUCNT2, GPMUCNT3]>, DwarfRegNum<[248]>; 467 def G31_30 : Rgg<30, "g31:30", [G30, G31]>, DwarfRegNum<[250]>; 468 } 469 470} 471 472// HVX types 473 474def VecI1: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 475 [v64i1, v128i1, v64i1]>; 476def VecI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 477 [v64i8, v128i8, v64i8]>; 478def VecI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 479 [v32i16, v64i16, v32i16]>; 480def VecI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 481 [v16i32, v32i32, v16i32]>; 482def VecF16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 483 [v32f16, v64f16, v32f16]>; 484def VecF32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 485 [v16f32, v32f32, v16f32]>; 486 487def VecPI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 488 [v128i8, v256i8, v128i8]>; 489def VecPI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 490 [v64i16, v128i16, v64i16]>; 491def VecPI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 492 [v32i32, v64i32, v32i32]>; 493def VecPF16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 494 [v64f16, v128f16, v64f16]>; 495def VecPF32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 496 [v32f32, v64f32, v32f32]>; 497 498def VecQ8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 499 [v64i1, v128i1, v64i1]>; 500def VecQ16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 501 [v32i1, v64i1, v32i1]>; 502def VecQ32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 503 [v16i1, v32i1, v16i1]>; 504 505// HVX register classes 506 507def HvxVR : RegisterClass<"Hexagon", [VecI8, VecI16, VecI32, VecF16, VecF32], 512, 508 (add (sequence "V%u", 0, 31), VTMP)> { 509 let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode], 510 [RegInfo<512,512,512>, RegInfo<1024,1024,1024>, RegInfo<512,512,512>]>; 511} 512 513def HvxWR : RegisterClass<"Hexagon", [VecPI8, VecPI16, VecPI32, VecPF16, VecPF32], 1024, 514 (add (sequence "W%u", 0, 15), (sequence "WR%u", 0, 15))> { 515 let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode], 516 [RegInfo<1024,1024,512>, RegInfo<2048,2048,1024>, RegInfo<1024,1024,512>]>; 517} 518 519def HvxQR : RegisterClass<"Hexagon", [VecI1, VecQ8, VecQ16, VecQ32], 128, 520 (add Q0, Q1, Q2, Q3)> { 521 let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode], 522 [RegInfo<64,512,512>, RegInfo<128,1024,1024>, RegInfo<64,512,512>]>; 523} 524 525def HvxVQR : RegisterClass<"Hexagon", [untyped], 2048, 526 (add (sequence "VQ%u", 0, 7))> { 527 let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode], 528 [RegInfo<2048,2048,512>, RegInfo<4096,4096,1024>, RegInfo<2048,2048,512>]>; 529} 530 531// Core register classes 532 533def IntRegs : RegisterClass<"Hexagon", [i32, f32, v4i8, v2i16], 32, 534 (add (sequence "R%u", 0, 9), (sequence "R%u", 12, 28), 535 R10, R11, R29, R30, R31)>; 536 537// Registers are listed in reverse order for allocation preference reasons. 538def GeneralSubRegs : RegisterClass<"Hexagon", [i32], 32, 539 (add R23, R22, R21, R20, R19, R18, R17, R16, 540 R7, R6, R5, R4, R3, R2, R1, R0)>; 541 542def IntRegsLow8 : RegisterClass<"Hexagon", [i32], 32, 543 (add R7, R6, R5, R4, R3, R2, R1, R0)> ; 544 545def DoubleRegs : RegisterClass<"Hexagon", [i64, f64, v8i8, v4i16, v2i32], 64, 546 (add (sequence "D%u", 0, 4), (sequence "D%u", 6, 13), D5, D14, D15)>; 547 548def GeneralDoubleLow8Regs : RegisterClass<"Hexagon", [i64], 64, 549 (add D11, D10, D9, D8, D3, D2, D1, D0)>; 550 551let Size = 32 in 552def PredRegs : RegisterClass<"Hexagon", 553 [i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32, (add P0, P1, P2, P3)>; 554 555let Size = 32 in 556def ModRegs : RegisterClass<"Hexagon", [i32], 32, (add M0, M1)>; 557 558let Size = 32, isAllocatable = 0 in 559def CtrRegs : RegisterClass<"Hexagon", [i32], 32, 560 (add LC0, SA0, LC1, SA1, P3_0, C5, C8, PC, UGP, GP, CS0, CS1, 561 UPCYCLELO, UPCYCLEHI, 562 FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI, UTIMERLO, UTIMERHI, 563 M0, M1, USR)>; 564 565let Size = 64 in 566def VectRegRev : RegisterClass<"Hexagon", [i64], 64, 567 (add (sequence "WR%u", 0, 15))>; 568 569let isAllocatable = 0 in 570def UsrBits : RegisterClass<"Hexagon", [i1], 0, (add USR_OVF)>; 571 572let Size = 64, isAllocatable = 0 in 573def CtrRegs64 : RegisterClass<"Hexagon", [i64], 64, 574 (add C1_0, C3_2, C5_4, C7_6, C9_8, C11_10, CS, UPCYCLE, C17_16, 575 PKTCOUNT, UTIMER)>; 576 577let Size = 32, isAllocatable = 0 in 578def GuestRegs : RegisterClass<"Hexagon", [i32], 32, 579 (add GELR, GSR, GOSP, 580 (sequence "G%u", 3, 15), 581 GPMUCNT4, GPMUCNT5, GPMUCNT6, GPMUCNT7, 582 G20, G21, G22, G23, 583 GPCYCLELO, GPCYCLEHI, GPMUCNT0, GPMUCNT1, 584 GPMUCNT2, GPMUCNT3, 585 G30, G31)>; 586 587let Size = 64, isAllocatable = 0 in 588def GuestRegs64 : RegisterClass<"Hexagon", [i64], 64, 589 (add G1_0, G3_2, 590 G5_4, G7_6, G9_8, G11_10, G13_12, G15_14, 591 G17_16, G19_18, 592 G21_20, G23_22, 593 G25_24, G27_26, G29_28, 594 G31_30)>; 595 596let Size = 32, isAllocatable = 0 in 597def SysRegs : RegisterClass<"Hexagon", [i32], 32, 598 (add SGP0, SGP1, STID, ELR, BADVA0, BADVA1, 599 SSR, CCR, HTID, BADVA, IMASK, 600 S11, S12, S13, S14, S15, 601 S19, S23, S25, 602 EVB, MODECTL, SYSCFG, S20, VID, S22, S24, 603 S26, CFGBASE, DIAG, REV, PCYCLEHI, 604 PCYCLELO, ISDBST, ISDBCFG0, ISDBCFG1, S35, 605 BRKPTPC0, BRKPTCFG0, BRKPTPC1, BRKPTCFG1, 606 ISDBMBXIN, ISDBMBXOUT, ISDBEN, ISDBGPR, 607 S44, S45, S46, S47, 608 PMUCNT0, PMUCNT1, PMUCNT2, PMUCNT3, 609 PMUEVTCFG, PMUCFG, S54, S55, S56, S57, 610 S58, S59, S60, S61, S62, S63, S64, S65, S66, S67, 611 S68, S69, S70, S71, S72, S73, S74, S75, S76, S77, 612 S78, S79, S80 613 )>; 614 615let Size = 64, isAllocatable = 0 in 616def SysRegs64 : RegisterClass<"Hexagon", [i64], 64, 617 (add SGP1_0, 618 S3_2, S5_4, S7_6, S9_8, 619 S11_10, S13_12, S15_14, 620 S17_16, S19_18, S21_20, 621 S23_22, S25_24, 622 S27_26, S29_28, S31_30, S33_32, S35_34, 623 S37_36, S39_38, S41_40, S43_42, S45_44, 624 S47_46, S49_48, S51_50, S53_52, 625 S55_54, S57_56, S59_58, 626 S61_60, S63_62, S65_64, S67_66, S69_68, 627 S71_70, S73_72, S75_74, S77_76, S79_78 628 )>; 629 630// These registers are new for v62 and onward. 631// The function RegisterMatchesArch() uses this list for validation. 632let isAllocatable = 0 in 633def V62Regs : RegisterClass<"Hexagon", [i32], 32, 634 (add FRAMELIMIT, FRAMEKEY, C17_16, PKTCOUNTLO, PKTCOUNTHI, PKTCOUNT, 635 UTIMERLO, UTIMERHI, UTIMER)>; 636 637// These registers are new for v65 and onward. 638let Size = 32, isAllocatable = 0 in 639def V65Regs : RegisterClass<"Hexagon", [i32], 32, (add VTMP)>; 640 641 642def HexagonCSR 643 : CalleeSavedRegs<(add R16, R17, R18, R19, R20, R21, R22, R23, 644 R24, R25, R26, R27)>; 645