1//=-HexagonScheduleV68.td - HexagonV68 Scheduling Definitions *- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//
10// ScalarItin and HVXItin contain some old itineraries
11// still used by a handful of instructions. Hopefully, we will be able
12// to get rid of them soon.
13def HexagonV68ItinList : DepScalarItinV68, ScalarItin,
14                         DepHVXItinV68, HVXItin, PseudoItin {
15  list<InstrItinData> ItinList =
16    !listconcat(DepScalarItinV68_list, ScalarItin_list,
17                DepHVXItinV68_list, HVXItin_list, PseudoItin_list);
18}
19
20def HexagonItinerariesV68 :
21      ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
22                            CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1,
23                            CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL,
24                            CVI_ALL_NOMEM, CVI_ZW],
25                            [Hex_FWD, HVX_FWD],
26                            HexagonV68ItinList.ItinList>;
27
28def HexagonModelV68 : SchedMachineModel {
29  // Max issue per cycle == bundle width.
30  let IssueWidth = 4;
31  let Itineraries = HexagonItinerariesV68;
32  let LoadLatency = 1;
33  let CompleteModel = 0;
34}
35
36//===----------------------------------------------------------------------===//
37// Hexagon V68 Resource Definitions -
38//===----------------------------------------------------------------------===//
39