1//=-HexagonScheduleV71.td - HexagonV71 Scheduling Definitions *- tablegen -*-=//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//
11// ScalarItin and HVXItin contain some old itineraries still used by a handful
12// of instructions. Hopefully, we will be able to get rid of them soon.
13def HexagonV71ItinList : DepScalarItinV71, ScalarItin,
14                         DepHVXItinV71, HVXItin, PseudoItin {
15  list<InstrItinData> ItinList =
16    !listconcat(DepScalarItinV71_list, ScalarItin_list,
17                DepHVXItinV71_list, HVXItin_list, PseudoItin_list);
18}
19
20def HexagonItinerariesV71 :
21      ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
22                            CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1,
23                            CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL,
24                            CVI_ALL_NOMEM, CVI_ZW],
25                            [Hex_FWD, HVX_FWD],
26                            HexagonV71ItinList.ItinList>;
27
28def HexagonModelV71 : SchedMachineModel {
29  // Max issue per cycle == bundle width.
30  let IssueWidth = 4;
31  let Itineraries = HexagonItinerariesV71;
32  let LoadLatency = 1;
33  let CompleteModel = 0;
34}
35
36//===----------------------------------------------------------------------===//
37// Hexagon V71 Resource Definitions -
38//===----------------------------------------------------------------------===//
39
40