1//=-HexagonScheduleV71T.td - Hexagon V71 Tiny Core Scheduling Definition ----=//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10class HexagonV71TPseudoItin {
11  list<InstrItinData> V71TPseudoItin_list = [
12    InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [2, 1, 1],
13                          [Hex_FWD, Hex_FWD, Hex_FWD]>,
14    InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
15                            InstrStage<1, [SLOT2, SLOT3]>],
16                           [2, 1, 1],
17                           [Hex_FWD, Hex_FWD, Hex_FWD]>,
18    InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>],
19                          [2, 1, 1]>,
20    InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>], [2]>
21  ];
22}
23
24//
25// HVXItin contains some old itineraries still used by a handful of
26// instructions. Hopefully, we will be able to get rid of them soon.
27def HexagonV71TItinList : DepScalarItinV71T, DepHVXItinV71, HVXItin,
28                          HexagonV71TPseudoItin {
29  list<InstrItinData> V71TItin_list = [
30    InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0]>],
31                                   [3, 1, 1],
32                                   [Hex_FWD, Hex_FWD, Hex_FWD]>,
33    InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0]>],
34                                   [1, 1, 3, 3],
35                                   [Hex_FWD, Hex_FWD]>
36  ];
37  list<InstrItinData> ItinList =
38    !listconcat(DepScalarItinV71T_list, V71TItin_list, DepHVXItinV71_list,
39                HVXItin_list, V71TPseudoItin_list);
40}
41
42def HexagonItinerariesV71T :
43      ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
44                            CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1,
45                            CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL,
46                            CVI_ALL_NOMEM, CVI_ZW],
47                            [Hex_FWD, HVX_FWD],
48                            HexagonV71TItinList.ItinList>;
49
50def HexagonModelV71T : SchedMachineModel {
51  let IssueWidth = 3;
52  let Itineraries = HexagonItinerariesV71T;
53  let LoadLatency = 1;
54  let CompleteModel = 0;
55}
56
57//===----------------------------------------------------------------------===//
58// Hexagon V71 Tiny Core Resource Definitions -
59//===----------------------------------------------------------------------===//
60