1 //===- HexagonPacketizer.h - VLIW packetizer --------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H
10 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H
11 
12 #include "llvm/CodeGen/DFAPacketizer.h"
13 #include "llvm/CodeGen/MachineBasicBlock.h"
14 #include "llvm/CodeGen/ScheduleDAG.h"
15 #include <vector>
16 
17 namespace llvm {
18 
19 class HexagonInstrInfo;
20 class HexagonRegisterInfo;
21 class MachineBranchProbabilityInfo;
22 class MachineFunction;
23 class MachineInstr;
24 class MachineLoopInfo;
25 class TargetRegisterClass;
26 
27 class HexagonPacketizerList : public VLIWPacketizerList {
28   // Vector of instructions assigned to the packet that has just been created.
29   std::vector<MachineInstr *> OldPacketMIs;
30 
31   // Has the instruction been promoted to a dot-new instruction.
32   bool PromotedToDotNew;
33 
34   // Has the instruction been glued to allocframe.
35   bool GlueAllocframeStore;
36 
37   // Has the feeder instruction been glued to new value jump.
38   bool GlueToNewValueJump;
39 
40   // This holds the offset value, when pruning the dependences.
41   int64_t ChangedOffset;
42 
43   // Check if there is a dependence between some instruction already in this
44   // packet and this instruction.
45   bool Dependence;
46 
47   // Only check for dependence if there are resources available to
48   // schedule this instruction.
49   bool FoundSequentialDependence;
50 
51   bool MemShufDisabled = false;
52 
53   // Track MIs with ignored dependence.
54   std::vector<MachineInstr*> IgnoreDepMIs;
55 
56   // Set to true if the packet contains an instruction that stalls with an
57   // instruction from the previous packet.
58   bool PacketStalls = false;
59 
60 protected:
61   /// A handle to the branch probability pass.
62   const MachineBranchProbabilityInfo *MBPI;
63   const MachineLoopInfo *MLI;
64 
65 private:
66   const HexagonInstrInfo *HII;
67   const HexagonRegisterInfo *HRI;
68   const bool Minimal;
69 
70 public:
71   HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
72                         AAResults *AA, const MachineBranchProbabilityInfo *MBPI,
73                         bool Minimal);
74 
75   // initPacketizerState - initialize some internal flags.
76   void initPacketizerState() override;
77 
78   // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
79   bool ignorePseudoInstruction(const MachineInstr &MI,
80                                const MachineBasicBlock *MBB) override;
81 
82   // isSoloInstruction - return true if instruction MI can not be packetized
83   // with any other instruction, which means that MI itself is a packet.
84   bool isSoloInstruction(const MachineInstr &MI) override;
85 
86   // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
87   // together.
88   bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override;
89 
90   // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
91   // and SUJ.
92   bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override;
93 
94   bool foundLSInPacket();
95   MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override;
96   void endPacket(MachineBasicBlock *MBB,
97                  MachineBasicBlock::iterator MI) override;
98   bool shouldAddToPacket(const MachineInstr &MI) override;
99 
100   void unpacketizeSoloInstrs(MachineFunction &MF);
101 
102 protected:
103   bool getmemShufDisabled() {
104     return MemShufDisabled;
105   };
106   void setmemShufDisabled(bool val) {
107     MemShufDisabled = val;
108   };
109   bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType,
110                        unsigned DepReg);
111   bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType,
112                        MachineBasicBlock::iterator &MII,
113                        const TargetRegisterClass *RC);
114   bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU,
115                           unsigned DepReg, MachineBasicBlock::iterator &MII,
116                           const TargetRegisterClass *RC);
117   void cleanUpDotCur();
118 
119   bool promoteToDotNew(MachineInstr &MI, SDep::Kind DepType,
120                        MachineBasicBlock::iterator &MII,
121                        const TargetRegisterClass *RC);
122   bool canPromoteToDotNew(const MachineInstr &MI, const SUnit *PacketSU,
123                           unsigned DepReg, MachineBasicBlock::iterator &MII,
124                           const TargetRegisterClass *RC);
125   bool canPromoteToNewValue(const MachineInstr &MI, const SUnit *PacketSU,
126                             unsigned DepReg, MachineBasicBlock::iterator &MII);
127   bool canPromoteToNewValueStore(const MachineInstr &MI,
128                                  const MachineInstr &PacketMI, unsigned DepReg);
129   bool demoteToDotOld(MachineInstr &MI);
130   bool useCallersSP(MachineInstr &MI);
131   void useCalleesSP(MachineInstr &MI);
132   bool updateOffset(SUnit *SUI, SUnit *SUJ);
133   void undoChangedOffset(MachineInstr &MI);
134   bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2);
135   bool restrictingDepExistInPacket(MachineInstr&, unsigned);
136   bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC);
137   bool isCurifiable(MachineInstr &MI);
138   bool cannotCoexist(const MachineInstr &MI, const MachineInstr &MJ);
139 
140   bool isPromotedToDotNew() const {
141     return PromotedToDotNew;
142   }
143 
144   bool tryAllocateResourcesForConstExt(bool Reserve);
145   bool canReserveResourcesForConstExt();
146   void reserveResourcesForConstExt();
147   bool hasDeadDependence(const MachineInstr &I, const MachineInstr &J);
148   bool hasControlDependence(const MachineInstr &I, const MachineInstr &J);
149   bool hasRegMaskDependence(const MachineInstr &I, const MachineInstr &J);
150   bool hasDualStoreDependence(const MachineInstr &I, const MachineInstr &J);
151   bool producesStall(const MachineInstr &MI);
152 };
153 
154 } // end namespace llvm
155 
156 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H
157