1 //===-- HexagonMCTargetDesc.h - Hexagon Target Descriptions -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Hexagon specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
14 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
15 
16 #include "llvm/MC/MCRegisterInfo.h"
17 #include "llvm/Support/CommandLine.h"
18 #include <cstdint>
19 #include <string>
20 
21 #define Hexagon_POINTER_SIZE 4
22 
23 #define Hexagon_PointerSize (Hexagon_POINTER_SIZE)
24 #define Hexagon_PointerSize_Bits (Hexagon_POINTER_SIZE * 8)
25 #define Hexagon_WordSize Hexagon_PointerSize
26 #define Hexagon_WordSize_Bits Hexagon_PointerSize_Bits
27 
28 // allocframe saves LR and FP on stack before allocating
29 // a new stack frame. This takes 8 bytes.
30 #define HEXAGON_LRFP_SIZE 8
31 
32 // Normal instruction size (in bytes).
33 #define HEXAGON_INSTR_SIZE 4
34 
35 // Maximum number of words and instructions in a packet.
36 #define HEXAGON_PACKET_SIZE 4
37 #define HEXAGON_MAX_PACKET_SIZE (HEXAGON_PACKET_SIZE * HEXAGON_INSTR_SIZE)
38 // Minimum number of instructions in an end-loop packet.
39 #define HEXAGON_PACKET_INNER_SIZE 2
40 #define HEXAGON_PACKET_OUTER_SIZE 3
41 // Maximum number of instructions in a packet before shuffling,
42 // including a compound one or a duplex or an extender.
43 #define HEXAGON_PRESHUFFLE_PACKET_SIZE (HEXAGON_PACKET_SIZE + 3)
44 
45 // Name of the global offset table as defined by the Hexagon ABI
46 #define HEXAGON_GOT_SYM_NAME "_GLOBAL_OFFSET_TABLE_"
47 
48 namespace llvm {
49 
50 struct InstrStage;
51 class FeatureBitset;
52 class MCAsmBackend;
53 class MCCodeEmitter;
54 class MCContext;
55 class MCInstrInfo;
56 class MCObjectTargetWriter;
57 class MCRegisterInfo;
58 class MCSubtargetInfo;
59 class MCTargetOptions;
60 class Target;
61 class Triple;
62 class StringRef;
63 
64 extern cl::opt<bool> HexagonDisableCompound;
65 extern cl::opt<bool> HexagonDisableDuplex;
66 extern const InstrStage HexagonStages[];
67 
68 MCInstrInfo *createHexagonMCInstrInfo();
69 MCRegisterInfo *createHexagonMCRegisterInfo(StringRef TT);
70 
71 namespace Hexagon_MC {
72   StringRef selectHexagonCPU(StringRef CPU);
73 
74   FeatureBitset completeHVXFeatures(const FeatureBitset &FB);
75   /// Create a Hexagon MCSubtargetInfo instance. This is exposed so Asm parser,
76   /// etc. do not need to go through TargetRegistry.
77   MCSubtargetInfo *createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU,
78                                                 StringRef FS);
79   MCSubtargetInfo const *getArchSubtarget(MCSubtargetInfo const *STI);
80   void addArchSubtarget(MCSubtargetInfo const *STI,
81                         StringRef FS);
82   unsigned GetELFFlags(const MCSubtargetInfo &STI);
83 
84   llvm::ArrayRef<MCPhysReg> GetVectRegRev();
85 }
86 
87 MCCodeEmitter *createHexagonMCCodeEmitter(const MCInstrInfo &MCII,
88                                           MCContext &MCT);
89 
90 MCAsmBackend *createHexagonAsmBackend(const Target &T,
91                                       const MCSubtargetInfo &STI,
92                                       const MCRegisterInfo &MRI,
93                                       const MCTargetOptions &Options);
94 
95 std::unique_ptr<MCObjectTargetWriter>
96 createHexagonELFObjectWriter(uint8_t OSABI, StringRef CPU);
97 
98 unsigned HexagonGetLastSlot();
99 unsigned HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes);
100 
101 } // End llvm namespace
102 
103 // Define symbolic names for Hexagon registers.  This defines a mapping from
104 // register name to register number.
105 //
106 #define GET_REGINFO_ENUM
107 #include "HexagonGenRegisterInfo.inc"
108 
109 // Defines symbolic names for the Hexagon instructions.
110 //
111 #define GET_INSTRINFO_ENUM
112 #define GET_INSTRINFO_SCHED_ENUM
113 #define GET_INSTRINFO_MC_HELPER_DECLS
114 #include "HexagonGenInstrInfo.inc"
115 
116 #define GET_SUBTARGETINFO_ENUM
117 #include "HexagonGenSubtargetInfo.inc"
118 
119 #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
120