10b57cec5SDimitry Andric//===- LanaiInstrFormats.td - Lanai Instruction Formats ----*- tablegen -*-===// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric 90b57cec5SDimitry Andricclass InstLanai<dag outs, dag ins, string asmstr, list<dag> pattern> 100b57cec5SDimitry Andric : Instruction { 110b57cec5SDimitry Andric field bits<32> Inst; 120b57cec5SDimitry Andric field bits<32> SoftFail = 0; 130b57cec5SDimitry Andric let Size = 4; 140b57cec5SDimitry Andric 150b57cec5SDimitry Andric let Namespace = "Lanai"; 160b57cec5SDimitry Andric let DecoderNamespace = "Lanai"; 170b57cec5SDimitry Andric 180b57cec5SDimitry Andric bits<4> Opcode; 190b57cec5SDimitry Andric let Inst{31 - 28} = Opcode; 200b57cec5SDimitry Andric 210b57cec5SDimitry Andric dag OutOperandList = outs; 220b57cec5SDimitry Andric dag InOperandList = ins; 230b57cec5SDimitry Andric let AsmString = asmstr; 240b57cec5SDimitry Andric let Pattern = pattern; 250b57cec5SDimitry Andric} 260b57cec5SDimitry Andric 270b57cec5SDimitry Andric//------------------------------------------------------------------------------ 280b57cec5SDimitry Andric// Register Immediate (RI) 290b57cec5SDimitry Andric//------------------------------------------------------------------------------ 300b57cec5SDimitry Andric// Encoding: 310b57cec5SDimitry Andric// ----------------------------------------------------------------- 320b57cec5SDimitry Andric// |0.A.A.A| . . . . | . . . . |F.H| . . . . . . . . . . . . . . . | 330b57cec5SDimitry Andric// ----------------------------------------------------------------- 340b57cec5SDimitry Andric// opcode Rd Rs1 constant (16) 350b57cec5SDimitry Andric// 360b57cec5SDimitry Andric// Action: 370b57cec5SDimitry Andric// Rd <- Rs1 op constant 380b57cec5SDimitry Andric// 390b57cec5SDimitry Andric// Except for shift instructions, `H' determines whether the constant 400b57cec5SDimitry Andric// is in the high (1) or low (0) word. The other halfword is 0x0000, 410b57cec5SDimitry Andric// except for the `AND' instruction (`AAA' = 100), for which the other 420b57cec5SDimitry Andric// halfword is 0xFFFF, and shifts (`AAA' = 111), for which the constant is 430b57cec5SDimitry Andric// sign extended. 440b57cec5SDimitry Andric// 450b57cec5SDimitry Andric// `F' determines whether the instruction modifies (1) or does not 460b57cec5SDimitry Andric// modify (0) the program flags. 470b57cec5SDimitry Andric// 480b57cec5SDimitry Andric// `AAA' specifies the operation: `add' (000), `addc' (001), `sub' 490b57cec5SDimitry Andric// (010), `subb' (011), `and' (100), `or' (101), `xor' (110), or `shift' 500b57cec5SDimitry Andric// (111). For the shift, `H' specifies a logical (0) or arithmetic (1) 510b57cec5SDimitry Andric// shift. The amount and direction of the shift are determined by the 520b57cec5SDimitry Andric// sign extended constant interpreted as a two's complement number. The 530b57cec5SDimitry Andric// shift operation is defined only for the range of: 540b57cec5SDimitry Andric// 31 ... 0 -1 ... -31 550b57cec5SDimitry Andric// \ / \ / 560b57cec5SDimitry Andric// left right 570b57cec5SDimitry Andric// shift shift 580b57cec5SDimitry Andric// 590b57cec5SDimitry Andric// If and only if the `F' bit is 1, RI instructions modify the 600b57cec5SDimitry Andric// condition bits, `Z' (Zero), `N' (Negative), `V' (oVerflow), and `C' 610b57cec5SDimitry Andric// (Carry), according to the result. If the flags are updated, they are 620b57cec5SDimitry Andric// updated as follows: 630b57cec5SDimitry Andric// `Z' 640b57cec5SDimitry Andric// is set if the result is zero and cleared otherwise. 650b57cec5SDimitry Andric// 660b57cec5SDimitry Andric// `N' 670b57cec5SDimitry Andric// is set to the most significant bit of the result. 680b57cec5SDimitry Andric// 690b57cec5SDimitry Andric// `V' 700b57cec5SDimitry Andric// For arithmetic instructions (`add', `addc', `sub', `subb') `V' is 710b57cec5SDimitry Andric// set if the sign (most significant) bits of the input operands are 720b57cec5SDimitry Andric// the same but different from the sign bit of the result and cleared 730b57cec5SDimitry Andric// otherwise. For other RI instructions, `V' is cleared. 740b57cec5SDimitry Andric// 750b57cec5SDimitry Andric// `C' 760b57cec5SDimitry Andric// For arithmetic instructions, `C' is set/cleared if there is/is_not 770b57cec5SDimitry Andric// a carry generated out of the most significant when performing the 780b57cec5SDimitry Andric// twos-complement addition (`sub(a,b) == a + ~b + 1', `subb(a,b) == 790b57cec5SDimitry Andric// a + ~b + `C''). For left shifts, `C' is set to the least 800b57cec5SDimitry Andric// significant bit discarded by the shift operation. For all other 810b57cec5SDimitry Andric// operations, `C' is cleared. 820b57cec5SDimitry Andric// 830b57cec5SDimitry Andric// A Jump is accomplished by `Rd' being `pc', and it has one shadow. 840b57cec5SDimitry Andric// 850b57cec5SDimitry Andric// The all-0s word is the instruction `R0 <- R0 + 0', which is a no-op. 860b57cec5SDimitry Andricclass InstRI<bits<3> op, dag outs, dag ins, string asmstr, 870b57cec5SDimitry Andric list<dag> pattern> 880b57cec5SDimitry Andric : InstLanai<outs, ins, asmstr, pattern>, Sched<[WriteALU]> { 890b57cec5SDimitry Andric let Itinerary = IIC_ALU; 900b57cec5SDimitry Andric bits<5> Rd; 910b57cec5SDimitry Andric bits<5> Rs1; 920b57cec5SDimitry Andric bit F; 930b57cec5SDimitry Andric bit H; 940b57cec5SDimitry Andric bits<16> imm16; 950b57cec5SDimitry Andric 960b57cec5SDimitry Andric let Opcode{3} = 0; 970b57cec5SDimitry Andric let Opcode{2 - 0} = op; 980b57cec5SDimitry Andric let Inst{27 - 23} = Rd; 990b57cec5SDimitry Andric let Inst{22 - 18} = Rs1; 1000b57cec5SDimitry Andric let Inst{17} = F; 1010b57cec5SDimitry Andric let Inst{16} = H; 1020b57cec5SDimitry Andric let Inst{15 - 0} = imm16; 1030b57cec5SDimitry Andric} 1040b57cec5SDimitry Andric 1050b57cec5SDimitry Andric//------------------------------------------------------------------------------ 1060b57cec5SDimitry Andric// Register Register (RR) 1070b57cec5SDimitry Andric//------------------------------------------------------------------------------ 1080b57cec5SDimitry Andric// Encoding: 1090b57cec5SDimitry Andric// ----------------------------------------------------------------- 1100b57cec5SDimitry Andric// |1.1.0.0| . . . . | . . . . |F.I| . . . . |B.B.B|J.J.J.J.J|D.D.D| 1110b57cec5SDimitry Andric// ----------------------------------------------------------------- 1120b57cec5SDimitry Andric// opcode Rd Rs1 Rs2 \ operation / 1130b57cec5SDimitry Andric// 1140b57cec5SDimitry Andric// Action: 1150b57cec5SDimitry Andric// `Rd <- Rs1 op Rs2' iff condition DDDI is true. 1160b57cec5SDimitry Andric// 1170b57cec5SDimitry Andric// `DDDI' is as described for the BR instruction. 1180b57cec5SDimitry Andric// 1190b57cec5SDimitry Andric// `F' determines whether the instruction modifies (1) or does not 1200b57cec5SDimitry Andric// modify (0) the program flags. 1210b57cec5SDimitry Andric// 1220b57cec5SDimitry Andric// `BBB' determines the operation: `add' (000), `addc' (001), `sub' 1230b57cec5SDimitry Andric// (010), `subb' (011), `and' (100), `or' (101), `xor' (110), or "special" 1240b57cec5SDimitry Andric// (111). The `JJJJJ' field is irrelevant except for special. 1250b57cec5SDimitry Andric// 1260b57cec5SDimitry Andric// `JJJJJ' determines which special operation is performed. `10---' 1270b57cec5SDimitry Andric// is a logical shift, and `11---' is an arithmetic shift, and ‘00000` is 1280b57cec5SDimitry Andric// the SELECT operation. The amount and direction of the shift are 1290b57cec5SDimitry Andric// determined by the contents of `Rs2' interpreted as a two's complement 1300b57cec5SDimitry Andric// number (in the same way as shifts in the Register-Immediate 1310b57cec5SDimitry Andric// instructions in *Note RI::). For the SELECT operation, Rd gets Rs1 if 1320b57cec5SDimitry Andric// condition DDDI is true, Rs2 otherwise. All other `JJJJJ' combinations 1330b57cec5SDimitry Andric// are reserved for instructions that may be defined in the future. 1340b57cec5SDimitry Andric// 1350b57cec5SDimitry Andric// If the `F' bit is 1, RR instructions modify the condition bits, `Z' 1360b57cec5SDimitry Andric// (Zero), `N' (Negative), `V' (oVerflow), and `C' (Carry), according to 1370b57cec5SDimitry Andric// the result. All RR instructions modify the `Z', `N', and `V' flags. 1380b57cec5SDimitry Andric// Except for arithmetic instructions (`add', `addc', `sub', `subb'), `V' 1390b57cec5SDimitry Andric// is cleared. Only arithmetic instructions and shifts modify `C'. Right 1400b57cec5SDimitry Andric// shifts clear C. 1410b57cec5SDimitry Andric// 1420b57cec5SDimitry Andric// DDDI is as described in the table for the BR instruction and only used for 1430b57cec5SDimitry Andric// the select instruction. 1440b57cec5SDimitry Andric// 1450b57cec5SDimitry Andric// A Jump is accomplished by `Rd' being `pc', and it has one shadow. 1460b57cec5SDimitry Andricclass InstRR<bits<3> op, dag outs, dag ins, string asmstr, 1470b57cec5SDimitry Andric list<dag> pattern> 1480b57cec5SDimitry Andric : InstLanai<outs, ins, asmstr, pattern>, Sched<[WriteALU]> { 1490b57cec5SDimitry Andric let Itinerary = IIC_ALU; 1500b57cec5SDimitry Andric bits<5> Rd; 1510b57cec5SDimitry Andric bits<5> Rs1; 1520b57cec5SDimitry Andric bits<5> Rs2; 1530b57cec5SDimitry Andric bit F; 1540b57cec5SDimitry Andric bits<4> DDDI; 1550b57cec5SDimitry Andric bits<5> JJJJJ; 1560b57cec5SDimitry Andric 1570b57cec5SDimitry Andric let Opcode = 0b1100; 1580b57cec5SDimitry Andric let Inst{27 - 23} = Rd; 1590b57cec5SDimitry Andric let Inst{22 - 18} = Rs1; 1600b57cec5SDimitry Andric let Inst{17} = F; 1610b57cec5SDimitry Andric let Inst{16} = DDDI{0}; 1620b57cec5SDimitry Andric let Inst{15 - 11} = Rs2; 1630b57cec5SDimitry Andric let Inst{10 - 8} = op; 1640b57cec5SDimitry Andric let Inst{7 - 3} = JJJJJ; 1650b57cec5SDimitry Andric let Inst{2 - 0} = DDDI{3 - 1}; 1660b57cec5SDimitry Andric} 1670b57cec5SDimitry Andric 1680b57cec5SDimitry Andric//------------------------------------------------------------------------------ 1690b57cec5SDimitry Andric// Register Memory (RM) 1700b57cec5SDimitry Andric//------------------------------------------------------------------------------ 1710b57cec5SDimitry Andric// Encoding: 1720b57cec5SDimitry Andric// ----------------------------------------------------------------- 1730b57cec5SDimitry Andric// |1.0.0.S| . . . . | . . . . |P.Q| . . . . . . . . . . . . . . . | 1740b57cec5SDimitry Andric// ----------------------------------------------------------------- 1750b57cec5SDimitry Andric// opcode Rd Rs1 constant (16) 1760b57cec5SDimitry Andric// 1770b57cec5SDimitry Andric// Action: 1780b57cec5SDimitry Andric// Rd <- Memory(ea) (Load) see below for the 1790b57cec5SDimitry Andric// Memory(ea) <- Rd (Store) definition of ea. 1800b57cec5SDimitry Andric// 1810b57cec5SDimitry Andric// `S' determines whether the instruction is a Load (0) or a Store (1). 1820b57cec5SDimitry Andric// Loads appear in Rd one cycle after this instruction executes. If the 1830b57cec5SDimitry Andric// following instruction reads Rd, that instruction will be delayed by 1 1840b57cec5SDimitry Andric// clock cycle. 1850b57cec5SDimitry Andric// 1860b57cec5SDimitry Andric// PQ operation 1870b57cec5SDimitry Andric// -- ------------------------------------------ 1880b57cec5SDimitry Andric// 00 ea = Rs1 1890b57cec5SDimitry Andric// 01 ea = Rs1, Rs1 <- Rs1 + constant 1900b57cec5SDimitry Andric// 10 ea = Rs1 + constant 1910b57cec5SDimitry Andric// 11 ea = Rs1 + constant, Rs1 <- Rs1 + constant 1920b57cec5SDimitry Andric// 1930b57cec5SDimitry Andric// The constant is sign-extended for this instruction. 1940b57cec5SDimitry Andric// 1950b57cec5SDimitry Andric// A Jump is accomplished by `Rd' being `pc', and it has *two* delay slots. 1960b57cec5SDimitry Andricclass InstRM<bit S, dag outs, dag ins, string asmstr, list<dag> pattern> 1970b57cec5SDimitry Andric : InstLanai<outs, ins, asmstr, pattern> { 1980b57cec5SDimitry Andric bits<5> Rd; 1990b57cec5SDimitry Andric bits<5> Rs1; 200bdd1243dSDimitry Andric bits<1> P; 201bdd1243dSDimitry Andric bits<1> Q; 2020b57cec5SDimitry Andric bits<16> imm16; 2030b57cec5SDimitry Andric // Dummy variables to allow multiclass definition of RM and RRM 2040b57cec5SDimitry Andric bits<2> YL; 2050b57cec5SDimitry Andric bit E; 2060b57cec5SDimitry Andric 2070b57cec5SDimitry Andric let Opcode{3 - 1} = 0b100; 2080b57cec5SDimitry Andric let Opcode{0} = S; 2090b57cec5SDimitry Andric let Inst{27 - 23} = Rd; 2100b57cec5SDimitry Andric let Inst{22 - 18} = Rs1; 2110b57cec5SDimitry Andric let Inst{17} = P; 2120b57cec5SDimitry Andric let Inst{16} = Q; 2130b57cec5SDimitry Andric let Inst{15 - 0} = imm16; 2140b57cec5SDimitry Andric 2150b57cec5SDimitry Andric let PostEncoderMethod = "adjustPqBitsRmAndRrm"; 2160b57cec5SDimitry Andric} 2170b57cec5SDimitry Andric 2180b57cec5SDimitry Andric//------------------------------------------------------------------------------ 2190b57cec5SDimitry Andric// Register Register Memory (RRM) 2200b57cec5SDimitry Andric//------------------------------------------------------------------------------ 2210b57cec5SDimitry Andric// Encoding: 2220b57cec5SDimitry Andric// ----------------------------------------------------------------- 2230b57cec5SDimitry Andric// |1.0.1.S| . . . . | . . . . |P.Q| . . . . |B.B.B|J.J.J.J.J|Y.L.E| 2240b57cec5SDimitry Andric// ----------------------------------------------------------------- 2250b57cec5SDimitry Andric// opcode Rd Rs1 Rs2 \ operation / 2260b57cec5SDimitry Andric// 2270b57cec5SDimitry Andric// Action: 2280b57cec5SDimitry Andric// Rd <- Memory(ea) (Load) see below for the 2290b57cec5SDimitry Andric// Memory(ea) <- Rd (Store) definition of ea. 2300b57cec5SDimitry Andric// 2310b57cec5SDimitry Andric// The RRM instruction is identical to the RM (*note RM::.) instruction 2320b57cec5SDimitry Andric// except that: 2330b57cec5SDimitry Andric// 2340b57cec5SDimitry Andric// 1. `Rs1 + constant' is replaced with `Rs1 op Rs2', where `op' is 2350b57cec5SDimitry Andric// determined in the same way as in the RR instruction (*note RR::.) 2360b57cec5SDimitry Andric// and 2370b57cec5SDimitry Andric// 2380b57cec5SDimitry Andric// 2. part-word memory accesses are allowed as specified below. 2390b57cec5SDimitry Andric// 2400b57cec5SDimitry Andric// If `BBB' != 111 (i.e.: For all but shift operations): 2410b57cec5SDimitry Andric// If `YLE' = 01- => fuLl-word memory access 2420b57cec5SDimitry Andric// If `YLE' = 00- => half-word memory access 2430b57cec5SDimitry Andric// If `YLE' = 10- => bYte memory access 2440b57cec5SDimitry Andric// If `YLE' = --1 => loads are zEro extended 2450b57cec5SDimitry Andric// If `YLE' = --0 => loads are sign extended 2460b57cec5SDimitry Andric// 2470b57cec5SDimitry Andric// If `BBB' = 111 (For shift operations): 2480b57cec5SDimitry Andric// fullword memory access are performed. 2490b57cec5SDimitry Andric// 2500b57cec5SDimitry Andric// All part-word loads write the least significant part of the 2510b57cec5SDimitry Andric// destination register with the higher-order bits zero- or sign-extended. 2520b57cec5SDimitry Andric// All part-word stores store the least significant part-word of the 2530b57cec5SDimitry Andric// source register in the destination memory location. 2540b57cec5SDimitry Andric// 2550b57cec5SDimitry Andric// A Jump is accomplished by `Rd' being `pc', and it has *two* delay slots. 2560b57cec5SDimitry Andricclass InstRRM<bit S, dag outs, dag ins, string asmstr, 2570b57cec5SDimitry Andric list<dag> pattern> 2580b57cec5SDimitry Andric : InstLanai<outs, ins, asmstr, pattern> { 2590b57cec5SDimitry Andric bits<5> Rd; 2600b57cec5SDimitry Andric bits<5> Rs1; 2610b57cec5SDimitry Andric bits<5> Rs2; 262bdd1243dSDimitry Andric bits<1> P; 263bdd1243dSDimitry Andric bits<1> Q; 2640b57cec5SDimitry Andric bits<3> BBB; 2650b57cec5SDimitry Andric bits<5> JJJJJ; 2660b57cec5SDimitry Andric bits<2> YL; 2670b57cec5SDimitry Andric bit E; 2680b57cec5SDimitry Andric 2690b57cec5SDimitry Andric let Opcode{3 - 1} = 0b101; 2700b57cec5SDimitry Andric let Opcode{0} = S; 2710b57cec5SDimitry Andric let Inst{27 - 23} = Rd; 2720b57cec5SDimitry Andric let Inst{22 - 18} = Rs1; 2730b57cec5SDimitry Andric let Inst{17} = P; 2740b57cec5SDimitry Andric let Inst{16} = Q; 2750b57cec5SDimitry Andric let Inst{15 - 11} = Rs2; 2760b57cec5SDimitry Andric let Inst{10 - 8} = BBB; 2770b57cec5SDimitry Andric let Inst{7 - 3} = JJJJJ; 2780b57cec5SDimitry Andric let Inst{2 - 1} = YL; 2790b57cec5SDimitry Andric let Inst{0} = E; 2800b57cec5SDimitry Andric 2810b57cec5SDimitry Andric let PostEncoderMethod = "adjustPqBitsRmAndRrm"; 2820b57cec5SDimitry Andric} 2830b57cec5SDimitry Andric 2840b57cec5SDimitry Andric//------------------------------------------------------------------------------ 2850b57cec5SDimitry Andric// Conditional Branch (BR) 2860b57cec5SDimitry Andric//------------------------------------------------------------------------------ 2870b57cec5SDimitry Andric// Encoding: 2880b57cec5SDimitry Andric// ----------------------------------------------------------------- 2890b57cec5SDimitry Andric// |1.1.1.0|D.D.D| . . . . . . . . . . . . . . . . . . . . . . |0.I| 2900b57cec5SDimitry Andric// ----------------------------------------------------------------- 2910b57cec5SDimitry Andric// opcode condition constant (23) 2920b57cec5SDimitry Andric// 2930b57cec5SDimitry Andric// Action: 2940b57cec5SDimitry Andric// if (condition) { `pc' <- 4*(zero-extended constant) } 2950b57cec5SDimitry Andric// 2960b57cec5SDimitry Andric// The BR instruction is an absolute branch. 2970b57cec5SDimitry Andric// The constant is scaled as shown by its position in the instruction word such 2980b57cec5SDimitry Andric// that it specifies word-aligned addresses in the range [0,2^25-4] 2990b57cec5SDimitry Andric// 3000b57cec5SDimitry Andric// The `DDDI' field selects the condition that causes the branch to be taken. 3010b57cec5SDimitry Andric// (the `I' (Invert sense) bit inverts the sense of the condition): 3020b57cec5SDimitry Andric// 3030b57cec5SDimitry Andric// DDDI logical function [code, used for...] 3040b57cec5SDimitry Andric// ---- -------------------------------------- ------------------------ 3050b57cec5SDimitry Andric// 0000 1 [T, true] 3060b57cec5SDimitry Andric// 0001 0 [F, false] 3070b57cec5SDimitry Andric// 0010 C AND Z' [HI, high] 3080b57cec5SDimitry Andric// 0011 C' OR Z [LS, low or same] 3090b57cec5SDimitry Andric// 0100 C' [CC, carry cleared] 3100b57cec5SDimitry Andric// 0101 C [CS, carry set] 3110b57cec5SDimitry Andric// 0110 Z' [NE, not equal] 3120b57cec5SDimitry Andric// 0111 Z [EQ, equal] 3130b57cec5SDimitry Andric// 1000 V' [VC, oVerflow cleared] 3140b57cec5SDimitry Andric// 1001 V [VS, oVerflow set] 3150b57cec5SDimitry Andric// 1010 N' [PL, plus] 3160b57cec5SDimitry Andric// 1011 N [MI, minus] 3170b57cec5SDimitry Andric// 1100 (N AND V) OR (N' AND V') [GE, greater than or equal] 3180b57cec5SDimitry Andric// 1101 (N AND V') OR (N' AND V) [LT, less than] 3190b57cec5SDimitry Andric// 1110 (N AND V AND Z') OR (N' AND V' AND Z') [GT, greater than] 3200b57cec5SDimitry Andric// 1111 (Z) OR (N AND V') OR (N' AND V) [LE, less than or equal] 3210b57cec5SDimitry Andric// 3220b57cec5SDimitry Andric// If the branch is not taken, the BR instruction is a no-op. If the branch is 3230b57cec5SDimitry Andric// taken, the processor starts executing instructions at the branch target 3240b57cec5SDimitry Andric// address *after* the processor has executed one more instruction. That is, 3250b57cec5SDimitry Andric// the branch has one “branch delay slot”. Be very careful if you find yourself 3260b57cec5SDimitry Andric// wanting to put a branch in a branch delays slot! 3270b57cec5SDimitry Andricclass InstBR<dag outs, dag ins, string asmstr, list<dag> pattern> 3280b57cec5SDimitry Andric : InstLanai<outs, ins, asmstr, pattern> { 3290b57cec5SDimitry Andric let Itinerary = IIC_ALU; 3300b57cec5SDimitry Andric bits<25> addr; 3310b57cec5SDimitry Andric bits<4> DDDI; 3320b57cec5SDimitry Andric 3330b57cec5SDimitry Andric let Opcode = 0b1110; 3340b57cec5SDimitry Andric let Inst{27 - 25} = DDDI{3 - 1}; 3350b57cec5SDimitry Andric let Inst{24 - 0} = addr; 3360b57cec5SDimitry Andric // These instructions overwrite the last two address bits (which are assumed 3370b57cec5SDimitry Andric // and ensured to be 0). 3380b57cec5SDimitry Andric let Inst{1} = 0; 3390b57cec5SDimitry Andric let Inst{0} = DDDI{0}; 3400b57cec5SDimitry Andric} 3410b57cec5SDimitry Andric 3420b57cec5SDimitry Andric//------------------------------------------------------------------------------ 3430b57cec5SDimitry Andric// Conditional Branch Relative (BRR) 3440b57cec5SDimitry Andric//------------------------------------------------------------------------------ 3450b57cec5SDimitry Andric// Encoding: 3460b57cec5SDimitry Andric// ----------------------------------------------------------------- 3470b57cec5SDimitry Andric// |1.1.1.0|D.D.D|1|-| . . . . |-.-| . . . . . . . . . . . . . |1.I| 3480b57cec5SDimitry Andric// ----------------------------------------------------------------- 3490b57cec5SDimitry Andric// opcode condition Rs1 constant (14) 3500b57cec5SDimitry Andric// Action: 3510b57cec5SDimitry Andric// if (condition) { ‘pc’ <- Rs1 + 4*sign-extended constant) } 3520b57cec5SDimitry Andric// 3530b57cec5SDimitry Andric// BRR behaves like BR, except the branch target address is a 16-bit PC relative 3540b57cec5SDimitry Andric// offset. 3550b57cec5SDimitry Andricclass InstBRR<dag outs, dag ins, string asmstr, list<dag> pattern> 3560b57cec5SDimitry Andric : InstLanai<outs, ins, asmstr, pattern> { 3570b57cec5SDimitry Andric bits<4> DDDI; 3580b57cec5SDimitry Andric bits<5> Rs1; 3590b57cec5SDimitry Andric bits<16> imm16; 3600b57cec5SDimitry Andric 3610b57cec5SDimitry Andric let Opcode = 0b1110; 3620b57cec5SDimitry Andric let Inst{27 - 25} = DDDI{3 - 1}; 3630b57cec5SDimitry Andric let Inst{24} = 1; 3640b57cec5SDimitry Andric let Inst{22 - 18} = Rs1; 3650b57cec5SDimitry Andric let Inst{17 - 16} = 0; 3660b57cec5SDimitry Andric let Inst{15 - 0} = imm16; 3670b57cec5SDimitry Andric // Overwrite last two bits which have to be zero 3680b57cec5SDimitry Andric let Inst{1} = 1; 3690b57cec5SDimitry Andric let Inst{0} = DDDI{0}; 3700b57cec5SDimitry Andric 3710b57cec5SDimitry Andric // Set don't cares to zero 3720b57cec5SDimitry Andric let Inst{23} = 0; 3730b57cec5SDimitry Andric} 3740b57cec5SDimitry Andric 3750b57cec5SDimitry Andric//------------------------------------------------------------------------------ 3760b57cec5SDimitry Andric// Conditional Set (SCC) 3770b57cec5SDimitry Andric//------------------------------------------------------------------------------ 3780b57cec5SDimitry Andric// Encoding: 3790b57cec5SDimitry Andric// ----------------------------------------------------------------- 3800b57cec5SDimitry Andric// |1.1.1.0|D.D.D|0.-| . . . . |-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-|1.I| 3810b57cec5SDimitry Andric// ----------------------------------------------------------------- 3820b57cec5SDimitry Andric// opcode condition Rs1 3830b57cec5SDimitry Andric// 3840b57cec5SDimitry Andric// Action: 3850b57cec5SDimitry Andric// Rs1 <- logical function result 3860b57cec5SDimitry Andric// 3870b57cec5SDimitry Andric// SCC sets dst_reg to the boolean result of computing the logical function 3880b57cec5SDimitry Andric// specified by DDDI, as described in the table for the BR instruction. 3890b57cec5SDimitry Andricclass InstSCC<dag outs, dag ins, string asmstr, 3900b57cec5SDimitry Andric list<dag> pattern> 3910b57cec5SDimitry Andric : InstLanai<outs, ins, asmstr, pattern> { 3920b57cec5SDimitry Andric let Itinerary = IIC_ALU; 3930b57cec5SDimitry Andric bits<5> Rs1; // dst_reg in documentation 3940b57cec5SDimitry Andric bits<4> DDDI; 3950b57cec5SDimitry Andric 3960b57cec5SDimitry Andric let Opcode = 0b1110; 3970b57cec5SDimitry Andric let Inst{27 - 25} = DDDI{3 - 1}; 3980b57cec5SDimitry Andric let Inst{24} = 0; 3990b57cec5SDimitry Andric let Inst{22 - 18} = Rs1; 4000b57cec5SDimitry Andric let Inst{1} = 1; 4010b57cec5SDimitry Andric let Inst{0} = DDDI{0}; 4020b57cec5SDimitry Andric 4030b57cec5SDimitry Andric // Set don't cares to zero 4040b57cec5SDimitry Andric let Inst{23} = 0; 4050b57cec5SDimitry Andric let Inst{17 - 2} = 0; 4060b57cec5SDimitry Andric} 4070b57cec5SDimitry Andric 4080b57cec5SDimitry Andric//------------------------------------------------------------------------------ 4090b57cec5SDimitry Andric// Special Load/Store (SLS) 4100b57cec5SDimitry Andric//------------------------------------------------------------------------------ 4110b57cec5SDimitry Andric// 4120b57cec5SDimitry Andric// Encoding: 4130b57cec5SDimitry Andric// ----------------------------------------------------------------- 4140b57cec5SDimitry Andric// |1.1.1.1| . . . . | . . . . |0.S| . . . . . . . . . . . . . . . | 4150b57cec5SDimitry Andric// ----------------------------------------------------------------- 4160b57cec5SDimitry Andric// opcode Rd addr 5msb's address 16 lsb's 4170b57cec5SDimitry Andric// 4180b57cec5SDimitry Andric// Action: 4190b57cec5SDimitry Andric// If S = 0 (LOAD): Rd <- Memory(address); 4200b57cec5SDimitry Andric// If S = 1 (STORE): Memory(address) <- Rd 4210b57cec5SDimitry Andric// 4220b57cec5SDimitry Andric// The timing is the same as for RM (*note RM::.) and RRM (*note 4230b57cec5SDimitry Andric// RRM::.) instructions. The two low-order bits of the 21-bit address are 4240b57cec5SDimitry Andric// ignored. The address is zero extended. Fullword memory accesses are 4250b57cec5SDimitry Andric// performed. 4260b57cec5SDimitry Andricclass InstSLS<bit S, dag outs, dag ins, string asmstr, list<dag> pattern> 4270b57cec5SDimitry Andric : InstLanai<outs, ins, asmstr, pattern> { 4280b57cec5SDimitry Andric bits<5> Rd; 4290b57cec5SDimitry Andric bits<5> msb; 4300b57cec5SDimitry Andric bits<16> lsb; 4310b57cec5SDimitry Andric 4320b57cec5SDimitry Andric let Opcode = 0b1111; 4330b57cec5SDimitry Andric let Inst{27 - 23} = Rd; 4340b57cec5SDimitry Andric let Inst{22 - 18} = msb; 4350b57cec5SDimitry Andric let Inst{17} = 0; 4360b57cec5SDimitry Andric let Inst{16} = S; 4370b57cec5SDimitry Andric let Inst{15 - 0} = lsb; 4380b57cec5SDimitry Andric} 4390b57cec5SDimitry Andric 4400b57cec5SDimitry Andric//------------------------------------------------------------------------------ 4410b57cec5SDimitry Andric// Special Load Immediate (SLI) 4420b57cec5SDimitry Andric//------------------------------------------------------------------------------ 4430b57cec5SDimitry Andric// Encoding: 4440b57cec5SDimitry Andric// ----------------------------------------------------------------- 4450b57cec5SDimitry Andric// |1.1.1.1| . . . . | . . . . |1.0| . . . . . . . . . . . . . . . | 4460b57cec5SDimitry Andric// ----------------------------------------------------------------- 4470b57cec5SDimitry Andric// opcode Rd const 5msb's constant 16 lsb's 4480b57cec5SDimitry Andric// 4490b57cec5SDimitry Andric// Action: 4500b57cec5SDimitry Andric// Rd <- constant 4510b57cec5SDimitry Andric// 4520b57cec5SDimitry Andric// The 21-bit constant is zero-extended. The timing is the same as the 4530b57cec5SDimitry Andric// RM instruction (*note RM::.). 4540b57cec5SDimitry Andricclass InstSLI<dag outs, dag ins, string asmstr, list<dag> pattern> 4550b57cec5SDimitry Andric : InstLanai<outs, ins, asmstr, pattern> { 4560b57cec5SDimitry Andric bits<5> Rd; 4570b57cec5SDimitry Andric bits<5> msb; 4580b57cec5SDimitry Andric bits<16> lsb; 4590b57cec5SDimitry Andric 4600b57cec5SDimitry Andric let Opcode = 0b1111; 4610b57cec5SDimitry Andric let Inst{27 - 23} = Rd; 4620b57cec5SDimitry Andric let Inst{22 - 18} = msb; 4630b57cec5SDimitry Andric let Inst{17} = 1; 4640b57cec5SDimitry Andric let Inst{16} = 0; 4650b57cec5SDimitry Andric let Inst{15 - 0} = lsb; 4660b57cec5SDimitry Andric} 4670b57cec5SDimitry Andric 4680b57cec5SDimitry Andric//------------------------------------------------------------------------------ 4690b57cec5SDimitry Andric// Special Part-Word Load/Store (SPLS) 4700b57cec5SDimitry Andric//------------------------------------------------------------------------------ 4710b57cec5SDimitry Andric// Encoding: 4720b57cec5SDimitry Andric// ----------------------------------------------------------------- 4730b57cec5SDimitry Andric// |1.1.1.1| . . . . | . . . . |1.1.0.Y.S.E.P.Q| . . . . . . . . . | 4740b57cec5SDimitry Andric// ----------------------------------------------------------------- 4750b57cec5SDimitry Andric// opcode Rd Rs1 constant (10) 4760b57cec5SDimitry Andric// 4770b57cec5SDimitry Andric// Action: 4780b57cec5SDimitry Andric// If `YS' = 11 (bYte Store): 4790b57cec5SDimitry Andric// Memory(ea) <- (least significant byte of Rr) 4800b57cec5SDimitry Andric// If `YS' = 01 (halfword Store): 4810b57cec5SDimitry Andric// Memory(ea) <- (least significant half-word of Rr) 4820b57cec5SDimitry Andric// If `YS' = 10 (bYte load): Rr <- Memory(ea) 4830b57cec5SDimitry Andric// If `YS' = 00 (halfword load): Rr <- Memory(ea) 4840b57cec5SDimitry Andric// [Note: here ea is determined as in the RM instruction. ] 4850b57cec5SDimitry Andric// If `SE' = 01 then the value is zEro extended 4860b57cec5SDimitry Andric// before being loaded into Rd. 4870b57cec5SDimitry Andric// If `SE' = 00 then the value is sign extended 4880b57cec5SDimitry Andric// before being loaded into Rd. 4890b57cec5SDimitry Andric// 4900b57cec5SDimitry Andric// `P' and `Q' are used to determine `ea' as in the RM instruction. The 4910b57cec5SDimitry Andric// constant is sign extended. The timing is the same as the RM and RRM 4920b57cec5SDimitry Andric// instructions. *Note RM:: and *Note RRM::. 4930b57cec5SDimitry Andric// 4940b57cec5SDimitry Andric// All part-word loads write the part-word into the least significant 4950b57cec5SDimitry Andric// part of the destination register, with the higher-order bits zero- or 4960b57cec5SDimitry Andric// sign-extended. All part-word stores store the least significant 4970b57cec5SDimitry Andric// part-word of the source register into the destination memory location. 4980b57cec5SDimitry Andricclass InstSPLS<dag outs, dag ins, string asmstr, 4990b57cec5SDimitry Andric list<dag> pattern> 5000b57cec5SDimitry Andric : InstLanai<outs, ins, asmstr, pattern> { 5010b57cec5SDimitry Andric bits<5> Rd; 5020b57cec5SDimitry Andric bits<5> Rs1; 5030b57cec5SDimitry Andric bits<5> msb; 5040b57cec5SDimitry Andric bit Y; 5050b57cec5SDimitry Andric bit S; 5060b57cec5SDimitry Andric bit E; 507bdd1243dSDimitry Andric bits<1> P; 508bdd1243dSDimitry Andric bits<1> Q; 5090b57cec5SDimitry Andric bits<10> imm10; 5100b57cec5SDimitry Andric 5110b57cec5SDimitry Andric let Opcode = 0b1111; 5120b57cec5SDimitry Andric let Inst{27 - 23} = Rd; 5130b57cec5SDimitry Andric let Inst{22 - 18} = Rs1; 5140b57cec5SDimitry Andric let Inst{17 - 15} = 0b110; 5150b57cec5SDimitry Andric let Inst{14} = Y; 5160b57cec5SDimitry Andric let Inst{13} = S; 5170b57cec5SDimitry Andric let Inst{12} = E; 5180b57cec5SDimitry Andric let Inst{11} = P; 5190b57cec5SDimitry Andric let Inst{10} = Q; 5200b57cec5SDimitry Andric let Inst{9 - 0} = imm10; 5210b57cec5SDimitry Andric 5220b57cec5SDimitry Andric let PostEncoderMethod = "adjustPqBitsSpls"; 5230b57cec5SDimitry Andric} 5240b57cec5SDimitry Andric 5250b57cec5SDimitry Andric//------------------------------------------------------------------------------ 5260b57cec5SDimitry Andric// Special instructions (popc, leadz, trailz) 5270b57cec5SDimitry Andric//------------------------------------------------------------------------------ 5280b57cec5SDimitry Andric// Encoding: 5290b57cec5SDimitry Andric// ----------------------------------------------------------------- 5300b57cec5SDimitry Andric// |1.1.0.1| Rd | Rs1 |F.-| . . . . | . . | . . . . | OP | 5310b57cec5SDimitry Andric// ----------------------------------------------------------------- 5320b57cec5SDimitry Andric// opcode Rd Rs1 5330b57cec5SDimitry Andric// Action: 5340b57cec5SDimitry Andric// Rd <- Perform action encoded in OP on Rs1 5350b57cec5SDimitry Andric// OP is one of: 5360b57cec5SDimitry Andric// 0b001 POPC Population count; 5370b57cec5SDimitry Andric// 0b010 LEADZ Count number of leading zeros; 5380b57cec5SDimitry Andric// 0b011 TRAILZ Count number of trailing zeros; 5390b57cec5SDimitry Andricclass InstSpecial<bits<3> op, dag outs, dag ins, string asmstr, 5400b57cec5SDimitry Andric list<dag> pattern> : InstLanai<outs, ins, asmstr, 5410b57cec5SDimitry Andric pattern>, Sched<[WriteALU]> { 5420b57cec5SDimitry Andric let Itinerary = IIC_ALU; 5430b57cec5SDimitry Andric bit F; 5440b57cec5SDimitry Andric bits<5> Rd; 5450b57cec5SDimitry Andric bits<5> Rs1; 5460b57cec5SDimitry Andric 5470b57cec5SDimitry Andric let Opcode = 0b1101; 5480b57cec5SDimitry Andric let Inst{27 - 23} = Rd; 5490b57cec5SDimitry Andric let Inst{22 - 18} = Rs1; 5500b57cec5SDimitry Andric let Inst{17} = F; 5510b57cec5SDimitry Andric let Inst{16 - 3} = 0; 5520b57cec5SDimitry Andric let Inst{2 - 0} = op; 5530b57cec5SDimitry Andric} 5540b57cec5SDimitry Andric 5550b57cec5SDimitry Andric// Pseudo instructions 5560b57cec5SDimitry Andricclass Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> 5570b57cec5SDimitry Andric : InstLanai<outs, ins, asmstr, pattern> { 5580b57cec5SDimitry Andric let Inst{15 - 0} = 0; 5590b57cec5SDimitry Andric let isPseudo = 1; 5600b57cec5SDimitry Andric} 561