10b57cec5SDimitry Andric //===-- LanaiRegisterInfo.cpp - Lanai Register Information ------*- C++ -*-===//
20b57cec5SDimitry Andric //
30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
60b57cec5SDimitry Andric //
70b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
80b57cec5SDimitry Andric //
90b57cec5SDimitry Andric // This file contains the Lanai implementation of the TargetRegisterInfo class.
100b57cec5SDimitry Andric //
110b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
120b57cec5SDimitry Andric
130b57cec5SDimitry Andric #include "LanaiRegisterInfo.h"
140b57cec5SDimitry Andric #include "LanaiAluCode.h"
150b57cec5SDimitry Andric #include "LanaiCondCode.h"
160b57cec5SDimitry Andric #include "LanaiFrameLowering.h"
170b57cec5SDimitry Andric #include "LanaiInstrInfo.h"
180b57cec5SDimitry Andric #include "llvm/ADT/BitVector.h"
190b57cec5SDimitry Andric #include "llvm/ADT/STLExtras.h"
200b57cec5SDimitry Andric #include "llvm/CodeGen/MachineFrameInfo.h"
210b57cec5SDimitry Andric #include "llvm/CodeGen/MachineFunction.h"
220b57cec5SDimitry Andric #include "llvm/CodeGen/MachineInstrBuilder.h"
230b57cec5SDimitry Andric #include "llvm/CodeGen/RegisterScavenging.h"
240b57cec5SDimitry Andric #include "llvm/CodeGen/TargetFrameLowering.h"
250b57cec5SDimitry Andric #include "llvm/CodeGen/TargetInstrInfo.h"
260b57cec5SDimitry Andric #include "llvm/IR/Function.h"
270b57cec5SDimitry Andric #include "llvm/IR/Type.h"
280b57cec5SDimitry Andric #include "llvm/Support/ErrorHandling.h"
290b57cec5SDimitry Andric
300b57cec5SDimitry Andric #define GET_REGINFO_TARGET_DESC
310b57cec5SDimitry Andric #include "LanaiGenRegisterInfo.inc"
320b57cec5SDimitry Andric
330b57cec5SDimitry Andric using namespace llvm;
340b57cec5SDimitry Andric
LanaiRegisterInfo()350b57cec5SDimitry Andric LanaiRegisterInfo::LanaiRegisterInfo() : LanaiGenRegisterInfo(Lanai::RCA) {}
360b57cec5SDimitry Andric
370b57cec5SDimitry Andric const uint16_t *
getCalleeSavedRegs(const MachineFunction *) const380b57cec5SDimitry Andric LanaiRegisterInfo::getCalleeSavedRegs(const MachineFunction * /*MF*/) const {
390b57cec5SDimitry Andric return CSR_SaveList;
400b57cec5SDimitry Andric }
410b57cec5SDimitry Andric
getReservedRegs(const MachineFunction & MF) const420b57cec5SDimitry Andric BitVector LanaiRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
430b57cec5SDimitry Andric BitVector Reserved(getNumRegs());
440b57cec5SDimitry Andric
450b57cec5SDimitry Andric Reserved.set(Lanai::R0);
460b57cec5SDimitry Andric Reserved.set(Lanai::R1);
470b57cec5SDimitry Andric Reserved.set(Lanai::PC);
480b57cec5SDimitry Andric Reserved.set(Lanai::R2);
490b57cec5SDimitry Andric Reserved.set(Lanai::SP);
500b57cec5SDimitry Andric Reserved.set(Lanai::R4);
510b57cec5SDimitry Andric Reserved.set(Lanai::FP);
520b57cec5SDimitry Andric Reserved.set(Lanai::R5);
530b57cec5SDimitry Andric Reserved.set(Lanai::RR1);
540b57cec5SDimitry Andric Reserved.set(Lanai::R10);
550b57cec5SDimitry Andric Reserved.set(Lanai::RR2);
560b57cec5SDimitry Andric Reserved.set(Lanai::R11);
570b57cec5SDimitry Andric Reserved.set(Lanai::RCA);
580b57cec5SDimitry Andric Reserved.set(Lanai::R15);
590b57cec5SDimitry Andric if (hasBasePointer(MF))
600b57cec5SDimitry Andric Reserved.set(getBaseRegister());
610b57cec5SDimitry Andric return Reserved;
620b57cec5SDimitry Andric }
630b57cec5SDimitry Andric
requiresRegisterScavenging(const MachineFunction &) const640b57cec5SDimitry Andric bool LanaiRegisterInfo::requiresRegisterScavenging(
650b57cec5SDimitry Andric const MachineFunction & /*MF*/) const {
660b57cec5SDimitry Andric return true;
670b57cec5SDimitry Andric }
680b57cec5SDimitry Andric
isALUArithLoOpcode(unsigned Opcode)690b57cec5SDimitry Andric static bool isALUArithLoOpcode(unsigned Opcode) {
700b57cec5SDimitry Andric switch (Opcode) {
710b57cec5SDimitry Andric case Lanai::ADD_I_LO:
720b57cec5SDimitry Andric case Lanai::SUB_I_LO:
730b57cec5SDimitry Andric case Lanai::ADD_F_I_LO:
740b57cec5SDimitry Andric case Lanai::SUB_F_I_LO:
750b57cec5SDimitry Andric case Lanai::ADDC_I_LO:
760b57cec5SDimitry Andric case Lanai::SUBB_I_LO:
770b57cec5SDimitry Andric case Lanai::ADDC_F_I_LO:
780b57cec5SDimitry Andric case Lanai::SUBB_F_I_LO:
790b57cec5SDimitry Andric return true;
800b57cec5SDimitry Andric default:
810b57cec5SDimitry Andric return false;
820b57cec5SDimitry Andric }
830b57cec5SDimitry Andric }
840b57cec5SDimitry Andric
getOppositeALULoOpcode(unsigned Opcode)850b57cec5SDimitry Andric static unsigned getOppositeALULoOpcode(unsigned Opcode) {
860b57cec5SDimitry Andric switch (Opcode) {
870b57cec5SDimitry Andric case Lanai::ADD_I_LO:
880b57cec5SDimitry Andric return Lanai::SUB_I_LO;
890b57cec5SDimitry Andric case Lanai::SUB_I_LO:
900b57cec5SDimitry Andric return Lanai::ADD_I_LO;
910b57cec5SDimitry Andric case Lanai::ADD_F_I_LO:
920b57cec5SDimitry Andric return Lanai::SUB_F_I_LO;
930b57cec5SDimitry Andric case Lanai::SUB_F_I_LO:
940b57cec5SDimitry Andric return Lanai::ADD_F_I_LO;
950b57cec5SDimitry Andric case Lanai::ADDC_I_LO:
960b57cec5SDimitry Andric return Lanai::SUBB_I_LO;
970b57cec5SDimitry Andric case Lanai::SUBB_I_LO:
980b57cec5SDimitry Andric return Lanai::ADDC_I_LO;
990b57cec5SDimitry Andric case Lanai::ADDC_F_I_LO:
1000b57cec5SDimitry Andric return Lanai::SUBB_F_I_LO;
1010b57cec5SDimitry Andric case Lanai::SUBB_F_I_LO:
1020b57cec5SDimitry Andric return Lanai::ADDC_F_I_LO;
1030b57cec5SDimitry Andric default:
1040b57cec5SDimitry Andric llvm_unreachable("Invalid ALU lo opcode");
1050b57cec5SDimitry Andric }
1060b57cec5SDimitry Andric }
1070b57cec5SDimitry Andric
getRRMOpcodeVariant(unsigned Opcode)1080b57cec5SDimitry Andric static unsigned getRRMOpcodeVariant(unsigned Opcode) {
1090b57cec5SDimitry Andric switch (Opcode) {
1100b57cec5SDimitry Andric case Lanai::LDBs_RI:
1110b57cec5SDimitry Andric return Lanai::LDBs_RR;
1120b57cec5SDimitry Andric case Lanai::LDBz_RI:
1130b57cec5SDimitry Andric return Lanai::LDBz_RR;
1140b57cec5SDimitry Andric case Lanai::LDHs_RI:
1150b57cec5SDimitry Andric return Lanai::LDHs_RR;
1160b57cec5SDimitry Andric case Lanai::LDHz_RI:
1170b57cec5SDimitry Andric return Lanai::LDHz_RR;
1180b57cec5SDimitry Andric case Lanai::LDW_RI:
1190b57cec5SDimitry Andric return Lanai::LDW_RR;
1200b57cec5SDimitry Andric case Lanai::STB_RI:
1210b57cec5SDimitry Andric return Lanai::STB_RR;
1220b57cec5SDimitry Andric case Lanai::STH_RI:
1230b57cec5SDimitry Andric return Lanai::STH_RR;
1240b57cec5SDimitry Andric case Lanai::SW_RI:
1250b57cec5SDimitry Andric return Lanai::SW_RR;
1260b57cec5SDimitry Andric default:
1270b57cec5SDimitry Andric llvm_unreachable("Opcode has no RRM variant");
1280b57cec5SDimitry Andric }
1290b57cec5SDimitry Andric }
1300b57cec5SDimitry Andric
eliminateFrameIndex(MachineBasicBlock::iterator II,int SPAdj,unsigned FIOperandNum,RegScavenger * RS) const131bdd1243dSDimitry Andric bool LanaiRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1320b57cec5SDimitry Andric int SPAdj, unsigned FIOperandNum,
1330b57cec5SDimitry Andric RegScavenger *RS) const {
1340b57cec5SDimitry Andric assert(SPAdj == 0 && "Unexpected");
1350b57cec5SDimitry Andric
1360b57cec5SDimitry Andric MachineInstr &MI = *II;
1370b57cec5SDimitry Andric MachineFunction &MF = *MI.getParent()->getParent();
1380b57cec5SDimitry Andric const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
1390b57cec5SDimitry Andric const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
1400b57cec5SDimitry Andric bool HasFP = TFI->hasFP(MF);
1410b57cec5SDimitry Andric DebugLoc DL = MI.getDebugLoc();
1420b57cec5SDimitry Andric
1430b57cec5SDimitry Andric int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
1440b57cec5SDimitry Andric
1450b57cec5SDimitry Andric int Offset = MF.getFrameInfo().getObjectOffset(FrameIndex) +
1460b57cec5SDimitry Andric MI.getOperand(FIOperandNum + 1).getImm();
1470b57cec5SDimitry Andric
1480b57cec5SDimitry Andric // Addressable stack objects are addressed using neg. offsets from fp
1490b57cec5SDimitry Andric // or pos. offsets from sp/basepointer
150fe6060f1SDimitry Andric if (!HasFP || (hasStackRealignment(MF) && FrameIndex >= 0))
1510b57cec5SDimitry Andric Offset += MF.getFrameInfo().getStackSize();
1520b57cec5SDimitry Andric
1538bcb0991SDimitry Andric Register FrameReg = getFrameRegister(MF);
1540b57cec5SDimitry Andric if (FrameIndex >= 0) {
1550b57cec5SDimitry Andric if (hasBasePointer(MF))
1560b57cec5SDimitry Andric FrameReg = getBaseRegister();
157fe6060f1SDimitry Andric else if (hasStackRealignment(MF))
1580b57cec5SDimitry Andric FrameReg = Lanai::SP;
1590b57cec5SDimitry Andric }
1600b57cec5SDimitry Andric
1610b57cec5SDimitry Andric // Replace frame index with a frame pointer reference.
1620b57cec5SDimitry Andric // If the offset is small enough to fit in the immediate field, directly
1630b57cec5SDimitry Andric // encode it.
1640b57cec5SDimitry Andric // Otherwise scavenge a register and encode it into a MOVHI, OR_I_LO sequence.
1650b57cec5SDimitry Andric if ((isSPLSOpcode(MI.getOpcode()) && !isInt<10>(Offset)) ||
1660b57cec5SDimitry Andric !isInt<16>(Offset)) {
1670b57cec5SDimitry Andric assert(RS && "Register scavenging must be on");
16804eeddc0SDimitry Andric Register Reg = RS->FindUnusedReg(&Lanai::GPRRegClass);
1690b57cec5SDimitry Andric if (!Reg)
17006c3fb27SDimitry Andric Reg = RS->scavengeRegisterBackwards(Lanai::GPRRegClass, II, false, SPAdj);
1710b57cec5SDimitry Andric assert(Reg && "Register scavenger failed");
1720b57cec5SDimitry Andric
1730b57cec5SDimitry Andric bool HasNegOffset = false;
1740b57cec5SDimitry Andric // ALU ops have unsigned immediate values. If the Offset is negative, we
1750b57cec5SDimitry Andric // negate it here and reverse the opcode later.
1760b57cec5SDimitry Andric if (Offset < 0) {
1770b57cec5SDimitry Andric HasNegOffset = true;
1780b57cec5SDimitry Andric Offset = -Offset;
1790b57cec5SDimitry Andric }
1800b57cec5SDimitry Andric
1810b57cec5SDimitry Andric if (!isInt<16>(Offset)) {
1820b57cec5SDimitry Andric // Reg = hi(offset) | lo(offset)
1830b57cec5SDimitry Andric BuildMI(*MI.getParent(), II, DL, TII->get(Lanai::MOVHI), Reg)
1840b57cec5SDimitry Andric .addImm(static_cast<uint32_t>(Offset) >> 16);
1850b57cec5SDimitry Andric BuildMI(*MI.getParent(), II, DL, TII->get(Lanai::OR_I_LO), Reg)
1860b57cec5SDimitry Andric .addReg(Reg)
1870b57cec5SDimitry Andric .addImm(Offset & 0xffffU);
1880b57cec5SDimitry Andric } else {
1890b57cec5SDimitry Andric // Reg = mov(offset)
1900b57cec5SDimitry Andric BuildMI(*MI.getParent(), II, DL, TII->get(Lanai::ADD_I_LO), Reg)
1910b57cec5SDimitry Andric .addImm(0)
1920b57cec5SDimitry Andric .addImm(Offset);
1930b57cec5SDimitry Andric }
1940b57cec5SDimitry Andric // Reg = FrameReg OP Reg
1950b57cec5SDimitry Andric if (MI.getOpcode() == Lanai::ADD_I_LO) {
1960b57cec5SDimitry Andric BuildMI(*MI.getParent(), II, DL,
1970b57cec5SDimitry Andric HasNegOffset ? TII->get(Lanai::SUB_R) : TII->get(Lanai::ADD_R),
1980b57cec5SDimitry Andric MI.getOperand(0).getReg())
1990b57cec5SDimitry Andric .addReg(FrameReg)
2000b57cec5SDimitry Andric .addReg(Reg)
2010b57cec5SDimitry Andric .addImm(LPCC::ICC_T);
2020b57cec5SDimitry Andric MI.eraseFromParent();
203bdd1243dSDimitry Andric return true;
2040b57cec5SDimitry Andric }
2050b57cec5SDimitry Andric if (isSPLSOpcode(MI.getOpcode()) || isRMOpcode(MI.getOpcode())) {
2060b57cec5SDimitry Andric MI.setDesc(TII->get(getRRMOpcodeVariant(MI.getOpcode())));
2070b57cec5SDimitry Andric if (HasNegOffset) {
2080b57cec5SDimitry Andric // Change the ALU op (operand 3) from LPAC::ADD (the default) to
2090b57cec5SDimitry Andric // LPAC::SUB with the already negated offset.
2100b57cec5SDimitry Andric assert((MI.getOperand(3).getImm() == LPAC::ADD) &&
2110b57cec5SDimitry Andric "Unexpected ALU op in RRM instruction");
2120b57cec5SDimitry Andric MI.getOperand(3).setImm(LPAC::SUB);
2130b57cec5SDimitry Andric }
2140b57cec5SDimitry Andric } else
2150b57cec5SDimitry Andric llvm_unreachable("Unexpected opcode in frame index operation");
2160b57cec5SDimitry Andric
2170b57cec5SDimitry Andric MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, /*isDef=*/false);
2180b57cec5SDimitry Andric MI.getOperand(FIOperandNum + 1)
2190b57cec5SDimitry Andric .ChangeToRegister(Reg, /*isDef=*/false, /*isImp=*/false,
2200b57cec5SDimitry Andric /*isKill=*/true);
221bdd1243dSDimitry Andric return false;
2220b57cec5SDimitry Andric }
2230b57cec5SDimitry Andric
2240b57cec5SDimitry Andric // ALU arithmetic ops take unsigned immediates. If the offset is negative,
2250b57cec5SDimitry Andric // we replace the instruction with one that inverts the opcode and negates
2260b57cec5SDimitry Andric // the immediate.
2270b57cec5SDimitry Andric if ((Offset < 0) && isALUArithLoOpcode(MI.getOpcode())) {
2280b57cec5SDimitry Andric unsigned NewOpcode = getOppositeALULoOpcode(MI.getOpcode());
2290b57cec5SDimitry Andric // We know this is an ALU op, so we know the operands are as follows:
2300b57cec5SDimitry Andric // 0: destination register
2310b57cec5SDimitry Andric // 1: source register (frame register)
2320b57cec5SDimitry Andric // 2: immediate
2330b57cec5SDimitry Andric BuildMI(*MI.getParent(), II, DL, TII->get(NewOpcode),
2340b57cec5SDimitry Andric MI.getOperand(0).getReg())
2350b57cec5SDimitry Andric .addReg(FrameReg)
2360b57cec5SDimitry Andric .addImm(-Offset);
2370b57cec5SDimitry Andric MI.eraseFromParent();
23806c3fb27SDimitry Andric return true;
23906c3fb27SDimitry Andric }
24006c3fb27SDimitry Andric
2410b57cec5SDimitry Andric MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, /*isDef=*/false);
2420b57cec5SDimitry Andric MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
243bdd1243dSDimitry Andric return false;
2440b57cec5SDimitry Andric }
2450b57cec5SDimitry Andric
hasBasePointer(const MachineFunction & MF) const2460b57cec5SDimitry Andric bool LanaiRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
2470b57cec5SDimitry Andric const MachineFrameInfo &MFI = MF.getFrameInfo();
2480b57cec5SDimitry Andric // When we need stack realignment and there are dynamic allocas, we can't
2490b57cec5SDimitry Andric // reference off of the stack pointer, so we reserve a base pointer.
250fe6060f1SDimitry Andric if (hasStackRealignment(MF) && MFI.hasVarSizedObjects())
2510b57cec5SDimitry Andric return true;
2520b57cec5SDimitry Andric
2530b57cec5SDimitry Andric return false;
2540b57cec5SDimitry Andric }
2550b57cec5SDimitry Andric
getRARegister() const2560b57cec5SDimitry Andric unsigned LanaiRegisterInfo::getRARegister() const { return Lanai::RCA; }
2570b57cec5SDimitry Andric
2580b57cec5SDimitry Andric Register
getFrameRegister(const MachineFunction &) const2590b57cec5SDimitry Andric LanaiRegisterInfo::getFrameRegister(const MachineFunction & /*MF*/) const {
2600b57cec5SDimitry Andric return Lanai::FP;
2610b57cec5SDimitry Andric }
2620b57cec5SDimitry Andric
getBaseRegister() const2630b57cec5SDimitry Andric Register LanaiRegisterInfo::getBaseRegister() const { return Lanai::R14; }
2640b57cec5SDimitry Andric
2650b57cec5SDimitry Andric const uint32_t *
getCallPreservedMask(const MachineFunction &,CallingConv::ID) const2660b57cec5SDimitry Andric LanaiRegisterInfo::getCallPreservedMask(const MachineFunction & /*MF*/,
2670b57cec5SDimitry Andric CallingConv::ID /*CC*/) const {
2680b57cec5SDimitry Andric return CSR_RegMask;
2690b57cec5SDimitry Andric }
270