1// LoongArchFloat32InstrInfo.td - Single-Precision Float instr --*- tablegen -*-
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the baisc single-precision floating-point instructions.
10//
11//===----------------------------------------------------------------------===//
12
13//===----------------------------------------------------------------------===//
14// LoongArch specific DAG Nodes.
15//===----------------------------------------------------------------------===//
16
17def SDT_LoongArchMOVGR2FR_W_LA64
18    : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisVT<1, i64>]>;
19def SDT_LoongArchMOVFR2GR_S_LA64
20    : SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, f32>]>;
21def SDT_LoongArchFTINT : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>;
22
23def loongarch_movgr2fr_w_la64
24    : SDNode<"LoongArchISD::MOVGR2FR_W_LA64", SDT_LoongArchMOVGR2FR_W_LA64>;
25def loongarch_movfr2gr_s_la64
26    : SDNode<"LoongArchISD::MOVFR2GR_S_LA64", SDT_LoongArchMOVFR2GR_S_LA64>;
27def loongarch_ftint : SDNode<"LoongArchISD::FTINT", SDT_LoongArchFTINT>;
28
29//===----------------------------------------------------------------------===//
30// Instructions
31//===----------------------------------------------------------------------===//
32
33let Predicates = [HasBasicF] in {
34
35// Arithmetic Operation Instructions
36def FADD_S : FP_ALU_3R<0x01008000>;
37def FSUB_S : FP_ALU_3R<0x01028000>;
38def FMUL_S : FP_ALU_3R<0x01048000>;
39def FDIV_S : FP_ALU_3R<0x01068000>;
40def FMADD_S  : FP_ALU_4R<0x08100000>;
41def FMSUB_S  : FP_ALU_4R<0x08500000>;
42def FNMADD_S : FP_ALU_4R<0x08900000>;
43def FNMSUB_S : FP_ALU_4R<0x08d00000>;
44def FMAX_S  : FP_ALU_3R<0x01088000>;
45def FMIN_S  : FP_ALU_3R<0x010a8000>;
46def FMAXA_S : FP_ALU_3R<0x010c8000>;
47def FMINA_S : FP_ALU_3R<0x010e8000>;
48def FABS_S   : FP_ALU_2R<0x01140400>;
49def FNEG_S   : FP_ALU_2R<0x01141400>;
50def FSQRT_S  : FP_ALU_2R<0x01144400>;
51def FRECIP_S : FP_ALU_2R<0x01145400>;
52def FRSQRT_S : FP_ALU_2R<0x01146400>;
53def FRECIPE_S : FP_ALU_2R<0x01147400>;
54def FRSQRTE_S : FP_ALU_2R<0x01148400>;
55def FSCALEB_S : FP_ALU_3R<0x01108000>;
56def FLOGB_S   : FP_ALU_2R<0x01142400>;
57def FCOPYSIGN_S : FP_ALU_3R<0x01128000>;
58def FCLASS_S  : FP_ALU_2R<0x01143400>;
59
60
61// Comparison Instructions
62def FCMP_CAF_S  : FP_CMP<0x0c100000>;
63def FCMP_CUN_S  : FP_CMP<0x0c140000>;
64def FCMP_CEQ_S  : FP_CMP<0x0c120000>;
65def FCMP_CUEQ_S : FP_CMP<0x0c160000>;
66def FCMP_CLT_S  : FP_CMP<0x0c110000>;
67def FCMP_CULT_S : FP_CMP<0x0c150000>;
68def FCMP_CLE_S  : FP_CMP<0x0c130000>;
69def FCMP_CULE_S : FP_CMP<0x0c170000>;
70def FCMP_CNE_S  : FP_CMP<0x0c180000>;
71def FCMP_COR_S  : FP_CMP<0x0c1a0000>;
72def FCMP_CUNE_S : FP_CMP<0x0c1c0000>;
73def FCMP_SAF_S  : FP_CMP<0x0c108000>;
74def FCMP_SUN_S  : FP_CMP<0x0c148000>;
75def FCMP_SEQ_S  : FP_CMP<0x0c128000>;
76def FCMP_SUEQ_S : FP_CMP<0x0c168000>;
77def FCMP_SLT_S  : FP_CMP<0x0c118000>;
78def FCMP_SULT_S : FP_CMP<0x0c158000>;
79def FCMP_SLE_S  : FP_CMP<0x0c138000>;
80def FCMP_SULE_S : FP_CMP<0x0c178000>;
81def FCMP_SNE_S  : FP_CMP<0x0c188000>;
82def FCMP_SOR_S  : FP_CMP<0x0c1a8000>;
83def FCMP_SUNE_S : FP_CMP<0x0c1c8000>;
84
85// Conversion Instructions
86def FFINT_S_W    : FP_CONV<0x011d1000>;
87def FTINT_W_S    : FP_CONV<0x011b0400>;
88def FTINTRM_W_S  : FP_CONV<0x011a0400>;
89def FTINTRP_W_S  : FP_CONV<0x011a4400>;
90def FTINTRZ_W_S  : FP_CONV<0x011a8400>;
91def FTINTRNE_W_S : FP_CONV<0x011ac400>;
92def FRINT_S      : FP_CONV<0x011e4400>;
93
94// Move Instructions
95def FSEL_xS    : FP_SEL<0x0d000000>;
96def FMOV_S     : FP_MOV<0x01149400>;
97def MOVGR2FR_W : FP_MOV<0x0114a400, FPR32, GPR>;
98def MOVFR2GR_S : FP_MOV<0x0114b400, GPR, FPR32>;
99let hasSideEffects = 1 in {
100def MOVGR2FCSR : FP_MOV<0x0114c000, FCSR, GPR>;
101def MOVFCSR2GR : FP_MOV<0x0114c800, GPR, FCSR>;
102} // hasSideEffects = 1
103def MOVFR2CF_xS : FP_MOV<0x0114d000, CFR, FPR32>;
104def MOVCF2FR_xS : FP_MOV<0x0114d400, FPR32, CFR>;
105def MOVGR2CF    : FP_MOV<0x0114d800, CFR, GPR>;
106def MOVCF2GR    : FP_MOV<0x0114dc00, GPR, CFR>;
107
108// Branch Instructions
109def BCEQZ : FP_BRANCH<0x48000000>;
110def BCNEZ : FP_BRANCH<0x48000100>;
111
112// Common Memory Access Instructions
113def FLD_S : FP_LOAD_2RI12<0x2b000000>;
114def FST_S : FP_STORE_2RI12<0x2b400000>;
115def FLDX_S : FP_LOAD_3R<0x38300000>;
116def FSTX_S : FP_STORE_3R<0x38380000>;
117
118// Bound Check Memory Access Instructions
119def FLDGT_S : FP_LOAD_3R<0x38740000>;
120def FLDLE_S : FP_LOAD_3R<0x38750000>;
121def FSTGT_S : FP_STORE_3R<0x38760000>;
122def FSTLE_S : FP_STORE_3R<0x38770000>;
123
124// Pseudo instructions for spill/reload CFRs.
125let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
126def PseudoST_CFR : Pseudo<(outs),
127                          (ins CFR:$ccd, GPR:$rj, grlenimm:$imm)>;
128let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
129def PseudoLD_CFR : Pseudo<(outs CFR:$ccd),
130                          (ins GPR:$rj, grlenimm:$imm)>;
131
132// SET_CFR_{FALSE,TRUE}
133// These instructions are defined in order to avoid expensive check error if
134// regular instruction patterns are used.
135// fcmp.caf.s $dst, $fa0, $fa0
136def SET_CFR_FALSE : SET_CFR<0x0c100000, "fcmp.caf.s">;
137// fcmp.cueq.s $dst, $fa0, $fa0
138def SET_CFR_TRUE  : SET_CFR<0x0c160000, "fcmp.cueq.s">;
139
140// Pseudo instruction for copying CFRs.
141def PseudoCopyCFR : Pseudo<(outs CFR:$dst), (ins CFR:$src)> {
142  let mayLoad = 0;
143  let mayStore = 0;
144  let hasSideEffects = 0;
145  let Size = 12;
146}
147
148} // Predicates = [HasBasicF]
149
150//===----------------------------------------------------------------------===//
151// Pseudo-instructions and codegen patterns
152//===----------------------------------------------------------------------===//
153
154/// Generic pattern classes
155
156class PatFpr<SDPatternOperator OpNode, LAInst Inst, RegisterClass RegTy>
157    : Pat<(OpNode RegTy:$fj), (Inst $fj)>;
158class PatFprFpr<SDPatternOperator OpNode, LAInst Inst, RegisterClass RegTy>
159    : Pat<(OpNode RegTy:$fj, RegTy:$fk), (Inst $fj, $fk)>;
160
161let Predicates = [HasBasicF] in {
162
163/// Float arithmetic operations
164
165def : PatFprFpr<fadd, FADD_S, FPR32>;
166def : PatFprFpr<fsub, FSUB_S, FPR32>;
167def : PatFprFpr<fmul, FMUL_S, FPR32>;
168def : PatFprFpr<fdiv, FDIV_S, FPR32>;
169def : PatFprFpr<fcopysign, FCOPYSIGN_S, FPR32>;
170def : PatFprFpr<fmaxnum_ieee, FMAX_S, FPR32>;
171def : PatFprFpr<fminnum_ieee, FMIN_S, FPR32>;
172def : PatFpr<fneg, FNEG_S, FPR32>;
173def : PatFpr<fabs, FABS_S, FPR32>;
174def : PatFpr<fsqrt, FSQRT_S, FPR32>;
175def : Pat<(fdiv fpimm1, (fsqrt FPR32:$fj)), (FRSQRT_S FPR32:$fj)>;
176def : Pat<(fcanonicalize FPR32:$fj), (FMAX_S $fj, $fj)>;
177def : Pat<(is_fpclass FPR32:$fj, (i32 timm:$mask)),
178          (SLTU R0, (ANDI (MOVFR2GR_S (FCLASS_S FPR32:$fj)),
179                          (to_fclass_mask timm:$mask)))>;
180
181/// Setcc
182
183// Match non-signaling comparison
184
185class PatFPSetcc<CondCode cc, LAInst CmpInst, RegisterClass RegTy>
186    : Pat<(any_fsetcc RegTy:$fj, RegTy:$fk, cc),
187          (CmpInst RegTy:$fj, RegTy:$fk)>;
188// SETOGT/SETOGE/SETUGT/SETUGE/SETGE/SETNE/SETGT will expand into
189// SETOLT/SETOLE/SETULT/SETULE/SETLE/SETEQ/SETLT.
190def : PatFPSetcc<SETOEQ, FCMP_CEQ_S,  FPR32>;
191def : PatFPSetcc<SETEQ,  FCMP_CEQ_S,  FPR32>;
192def : PatFPSetcc<SETOLT, FCMP_CLT_S,  FPR32>;
193def : PatFPSetcc<SETOLE, FCMP_CLE_S,  FPR32>;
194def : PatFPSetcc<SETLE,  FCMP_CLE_S,  FPR32>;
195def : PatFPSetcc<SETONE, FCMP_CNE_S,  FPR32>;
196def : PatFPSetcc<SETO,   FCMP_COR_S,  FPR32>;
197def : PatFPSetcc<SETUEQ, FCMP_CUEQ_S, FPR32>;
198def : PatFPSetcc<SETULT, FCMP_CULT_S, FPR32>;
199def : PatFPSetcc<SETULE, FCMP_CULE_S, FPR32>;
200def : PatFPSetcc<SETUNE, FCMP_CUNE_S, FPR32>;
201def : PatFPSetcc<SETUO,  FCMP_CUN_S,  FPR32>;
202def : PatFPSetcc<SETLT,  FCMP_CLT_S,  FPR32>;
203
204multiclass PatFPBrcond<CondCode cc, LAInst CmpInst, RegisterClass RegTy> {
205  def : Pat<(brcond (xor (GRLenVT (setcc RegTy:$fj, RegTy:$fk, cc)), -1),
206                     bb:$imm21),
207            (BCEQZ (CmpInst RegTy:$fj, RegTy:$fk), bb:$imm21)>;
208  def : Pat<(brcond (GRLenVT (setcc RegTy:$fj, RegTy:$fk, cc)), bb:$imm21),
209            (BCNEZ (CmpInst RegTy:$fj, RegTy:$fk), bb:$imm21)>;
210}
211
212defm : PatFPBrcond<SETOEQ, FCMP_CEQ_S, FPR32>;
213defm : PatFPBrcond<SETOLT, FCMP_CLT_S, FPR32>;
214defm : PatFPBrcond<SETOLE, FCMP_CLE_S, FPR32>;
215defm : PatFPBrcond<SETONE, FCMP_CNE_S, FPR32>;
216defm : PatFPBrcond<SETO,   FCMP_COR_S, FPR32>;
217defm : PatFPBrcond<SETUEQ, FCMP_CUEQ_S, FPR32>;
218defm : PatFPBrcond<SETULT, FCMP_CULT_S, FPR32>;
219defm : PatFPBrcond<SETULE, FCMP_CULE_S, FPR32>;
220defm : PatFPBrcond<SETUNE, FCMP_CUNE_S, FPR32>;
221defm : PatFPBrcond<SETUO,  FCMP_CUN_S, FPR32>;
222defm : PatFPBrcond<SETLT,  FCMP_CLT_S, FPR32>;
223
224// Match signaling comparison
225
226class PatStrictFsetccs<CondCode cc, LAInst CmpInst, RegisterClass RegTy>
227    : Pat<(strict_fsetccs RegTy:$fj, RegTy:$fk, cc),
228          (CmpInst RegTy:$fj, RegTy:$fk)>;
229def : PatStrictFsetccs<SETOEQ, FCMP_SEQ_S,  FPR32>;
230def : PatStrictFsetccs<SETOLT, FCMP_SLT_S,  FPR32>;
231def : PatStrictFsetccs<SETOLE, FCMP_SLE_S,  FPR32>;
232def : PatStrictFsetccs<SETONE, FCMP_SNE_S,  FPR32>;
233def : PatStrictFsetccs<SETO,   FCMP_SOR_S,  FPR32>;
234def : PatStrictFsetccs<SETUEQ, FCMP_SUEQ_S, FPR32>;
235def : PatStrictFsetccs<SETULT, FCMP_SULT_S, FPR32>;
236def : PatStrictFsetccs<SETULE, FCMP_SULE_S, FPR32>;
237def : PatStrictFsetccs<SETUNE, FCMP_SUNE_S, FPR32>;
238def : PatStrictFsetccs<SETUO,  FCMP_SUN_S,  FPR32>;
239def : PatStrictFsetccs<SETLT,  FCMP_SLT_S,  FPR32>;
240
241/// Select
242
243def : Pat<(select CFR:$cc, FPR32:$fk, FPR32:$fj),
244          (FSEL_xS FPR32:$fj, FPR32:$fk, CFR:$cc)>;
245
246/// Selectcc
247
248class PatFPSelectcc<CondCode cc, LAInst CmpInst, LAInst SelInst,
249                    RegisterClass RegTy>
250    : Pat<(select (GRLenVT (setcc RegTy:$a, RegTy:$b, cc)), RegTy:$t, RegTy:$f),
251          (SelInst RegTy:$f, RegTy:$t, (CmpInst RegTy:$a, RegTy:$b))>;
252def : PatFPSelectcc<SETOEQ, FCMP_CEQ_S,  FSEL_xS, FPR32>;
253def : PatFPSelectcc<SETOLT, FCMP_CLT_S,  FSEL_xS, FPR32>;
254def : PatFPSelectcc<SETOLE, FCMP_CLE_S,  FSEL_xS, FPR32>;
255def : PatFPSelectcc<SETONE, FCMP_CNE_S,  FSEL_xS, FPR32>;
256def : PatFPSelectcc<SETO,   FCMP_COR_S,  FSEL_xS, FPR32>;
257def : PatFPSelectcc<SETUEQ, FCMP_CUEQ_S, FSEL_xS, FPR32>;
258def : PatFPSelectcc<SETULT, FCMP_CULT_S, FSEL_xS, FPR32>;
259def : PatFPSelectcc<SETULE, FCMP_CULE_S, FSEL_xS, FPR32>;
260def : PatFPSelectcc<SETUNE, FCMP_CUNE_S, FSEL_xS, FPR32>;
261def : PatFPSelectcc<SETUO,  FCMP_CUN_S,  FSEL_xS, FPR32>;
262
263/// Loads
264
265defm : LdPat<load, FLD_S, f32>;
266def : RegRegLdPat<load, FLDX_S, f32>;
267
268/// Stores
269
270defm : StPat<store, FST_S, FPR32, f32>;
271def : RegRegStPat<store, FSTX_S, FPR32, f32>;
272
273/// Floating point constants
274
275def : Pat<(f32 fpimm0), (MOVGR2FR_W R0)>;
276def : Pat<(f32 fpimm0neg), (FNEG_S (MOVGR2FR_W R0))>;
277def : Pat<(f32 fpimm1), (FFINT_S_W (MOVGR2FR_W (ADDI_W R0, 1)))>;
278
279// FP Conversion
280def : Pat<(loongarch_ftint FPR32:$src), (FTINTRZ_W_S FPR32:$src)>;
281
282// FP reciprocal operation
283def : Pat<(fdiv fpimm1, FPR32:$src), (FRECIP_S $src)>;
284
285let Predicates = [HasFrecipe] in {
286// FP approximate reciprocal operation
287def : Pat<(int_loongarch_frecipe_s FPR32:$src), (FRECIPE_S FPR32:$src)>;
288def : Pat<(int_loongarch_frsqrte_s FPR32:$src), (FRSQRTE_S FPR32:$src)>;
289}
290
291// fmadd.s: fj * fk + fa
292def : Pat<(fma FPR32:$fj, FPR32:$fk, FPR32:$fa), (FMADD_S $fj, $fk, $fa)>;
293
294// fmsub.s: fj * fk - fa
295def : Pat<(fma FPR32:$fj, FPR32:$fk, (fneg FPR32:$fa)),
296          (FMSUB_S FPR32:$fj, FPR32:$fk, FPR32:$fa)>;
297
298// fnmadd.s: -(fj * fk + fa)
299def : Pat<(fneg (fma FPR32:$fj, FPR32:$fk, FPR32:$fa)),
300          (FNMADD_S FPR32:$fj, FPR32:$fk, FPR32:$fa)>;
301
302// fnmadd.s: -fj * fk - fa (the nsz flag on the FMA)
303def : Pat<(fma_nsz (fneg FPR32:$fj), FPR32:$fk, (fneg FPR32:$fa)),
304          (FNMADD_S FPR32:$fj, FPR32:$fk, FPR32:$fa)>;
305
306// fnmsub.s: -(fj * fk - fa)
307def : Pat<(fneg (fma FPR32:$fj, FPR32:$fk, (fneg FPR32:$fa))),
308          (FNMSUB_S FPR32:$fj, FPR32:$fk, FPR32:$fa)>;
309
310// fnmsub.s: -fj * fk + fa (the nsz flag on the FMA)
311def : Pat<(fma_nsz (fneg FPR32:$fj), FPR32:$fk, FPR32:$fa),
312          (FNMSUB_S FPR32:$fj, FPR32:$fk, FPR32:$fa)>;
313} // Predicates = [HasBasicF]
314
315let Predicates = [HasBasicF, IsLA64] in {
316// GPR -> FPR
317def : Pat<(loongarch_movgr2fr_w_la64 GPR:$src), (MOVGR2FR_W GPR:$src)>;
318// FPR -> GPR
319def : Pat<(loongarch_movfr2gr_s_la64 FPR32:$src),
320          (MOVFR2GR_S FPR32:$src)>;
321// int -> f32
322def : Pat<(f32 (sint_to_fp (i64 (sexti32 (i64 GPR:$src))))),
323          (FFINT_S_W (MOVGR2FR_W GPR:$src))>;
324// uint -> f32
325def : Pat<(f32 (uint_to_fp (i64 (sexti32 (i64 GPR:$src))))),
326          (FFINT_S_W (MOVGR2FR_W GPR:$src))>;
327} // Predicates = [HasBasicF, IsLA64]
328
329// FP Rounding
330let Predicates = [HasBasicF, IsLA64] in {
331def : PatFpr<frint, FRINT_S, FPR32>;
332} // Predicates = [HasBasicF, IsLA64]
333
334let Predicates = [HasBasicF, IsLA32] in {
335// GPR -> FPR
336def : Pat<(bitconvert (i32 GPR:$src)), (MOVGR2FR_W GPR:$src)>;
337// FPR -> GPR
338def : Pat<(i32 (bitconvert FPR32:$src)), (MOVFR2GR_S FPR32:$src)>;
339// int -> f32
340def : Pat<(f32 (sint_to_fp (i32 GPR:$src))), (FFINT_S_W (MOVGR2FR_W GPR:$src))>;
341} // Predicates = [HasBasicF, IsLA32]
342