181ad6265SDimitry Andric//===- LoongArchInstrFormats.td - LoongArch Instr. Formats -*- tablegen -*-===// 281ad6265SDimitry Andric// 381ad6265SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 481ad6265SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 581ad6265SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 681ad6265SDimitry Andric// 781ad6265SDimitry Andric//===----------------------------------------------------------------------===// 881ad6265SDimitry Andric 981ad6265SDimitry Andric//===----------------------------------------------------------------------===// 1081ad6265SDimitry Andric// Describe LoongArch instructions format 1181ad6265SDimitry Andric// 1281ad6265SDimitry Andric// opcode - operation code. 1381ad6265SDimitry Andric// rd - destination register operand. 1481ad6265SDimitry Andric// r{j/k} - source register operand. 1581ad6265SDimitry Andric// immN - immediate data operand. 1681ad6265SDimitry Andric// 1781ad6265SDimitry Andric//===----------------------------------------------------------------------===// 1881ad6265SDimitry Andric 1981ad6265SDimitry Andricclass LAInst<dag outs, dag ins, string opcstr, string opnstr, 2081ad6265SDimitry Andric list<dag> pattern = []> 2181ad6265SDimitry Andric : Instruction { 2281ad6265SDimitry Andric field bits<32> Inst; 2381ad6265SDimitry Andric // SoftFail is a field the disassembler can use to provide a way for 2481ad6265SDimitry Andric // instructions to not match without killing the whole decode process. It is 2581ad6265SDimitry Andric // mainly used for ARM, but Tablegen expects this field to exist or it fails 2681ad6265SDimitry Andric // to build the decode table. 2781ad6265SDimitry Andric field bits<32> SoftFail = 0; 2881ad6265SDimitry Andric 2981ad6265SDimitry Andric let Namespace = "LoongArch"; 3081ad6265SDimitry Andric let Size = 4; 3181ad6265SDimitry Andric let OutOperandList = outs; 3281ad6265SDimitry Andric let InOperandList = ins; 3381ad6265SDimitry Andric let AsmString = opcstr # "\t" # opnstr; 3481ad6265SDimitry Andric let Pattern = pattern; 3581ad6265SDimitry Andric} 3681ad6265SDimitry Andric 3781ad6265SDimitry Andric// Pseudo instructions 3881ad6265SDimitry Andricclass Pseudo<dag outs, dag ins, list<dag> pattern = [], string opcstr = "", 3981ad6265SDimitry Andric string opnstr = ""> 4081ad6265SDimitry Andric : LAInst<outs, ins, opcstr, opnstr, pattern> { 4181ad6265SDimitry Andric let isPseudo = 1; 4281ad6265SDimitry Andric let isCodeGenOnly = 1; 4381ad6265SDimitry Andric} 4481ad6265SDimitry Andric 45*06c3fb27SDimitry Andricclass deriveInsnMnemonic<string name> { 46*06c3fb27SDimitry Andric string ret = !tolower(!subst("@", "_", !subst("_", ".", !subst("__", "@", name)))); 47*06c3fb27SDimitry Andric} 48*06c3fb27SDimitry Andric 4981ad6265SDimitry Andric// 2R-type 5081ad6265SDimitry Andric// <opcode | rj | rd> 51*06c3fb27SDimitry Andricclass Fmt2R<bits<32> op, dag outs, dag ins, string opnstr, 5281ad6265SDimitry Andric list<dag> pattern = []> 53*06c3fb27SDimitry Andric : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 5481ad6265SDimitry Andric bits<5> rj; 5581ad6265SDimitry Andric bits<5> rd; 5681ad6265SDimitry Andric 57*06c3fb27SDimitry Andric let Inst{31-0} = op; 5881ad6265SDimitry Andric let Inst{9-5} = rj; 5981ad6265SDimitry Andric let Inst{4-0} = rd; 6081ad6265SDimitry Andric} 6181ad6265SDimitry Andric 6281ad6265SDimitry Andric// 3R-type 6381ad6265SDimitry Andric// <opcode | rk | rj | rd> 64*06c3fb27SDimitry Andricclass Fmt3R<bits<32> op, dag outs, dag ins, string opnstr, 6581ad6265SDimitry Andric list<dag> pattern = []> 66*06c3fb27SDimitry Andric : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 6781ad6265SDimitry Andric bits<5> rk; 6881ad6265SDimitry Andric bits<5> rj; 6981ad6265SDimitry Andric bits<5> rd; 7081ad6265SDimitry Andric 71*06c3fb27SDimitry Andric let Inst{31-0} = op; 7281ad6265SDimitry Andric let Inst{14-10} = rk; 7381ad6265SDimitry Andric let Inst{9-5} = rj; 7481ad6265SDimitry Andric let Inst{4-0} = rd; 7581ad6265SDimitry Andric} 7681ad6265SDimitry Andric 7781ad6265SDimitry Andric// 3RI2-type 7881ad6265SDimitry Andric// <opcode | I2 | rk | rj | rd> 79*06c3fb27SDimitry Andricclass Fmt3RI2<bits<32> op, dag outs, dag ins, string opnstr, 8081ad6265SDimitry Andric list<dag> pattern = []> 81*06c3fb27SDimitry Andric : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 8281ad6265SDimitry Andric bits<2> imm2; 8381ad6265SDimitry Andric bits<5> rk; 8481ad6265SDimitry Andric bits<5> rj; 8581ad6265SDimitry Andric bits<5> rd; 8681ad6265SDimitry Andric 87*06c3fb27SDimitry Andric let Inst{31-0} = op; 8881ad6265SDimitry Andric let Inst{16-15} = imm2; 8981ad6265SDimitry Andric let Inst{14-10} = rk; 9081ad6265SDimitry Andric let Inst{9-5} = rj; 9181ad6265SDimitry Andric let Inst{4-0} = rd; 9281ad6265SDimitry Andric} 9381ad6265SDimitry Andric 9481ad6265SDimitry Andric// 3RI3-type 9581ad6265SDimitry Andric// <opcode | I3 | rk | rj | rd> 96*06c3fb27SDimitry Andricclass Fmt3RI3<bits<32> op, dag outs, dag ins, string opnstr, 9781ad6265SDimitry Andric list<dag> pattern = []> 98*06c3fb27SDimitry Andric : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 9981ad6265SDimitry Andric bits<3> imm3; 10081ad6265SDimitry Andric bits<5> rk; 10181ad6265SDimitry Andric bits<5> rj; 10281ad6265SDimitry Andric bits<5> rd; 10381ad6265SDimitry Andric 104*06c3fb27SDimitry Andric let Inst{31-0} = op; 10581ad6265SDimitry Andric let Inst{17-15} = imm3; 10681ad6265SDimitry Andric let Inst{14-10} = rk; 10781ad6265SDimitry Andric let Inst{9-5} = rj; 10881ad6265SDimitry Andric let Inst{4-0} = rd; 10981ad6265SDimitry Andric} 11081ad6265SDimitry Andric 11181ad6265SDimitry Andric// 2RI5-type 11281ad6265SDimitry Andric// <opcode | I5 | rj | rd> 113*06c3fb27SDimitry Andricclass Fmt2RI5<bits<32> op, dag outs, dag ins, string opnstr, 11481ad6265SDimitry Andric list<dag> pattern = []> 115*06c3fb27SDimitry Andric : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 11681ad6265SDimitry Andric bits<5> imm5; 11781ad6265SDimitry Andric bits<5> rj; 11881ad6265SDimitry Andric bits<5> rd; 11981ad6265SDimitry Andric 120*06c3fb27SDimitry Andric let Inst{31-0} = op; 12181ad6265SDimitry Andric let Inst{14-10} = imm5; 12281ad6265SDimitry Andric let Inst{9-5} = rj; 12381ad6265SDimitry Andric let Inst{4-0} = rd; 12481ad6265SDimitry Andric} 12581ad6265SDimitry Andric 12681ad6265SDimitry Andric// 2RI6-type 12781ad6265SDimitry Andric// <opcode | I6 | rj | rd> 128*06c3fb27SDimitry Andricclass Fmt2RI6<bits<32> op, dag outs, dag ins, string opnstr, 12981ad6265SDimitry Andric list<dag> pattern = []> 130*06c3fb27SDimitry Andric : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 13181ad6265SDimitry Andric bits<6> imm6; 13281ad6265SDimitry Andric bits<5> rj; 13381ad6265SDimitry Andric bits<5> rd; 13481ad6265SDimitry Andric 135*06c3fb27SDimitry Andric let Inst{31-0} = op; 13681ad6265SDimitry Andric let Inst{15-10} = imm6; 13781ad6265SDimitry Andric let Inst{9-5} = rj; 13881ad6265SDimitry Andric let Inst{4-0} = rd; 13981ad6265SDimitry Andric} 14081ad6265SDimitry Andric 14181ad6265SDimitry Andric// 2RI8-type 14281ad6265SDimitry Andric// <opcode | I8 | rj | rd> 143*06c3fb27SDimitry Andricclass Fmt2RI8<bits<32> op, dag outs, dag ins, string opnstr, 14481ad6265SDimitry Andric list<dag> pattern = []> 145*06c3fb27SDimitry Andric : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 14681ad6265SDimitry Andric bits<8> imm8; 14781ad6265SDimitry Andric bits<5> rj; 14881ad6265SDimitry Andric bits<5> rd; 14981ad6265SDimitry Andric 150*06c3fb27SDimitry Andric let Inst{31-0} = op; 15181ad6265SDimitry Andric let Inst{17-10} = imm8; 15281ad6265SDimitry Andric let Inst{9-5} = rj; 15381ad6265SDimitry Andric let Inst{4-0} = rd; 15481ad6265SDimitry Andric} 15581ad6265SDimitry Andric 15681ad6265SDimitry Andric// 2RI12-type 15781ad6265SDimitry Andric// <opcode | I12 | rj | rd> 158*06c3fb27SDimitry Andricclass Fmt2RI12<bits<32> op, dag outs, dag ins, string opnstr, 15981ad6265SDimitry Andric list<dag> pattern = []> 160*06c3fb27SDimitry Andric : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 16181ad6265SDimitry Andric bits<12> imm12; 16281ad6265SDimitry Andric bits<5> rj; 16381ad6265SDimitry Andric bits<5> rd; 16481ad6265SDimitry Andric 165*06c3fb27SDimitry Andric let Inst{31-0} = op; 16681ad6265SDimitry Andric let Inst{21-10} = imm12; 16781ad6265SDimitry Andric let Inst{9-5} = rj; 16881ad6265SDimitry Andric let Inst{4-0} = rd; 16981ad6265SDimitry Andric} 17081ad6265SDimitry Andric 17181ad6265SDimitry Andric// 2RI14-type 17281ad6265SDimitry Andric// <opcode | I14 | rj | rd> 173*06c3fb27SDimitry Andricclass Fmt2RI14<bits<32> op, dag outs, dag ins, string opnstr, 17481ad6265SDimitry Andric list<dag> pattern = []> 175*06c3fb27SDimitry Andric : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 17681ad6265SDimitry Andric bits<14> imm14; 17781ad6265SDimitry Andric bits<5> rj; 17881ad6265SDimitry Andric bits<5> rd; 17981ad6265SDimitry Andric 180*06c3fb27SDimitry Andric let Inst{31-0} = op; 18181ad6265SDimitry Andric let Inst{23-10} = imm14; 18281ad6265SDimitry Andric let Inst{9-5} = rj; 18381ad6265SDimitry Andric let Inst{4-0} = rd; 18481ad6265SDimitry Andric} 18581ad6265SDimitry Andric 18681ad6265SDimitry Andric// 2RI16-type 18781ad6265SDimitry Andric// <opcode | I16 | rj | rd> 188*06c3fb27SDimitry Andricclass Fmt2RI16<bits<32> op, dag outs, dag ins, string opnstr, 18981ad6265SDimitry Andric list<dag> pattern = []> 190*06c3fb27SDimitry Andric : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 19181ad6265SDimitry Andric bits<16> imm16; 19281ad6265SDimitry Andric bits<5> rj; 19381ad6265SDimitry Andric bits<5> rd; 19481ad6265SDimitry Andric 195*06c3fb27SDimitry Andric let Inst{31-0} = op; 19681ad6265SDimitry Andric let Inst{25-10} = imm16; 19781ad6265SDimitry Andric let Inst{9-5} = rj; 19881ad6265SDimitry Andric let Inst{4-0} = rd; 19981ad6265SDimitry Andric} 20081ad6265SDimitry Andric 20181ad6265SDimitry Andric// 1RI20-type 20281ad6265SDimitry Andric// <opcode | I20 | rd> 203*06c3fb27SDimitry Andricclass Fmt1RI20<bits<32> op, dag outs, dag ins, string opnstr, 20481ad6265SDimitry Andric list<dag> pattern = []> 205*06c3fb27SDimitry Andric : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 20681ad6265SDimitry Andric bits<20> imm20; 20781ad6265SDimitry Andric bits<5> rd; 20881ad6265SDimitry Andric 209*06c3fb27SDimitry Andric let Inst{31-0} = op; 21081ad6265SDimitry Andric let Inst{24-5} = imm20; 21181ad6265SDimitry Andric let Inst{4-0} = rd; 21281ad6265SDimitry Andric} 21381ad6265SDimitry Andric 21481ad6265SDimitry Andric// 1RI21-type 21581ad6265SDimitry Andric// <opcode | I21[15:0] | rj | I21[20:16]> 216*06c3fb27SDimitry Andricclass Fmt1RI21<bits<32> op, dag outs, dag ins, string opnstr, 21781ad6265SDimitry Andric list<dag> pattern = []> 218*06c3fb27SDimitry Andric : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 21981ad6265SDimitry Andric bits<21> imm21; 22081ad6265SDimitry Andric bits<5> rj; 22181ad6265SDimitry Andric 222*06c3fb27SDimitry Andric let Inst{31-0} = op; 22381ad6265SDimitry Andric let Inst{25-10} = imm21{15-0}; 22481ad6265SDimitry Andric let Inst{9-5} = rj; 22581ad6265SDimitry Andric let Inst{4-0} = imm21{20-16}; 22681ad6265SDimitry Andric} 22781ad6265SDimitry Andric 22881ad6265SDimitry Andric// I15-type 22981ad6265SDimitry Andric// <opcode | I15> 230*06c3fb27SDimitry Andricclass FmtI15<bits<32> op, dag outs, dag ins, string opnstr, 23181ad6265SDimitry Andric list<dag> pattern = []> 232*06c3fb27SDimitry Andric : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 23381ad6265SDimitry Andric bits<15> imm15; 23481ad6265SDimitry Andric 235*06c3fb27SDimitry Andric let Inst{31-0} = op; 23681ad6265SDimitry Andric let Inst{14-0} = imm15; 23781ad6265SDimitry Andric} 23881ad6265SDimitry Andric 23981ad6265SDimitry Andric// I26-type 24081ad6265SDimitry Andric// <opcode | I26[15:0] | I26[25:16]> 241*06c3fb27SDimitry Andricclass FmtI26<bits<32> op, dag outs, dag ins, string opnstr, 24281ad6265SDimitry Andric list<dag> pattern = []> 243*06c3fb27SDimitry Andric : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 24481ad6265SDimitry Andric bits<26> imm26; 24581ad6265SDimitry Andric 246*06c3fb27SDimitry Andric let Inst{31-0} = op; 24781ad6265SDimitry Andric let Inst{25-10} = imm26{15-0}; 24881ad6265SDimitry Andric let Inst{9-0} = imm26{25-16}; 24981ad6265SDimitry Andric} 25081ad6265SDimitry Andric 25181ad6265SDimitry Andric// FmtBSTR_W 252*06c3fb27SDimitry Andric// <opcode | msbw | lsbw | rj | rd> 253*06c3fb27SDimitry Andricclass FmtBSTR_W<bits<32> op, dag outs, dag ins, string opnstr, 25481ad6265SDimitry Andric list<dag> pattern = []> 255*06c3fb27SDimitry Andric : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 25681ad6265SDimitry Andric bits<5> msbw; 25781ad6265SDimitry Andric bits<5> lsbw; 25881ad6265SDimitry Andric bits<5> rj; 25981ad6265SDimitry Andric bits<5> rd; 26081ad6265SDimitry Andric 261*06c3fb27SDimitry Andric let Inst{31-0} = op; 26281ad6265SDimitry Andric let Inst{20-16} = msbw; 26381ad6265SDimitry Andric let Inst{14-10} = lsbw; 26481ad6265SDimitry Andric let Inst{9-5} = rj; 26581ad6265SDimitry Andric let Inst{4-0} = rd; 26681ad6265SDimitry Andric} 26781ad6265SDimitry Andric 26881ad6265SDimitry Andric// FmtBSTR_D 26981ad6265SDimitry Andric// <opcode | msbd | lsbd | rj | rd> 270*06c3fb27SDimitry Andricclass FmtBSTR_D<bits<32> op, dag outs, dag ins, string opnstr, 27181ad6265SDimitry Andric list<dag> pattern = []> 272*06c3fb27SDimitry Andric : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 27381ad6265SDimitry Andric bits<6> msbd; 27481ad6265SDimitry Andric bits<6> lsbd; 27581ad6265SDimitry Andric bits<5> rj; 27681ad6265SDimitry Andric bits<5> rd; 27781ad6265SDimitry Andric 278*06c3fb27SDimitry Andric let Inst{31-0} = op; 27981ad6265SDimitry Andric let Inst{21-16} = msbd; 28081ad6265SDimitry Andric let Inst{15-10} = lsbd; 28181ad6265SDimitry Andric let Inst{9-5} = rj; 28281ad6265SDimitry Andric let Inst{4-0} = rd; 28381ad6265SDimitry Andric} 28481ad6265SDimitry Andric 28581ad6265SDimitry Andric// FmtASRT 286*06c3fb27SDimitry Andric// <opcode | rk | rj> 287*06c3fb27SDimitry Andricclass FmtASRT<bits<32> op, dag outs, dag ins, string opnstr, 28881ad6265SDimitry Andric list<dag> pattern = []> 289*06c3fb27SDimitry Andric : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 29081ad6265SDimitry Andric bits<5> rk; 29181ad6265SDimitry Andric bits<5> rj; 29281ad6265SDimitry Andric 293*06c3fb27SDimitry Andric let Inst{31-0} = op; 29481ad6265SDimitry Andric let Inst{14-10} = rk; 29581ad6265SDimitry Andric let Inst{9-5} = rj; 29681ad6265SDimitry Andric} 29781ad6265SDimitry Andric 29881ad6265SDimitry Andric// FmtPRELD 29981ad6265SDimitry Andric// < 0b0010101011 | I12 | rj | I5> 300*06c3fb27SDimitry Andricclass FmtPRELD<dag outs, dag ins, string opnstr, list<dag> pattern = []> 301*06c3fb27SDimitry Andric : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 30281ad6265SDimitry Andric bits<12> imm12; 30381ad6265SDimitry Andric bits<5> rj; 30481ad6265SDimitry Andric bits<5> imm5; 30581ad6265SDimitry Andric 30681ad6265SDimitry Andric let Inst{31-22} = 0b0010101011; 30781ad6265SDimitry Andric let Inst{21-10} = imm12; 30881ad6265SDimitry Andric let Inst{9-5} = rj; 30981ad6265SDimitry Andric let Inst{4-0} = imm5; 31081ad6265SDimitry Andric} 31181ad6265SDimitry Andric 31281ad6265SDimitry Andric// FmtPRELDX 31381ad6265SDimitry Andric// < 0b00111000001011000 | rk | rj | I5> 314*06c3fb27SDimitry Andricclass FmtPRELDX<dag outs, dag ins, string opnstr, list<dag> pattern = []> 315*06c3fb27SDimitry Andric : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 31681ad6265SDimitry Andric bits<5> rk; 31781ad6265SDimitry Andric bits<5> rj; 31881ad6265SDimitry Andric bits<5> imm5; 31981ad6265SDimitry Andric 32081ad6265SDimitry Andric let Inst{31-15} = 0b00111000001011000; 32181ad6265SDimitry Andric let Inst{14-10} = rk; 32281ad6265SDimitry Andric let Inst{9-5} = rj; 32381ad6265SDimitry Andric let Inst{4-0} = imm5; 32481ad6265SDimitry Andric} 32581ad6265SDimitry Andric 32681ad6265SDimitry Andric// FmtCSR 327*06c3fb27SDimitry Andric// <opcode | csr_num | rd> 328*06c3fb27SDimitry Andricclass FmtCSR<bits<32> op, dag outs, dag ins, string opnstr, 32981ad6265SDimitry Andric list<dag> pattern = []> 330*06c3fb27SDimitry Andric : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 33181ad6265SDimitry Andric bits<14> csr_num; 33281ad6265SDimitry Andric bits<5> rd; 33381ad6265SDimitry Andric 334*06c3fb27SDimitry Andric let Inst{31-0} = op; 33581ad6265SDimitry Andric let Inst{23-10} = csr_num; 33681ad6265SDimitry Andric let Inst{4-0} = rd; 33781ad6265SDimitry Andric} 33881ad6265SDimitry Andric 33981ad6265SDimitry Andric// FmtCSRXCHG 34081ad6265SDimitry Andric// <opcode | csr_num | rj | rd> 341*06c3fb27SDimitry Andricclass FmtCSRXCHG<bits<32> op, dag outs, dag ins, string opnstr, 34281ad6265SDimitry Andric list<dag> pattern = []> 343*06c3fb27SDimitry Andric : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 34481ad6265SDimitry Andric bits<14> csr_num; 34581ad6265SDimitry Andric bits<5> rj; 34681ad6265SDimitry Andric bits<5> rd; 34781ad6265SDimitry Andric 348*06c3fb27SDimitry Andric let Inst{31-0} = op; 34981ad6265SDimitry Andric let Inst{23-10} = csr_num; 35081ad6265SDimitry Andric let Inst{9-5} = rj; 35181ad6265SDimitry Andric let Inst{4-0} = rd; 35281ad6265SDimitry Andric} 35381ad6265SDimitry Andric 35481ad6265SDimitry Andric// FmtCACOP 35581ad6265SDimitry Andric// <0b0000011000 | I12 | rj | I5> 356*06c3fb27SDimitry Andricclass FmtCACOP<dag outs, dag ins, string opnstr, list<dag> pattern = []> 357*06c3fb27SDimitry Andric : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 35881ad6265SDimitry Andric bits<12> imm12; 35981ad6265SDimitry Andric bits<5> rj; 36081ad6265SDimitry Andric bits<5> op; 36181ad6265SDimitry Andric 36281ad6265SDimitry Andric let Inst{31-22} = 0b0000011000; 36381ad6265SDimitry Andric let Inst{21-10} = imm12; 36481ad6265SDimitry Andric let Inst{9-5} = rj; 36581ad6265SDimitry Andric let Inst{4-0} = op; 36681ad6265SDimitry Andric} 36781ad6265SDimitry Andric 36881ad6265SDimitry Andric// FmtIMM32 36981ad6265SDimitry Andric// <I32> 370*06c3fb27SDimitry Andricclass FmtI32<bits<32> op, list<dag> pattern = []> 371*06c3fb27SDimitry Andric : LAInst<(outs), (ins), deriveInsnMnemonic<NAME>.ret, "", pattern> { 37281ad6265SDimitry Andric let Inst{31-0} = op; 37381ad6265SDimitry Andric} 37481ad6265SDimitry Andric 37581ad6265SDimitry Andric// FmtINVTLB 37681ad6265SDimitry Andric// <0b00000110010010011 | rk | rj | I5> 377*06c3fb27SDimitry Andricclass FmtINVTLB<dag outs, dag ins, string opnstr, list<dag> pattern = []> 378*06c3fb27SDimitry Andric : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 37981ad6265SDimitry Andric bits<5> rk; 38081ad6265SDimitry Andric bits<5> rj; 38181ad6265SDimitry Andric bits<5> op; 38281ad6265SDimitry Andric 38381ad6265SDimitry Andric let Inst{31-15} = 0b00000110010010011; 38481ad6265SDimitry Andric let Inst{14-10} = rk; 38581ad6265SDimitry Andric let Inst{9-5} = rj; 38681ad6265SDimitry Andric let Inst{4-0} = op; 38781ad6265SDimitry Andric} 38881ad6265SDimitry Andric 38981ad6265SDimitry Andric// FmtLDPTE 39081ad6265SDimitry Andric// <0b00000110010001 | seq | rj | 00000> 391*06c3fb27SDimitry Andricclass FmtLDPTE<dag outs, dag ins, string opnstr, list<dag> pattern = []> 392*06c3fb27SDimitry Andric : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 39381ad6265SDimitry Andric bits<8> seq; 39481ad6265SDimitry Andric bits<5> rj; 39581ad6265SDimitry Andric 39681ad6265SDimitry Andric let Inst{31-18} = 0b00000110010001; 39781ad6265SDimitry Andric let Inst{17-10} = seq; 39881ad6265SDimitry Andric let Inst{9-5} = rj; 39981ad6265SDimitry Andric let Inst{4-0} = 0b00000; 40081ad6265SDimitry Andric} 401