1//===- LoongArchLSXInstrInfo.td - LoongArch LSX instructions -*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the SIMD extension instructions. 10// 11//===----------------------------------------------------------------------===// 12 13def SDT_LoongArchVreplve : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>, 14 SDTCisInt<1>, SDTCisVec<1>, 15 SDTCisSameAs<0, 1>, SDTCisInt<2>]>; 16def SDT_LoongArchVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>; 17 18// Target nodes. 19def loongarch_vreplve : SDNode<"LoongArchISD::VREPLVE", SDT_LoongArchVreplve>; 20def loongarch_vall_nonzero : SDNode<"LoongArchISD::VALL_NONZERO", 21 SDT_LoongArchVecCond>; 22def loongarch_vany_nonzero : SDNode<"LoongArchISD::VANY_NONZERO", 23 SDT_LoongArchVecCond>; 24def loongarch_vall_zero : SDNode<"LoongArchISD::VALL_ZERO", 25 SDT_LoongArchVecCond>; 26def loongarch_vany_zero : SDNode<"LoongArchISD::VANY_ZERO", 27 SDT_LoongArchVecCond>; 28 29def loongarch_vpick_sext_elt : SDNode<"LoongArchISD::VPICK_SEXT_ELT", 30 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>>; 31def loongarch_vpick_zext_elt : SDNode<"LoongArchISD::VPICK_ZEXT_ELT", 32 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>>; 33 34class VecCond<SDPatternOperator OpNode, ValueType TyNode, 35 RegisterClass RC = LSX128> 36 : Pseudo<(outs GPR:$rd), (ins RC:$vj), 37 [(set GPR:$rd, (OpNode (TyNode RC:$vj)))]> { 38 let hasSideEffects = 0; 39 let mayLoad = 0; 40 let mayStore = 0; 41 let usesCustomInserter = 1; 42} 43 44def vsplat_imm_eq_1 : PatFrags<(ops), [(build_vector), 45 (bitconvert (v4i32 (build_vector)))], [{ 46 APInt Imm; 47 EVT EltTy = N->getValueType(0).getVectorElementType(); 48 49 if (N->getOpcode() == ISD::BITCAST) 50 N = N->getOperand(0).getNode(); 51 52 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 53 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1; 54}]>; 55 56def vsplati8_imm_eq_7 : PatFrags<(ops), [(build_vector)], [{ 57 APInt Imm; 58 EVT EltTy = N->getValueType(0).getVectorElementType(); 59 60 if (N->getOpcode() == ISD::BITCAST) 61 N = N->getOperand(0).getNode(); 62 63 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 64 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 7; 65}]>; 66def vsplati16_imm_eq_15 : PatFrags<(ops), [(build_vector)], [{ 67 APInt Imm; 68 EVT EltTy = N->getValueType(0).getVectorElementType(); 69 70 if (N->getOpcode() == ISD::BITCAST) 71 N = N->getOperand(0).getNode(); 72 73 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 74 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 15; 75}]>; 76def vsplati32_imm_eq_31 : PatFrags<(ops), [(build_vector)], [{ 77 APInt Imm; 78 EVT EltTy = N->getValueType(0).getVectorElementType(); 79 80 if (N->getOpcode() == ISD::BITCAST) 81 N = N->getOperand(0).getNode(); 82 83 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 84 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 31; 85}]>; 86def vsplati64_imm_eq_63 : PatFrags<(ops), [(build_vector), 87 (bitconvert (v4i32 (build_vector)))], [{ 88 APInt Imm; 89 EVT EltTy = N->getValueType(0).getVectorElementType(); 90 91 if (N->getOpcode() == ISD::BITCAST) 92 N = N->getOperand(0).getNode(); 93 94 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 95 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 63; 96}]>; 97 98def vsplatf32_fpimm_eq_1 99 : PatFrags<(ops), [(bitconvert (v4i32 (build_vector))), 100 (bitconvert (v8i32 (build_vector)))], [{ 101 APInt Imm; 102 EVT EltTy = N->getValueType(0).getVectorElementType(); 103 N = N->getOperand(0).getNode(); 104 105 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 106 Imm.getBitWidth() == EltTy.getSizeInBits() && 107 Imm == APFloat(+1.0f).bitcastToAPInt(); 108}]>; 109def vsplatf64_fpimm_eq_1 110 : PatFrags<(ops), [(bitconvert (v2i64 (build_vector))), 111 (bitconvert (v4i64 (build_vector)))], [{ 112 APInt Imm; 113 EVT EltTy = N->getValueType(0).getVectorElementType(); 114 N = N->getOperand(0).getNode(); 115 116 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 117 Imm.getBitWidth() == EltTy.getSizeInBits() && 118 Imm == APFloat(+1.0).bitcastToAPInt(); 119}]>; 120 121def vsplati8imm7 : PatFrag<(ops node:$reg), 122 (and node:$reg, vsplati8_imm_eq_7)>; 123def vsplati16imm15 : PatFrag<(ops node:$reg), 124 (and node:$reg, vsplati16_imm_eq_15)>; 125def vsplati32imm31 : PatFrag<(ops node:$reg), 126 (and node:$reg, vsplati32_imm_eq_31)>; 127def vsplati64imm63 : PatFrag<(ops node:$reg), 128 (and node:$reg, vsplati64_imm_eq_63)>; 129 130foreach N = [3, 4, 5, 6, 8] in 131 def SplatPat_uimm#N : ComplexPattern<vAny, 1, "selectVSplatImm<"#N#">", 132 [build_vector, bitconvert], [], 2>; 133 134foreach N = [5] in 135 def SplatPat_simm#N : ComplexPattern<vAny, 1, "selectVSplatImm<"#N#", true>", 136 [build_vector, bitconvert]>; 137 138def vsplat_uimm_inv_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmInvPow2", 139 [build_vector, bitconvert]>; 140 141def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2", 142 [build_vector, bitconvert]>; 143 144def muladd : PatFrag<(ops node:$vd, node:$vj, node:$vk), 145 (add node:$vd, (mul node:$vj, node:$vk))>; 146 147def mulsub : PatFrag<(ops node:$vd, node:$vj, node:$vk), 148 (sub node:$vd, (mul node:$vj, node:$vk))>; 149 150def lsxsplati8 : PatFrag<(ops node:$e0), 151 (v16i8 (build_vector node:$e0, node:$e0, 152 node:$e0, node:$e0, 153 node:$e0, node:$e0, 154 node:$e0, node:$e0, 155 node:$e0, node:$e0, 156 node:$e0, node:$e0, 157 node:$e0, node:$e0, 158 node:$e0, node:$e0))>; 159def lsxsplati16 : PatFrag<(ops node:$e0), 160 (v8i16 (build_vector node:$e0, node:$e0, 161 node:$e0, node:$e0, 162 node:$e0, node:$e0, 163 node:$e0, node:$e0))>; 164def lsxsplati32 : PatFrag<(ops node:$e0), 165 (v4i32 (build_vector node:$e0, node:$e0, 166 node:$e0, node:$e0))>; 167def lsxsplati64 : PatFrag<(ops node:$e0), 168 (v2i64 (build_vector node:$e0, node:$e0))>; 169def lsxsplatf32 : PatFrag<(ops node:$e0), 170 (v4f32 (build_vector node:$e0, node:$e0, 171 node:$e0, node:$e0))>; 172def lsxsplatf64 : PatFrag<(ops node:$e0), 173 (v2f64 (build_vector node:$e0, node:$e0))>; 174 175def to_valid_timm : SDNodeXForm<timm, [{ 176 auto CN = cast<ConstantSDNode>(N); 177 return CurDAG->getTargetConstant(CN->getSExtValue(), SDLoc(N), Subtarget->getGRLenVT()); 178}]>; 179 180//===----------------------------------------------------------------------===// 181// Instruction class templates 182//===----------------------------------------------------------------------===// 183 184class LSX1RI13_VI<bits<32> op, Operand ImmOpnd = simm13> 185 : Fmt1RI13_VI<op, (outs LSX128:$vd), (ins ImmOpnd:$imm13), "$vd, $imm13">; 186 187class LSX2R_VV<bits<32> op> 188 : Fmt2R_VV<op, (outs LSX128:$vd), (ins LSX128:$vj), "$vd, $vj">; 189 190class LSX2R_VR<bits<32> op> 191 : Fmt2R_VR<op, (outs LSX128:$vd), (ins GPR:$rj), "$vd, $rj">; 192 193class LSX2R_CV<bits<32> op> 194 : Fmt2R_CV<op, (outs CFR:$cd), (ins LSX128:$vj), "$cd, $vj">; 195 196class LSX2RI1_VVI<bits<32> op, Operand ImmOpnd = uimm1> 197 : Fmt2RI1_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm1), 198 "$vd, $vj, $imm1">; 199 200class LSX2RI1_RVI<bits<32> op, Operand ImmOpnd = uimm1> 201 : Fmt2RI1_RVI<op, (outs GPR:$rd), (ins LSX128:$vj, ImmOpnd:$imm1), 202 "$rd, $vj, $imm1">; 203 204class LSX2RI2_VVI<bits<32> op, Operand ImmOpnd = uimm2> 205 : Fmt2RI2_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm2), 206 "$vd, $vj, $imm2">; 207 208class LSX2RI2_RVI<bits<32> op, Operand ImmOpnd = uimm2> 209 : Fmt2RI2_RVI<op, (outs GPR:$rd), (ins LSX128:$vj, ImmOpnd:$imm2), 210 "$rd, $vj, $imm2">; 211 212class LSX2RI3_VVI<bits<32> op, Operand ImmOpnd = uimm3> 213 : Fmt2RI3_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm3), 214 "$vd, $vj, $imm3">; 215 216class LSX2RI3_RVI<bits<32> op, Operand ImmOpnd = uimm3> 217 : Fmt2RI3_RVI<op, (outs GPR:$rd), (ins LSX128:$vj, ImmOpnd:$imm3), 218 "$rd, $vj, $imm3">; 219 220class LSX2RI4_VVI<bits<32> op, Operand ImmOpnd = uimm4> 221 : Fmt2RI4_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm4), 222 "$vd, $vj, $imm4">; 223 224class LSX2RI4_RVI<bits<32> op, Operand ImmOpnd = uimm4> 225 : Fmt2RI4_RVI<op, (outs GPR:$rd), (ins LSX128:$vj, ImmOpnd:$imm4), 226 "$rd, $vj, $imm4">; 227 228class LSX2RI5_VVI<bits<32> op, Operand ImmOpnd = uimm5> 229 : Fmt2RI5_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm5), 230 "$vd, $vj, $imm5">; 231 232class LSX2RI6_VVI<bits<32> op, Operand ImmOpnd = uimm6> 233 : Fmt2RI6_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm6), 234 "$vd, $vj, $imm6">; 235 236class LSX2RI8_VVI<bits<32> op, Operand ImmOpnd = uimm8> 237 : Fmt2RI8_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm8), 238 "$vd, $vj, $imm8">; 239 240class LSX2RI8I1_VRII<bits<32> op, Operand ImmOpnd = simm8, 241 Operand IdxOpnd = uimm1> 242 : Fmt2RI8I1_VRII<op, (outs), 243 (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm1), 244 "$vd, $rj, $imm8, $imm1">; 245class LSX2RI8I2_VRII<bits<32> op, Operand ImmOpnd = simm8, 246 Operand IdxOpnd = uimm2> 247 : Fmt2RI8I2_VRII<op, (outs), 248 (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm2), 249 "$vd, $rj, $imm8, $imm2">; 250class LSX2RI8I3_VRII<bits<32> op, Operand ImmOpnd = simm8, 251 Operand IdxOpnd = uimm3> 252 : Fmt2RI8I3_VRII<op, (outs), 253 (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm3), 254 "$vd, $rj, $imm8, $imm3">; 255class LSX2RI8I4_VRII<bits<32> op, Operand ImmOpnd = simm8, 256 Operand IdxOpnd = uimm4> 257 : Fmt2RI8I4_VRII<op, (outs), 258 (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm4), 259 "$vd, $rj, $imm8, $imm4">; 260 261class LSX3R_VVV<bits<32> op> 262 : Fmt3R_VVV<op, (outs LSX128:$vd), (ins LSX128:$vj, LSX128:$vk), 263 "$vd, $vj, $vk">; 264 265class LSX3R_VVR<bits<32> op> 266 : Fmt3R_VVR<op, (outs LSX128:$vd), (ins LSX128:$vj, GPR:$rk), 267 "$vd, $vj, $rk">; 268 269class LSX4R_VVVV<bits<32> op> 270 : Fmt4R_VVVV<op, (outs LSX128:$vd), 271 (ins LSX128:$vj, LSX128:$vk, LSX128:$va), 272 "$vd, $vj, $vk, $va">; 273 274let Constraints = "$vd = $dst" in { 275 276class LSX2RI1_VVRI<bits<32> op, Operand ImmOpnd = uimm1> 277 : Fmt2RI1_VRI<op, (outs LSX128:$dst), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm1), 278 "$vd, $rj, $imm1">; 279class LSX2RI2_VVRI<bits<32> op, Operand ImmOpnd = uimm2> 280 : Fmt2RI2_VRI<op, (outs LSX128:$dst), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm2), 281 "$vd, $rj, $imm2">; 282class LSX2RI3_VVRI<bits<32> op, Operand ImmOpnd = uimm3> 283 : Fmt2RI3_VRI<op, (outs LSX128:$dst), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm3), 284 "$vd, $rj, $imm3">; 285class LSX2RI4_VVRI<bits<32> op, Operand ImmOpnd = uimm4> 286 : Fmt2RI4_VRI<op, (outs LSX128:$dst), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm4), 287 "$vd, $rj, $imm4">; 288 289class LSX2RI4_VVVI<bits<32> op, Operand ImmOpnd = uimm4> 290 : Fmt2RI4_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm4), 291 "$vd, $vj, $imm4">; 292class LSX2RI5_VVVI<bits<32> op, Operand ImmOpnd = uimm5> 293 : Fmt2RI5_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm5), 294 "$vd, $vj, $imm5">; 295class LSX2RI6_VVVI<bits<32> op, Operand ImmOpnd = uimm6> 296 : Fmt2RI6_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm6), 297 "$vd, $vj, $imm6">; 298class LSX2RI7_VVVI<bits<32> op, Operand ImmOpnd = uimm7> 299 : Fmt2RI7_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm7), 300 "$vd, $vj, $imm7">; 301 302class LSX2RI8_VVVI<bits<32> op, Operand ImmOpnd = uimm8> 303 : Fmt2RI8_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm8), 304 "$vd, $vj, $imm8">; 305 306class LSX3R_VVVV<bits<32> op> 307 : Fmt3R_VVV<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, LSX128:$vk), 308 "$vd, $vj, $vk">; 309 310} // Constraints = "$vd = $dst" 311 312class LSX2RI9_Load<bits<32> op, Operand ImmOpnd = simm9_lsl3> 313 : Fmt2RI9_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm9), 314 "$vd, $rj, $imm9">; 315class LSX2RI10_Load<bits<32> op, Operand ImmOpnd = simm10_lsl2> 316 : Fmt2RI10_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm10), 317 "$vd, $rj, $imm10">; 318class LSX2RI11_Load<bits<32> op, Operand ImmOpnd = simm11_lsl1> 319 : Fmt2RI11_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm11), 320 "$vd, $rj, $imm11">; 321class LSX2RI12_Load<bits<32> op, Operand ImmOpnd = simm12> 322 : Fmt2RI12_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm12), 323 "$vd, $rj, $imm12">; 324class LSX2RI12_Store<bits<32> op, Operand ImmOpnd = simm12> 325 : Fmt2RI12_VRI<op, (outs), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm12), 326 "$vd, $rj, $imm12">; 327 328class LSX3R_Load<bits<32> op> 329 : Fmt3R_VRR<op, (outs LSX128:$vd), (ins GPR:$rj, GPR:$rk), 330 "$vd, $rj, $rk">; 331class LSX3R_Store<bits<32> op> 332 : Fmt3R_VRR<op, (outs), (ins LSX128:$vd, GPR:$rj, GPR:$rk), 333 "$vd, $rj, $rk">; 334 335//===----------------------------------------------------------------------===// 336// Instructions 337//===----------------------------------------------------------------------===// 338 339let hasSideEffects = 0, Predicates = [HasExtLSX] in { 340 341let mayLoad = 0, mayStore = 0 in { 342 343def VADD_B : LSX3R_VVV<0x700a0000>; 344def VADD_H : LSX3R_VVV<0x700a8000>; 345def VADD_W : LSX3R_VVV<0x700b0000>; 346def VADD_D : LSX3R_VVV<0x700b8000>; 347def VADD_Q : LSX3R_VVV<0x712d0000>; 348 349def VSUB_B : LSX3R_VVV<0x700c0000>; 350def VSUB_H : LSX3R_VVV<0x700c8000>; 351def VSUB_W : LSX3R_VVV<0x700d0000>; 352def VSUB_D : LSX3R_VVV<0x700d8000>; 353def VSUB_Q : LSX3R_VVV<0x712d8000>; 354 355def VADDI_BU : LSX2RI5_VVI<0x728a0000>; 356def VADDI_HU : LSX2RI5_VVI<0x728a8000>; 357def VADDI_WU : LSX2RI5_VVI<0x728b0000>; 358def VADDI_DU : LSX2RI5_VVI<0x728b8000>; 359 360def VSUBI_BU : LSX2RI5_VVI<0x728c0000>; 361def VSUBI_HU : LSX2RI5_VVI<0x728c8000>; 362def VSUBI_WU : LSX2RI5_VVI<0x728d0000>; 363def VSUBI_DU : LSX2RI5_VVI<0x728d8000>; 364 365def VNEG_B : LSX2R_VV<0x729c3000>; 366def VNEG_H : LSX2R_VV<0x729c3400>; 367def VNEG_W : LSX2R_VV<0x729c3800>; 368def VNEG_D : LSX2R_VV<0x729c3c00>; 369 370def VSADD_B : LSX3R_VVV<0x70460000>; 371def VSADD_H : LSX3R_VVV<0x70468000>; 372def VSADD_W : LSX3R_VVV<0x70470000>; 373def VSADD_D : LSX3R_VVV<0x70478000>; 374def VSADD_BU : LSX3R_VVV<0x704a0000>; 375def VSADD_HU : LSX3R_VVV<0x704a8000>; 376def VSADD_WU : LSX3R_VVV<0x704b0000>; 377def VSADD_DU : LSX3R_VVV<0x704b8000>; 378 379def VSSUB_B : LSX3R_VVV<0x70480000>; 380def VSSUB_H : LSX3R_VVV<0x70488000>; 381def VSSUB_W : LSX3R_VVV<0x70490000>; 382def VSSUB_D : LSX3R_VVV<0x70498000>; 383def VSSUB_BU : LSX3R_VVV<0x704c0000>; 384def VSSUB_HU : LSX3R_VVV<0x704c8000>; 385def VSSUB_WU : LSX3R_VVV<0x704d0000>; 386def VSSUB_DU : LSX3R_VVV<0x704d8000>; 387 388def VHADDW_H_B : LSX3R_VVV<0x70540000>; 389def VHADDW_W_H : LSX3R_VVV<0x70548000>; 390def VHADDW_D_W : LSX3R_VVV<0x70550000>; 391def VHADDW_Q_D : LSX3R_VVV<0x70558000>; 392def VHADDW_HU_BU : LSX3R_VVV<0x70580000>; 393def VHADDW_WU_HU : LSX3R_VVV<0x70588000>; 394def VHADDW_DU_WU : LSX3R_VVV<0x70590000>; 395def VHADDW_QU_DU : LSX3R_VVV<0x70598000>; 396 397def VHSUBW_H_B : LSX3R_VVV<0x70560000>; 398def VHSUBW_W_H : LSX3R_VVV<0x70568000>; 399def VHSUBW_D_W : LSX3R_VVV<0x70570000>; 400def VHSUBW_Q_D : LSX3R_VVV<0x70578000>; 401def VHSUBW_HU_BU : LSX3R_VVV<0x705a0000>; 402def VHSUBW_WU_HU : LSX3R_VVV<0x705a8000>; 403def VHSUBW_DU_WU : LSX3R_VVV<0x705b0000>; 404def VHSUBW_QU_DU : LSX3R_VVV<0x705b8000>; 405 406def VADDWEV_H_B : LSX3R_VVV<0x701e0000>; 407def VADDWEV_W_H : LSX3R_VVV<0x701e8000>; 408def VADDWEV_D_W : LSX3R_VVV<0x701f0000>; 409def VADDWEV_Q_D : LSX3R_VVV<0x701f8000>; 410def VADDWOD_H_B : LSX3R_VVV<0x70220000>; 411def VADDWOD_W_H : LSX3R_VVV<0x70228000>; 412def VADDWOD_D_W : LSX3R_VVV<0x70230000>; 413def VADDWOD_Q_D : LSX3R_VVV<0x70238000>; 414 415def VSUBWEV_H_B : LSX3R_VVV<0x70200000>; 416def VSUBWEV_W_H : LSX3R_VVV<0x70208000>; 417def VSUBWEV_D_W : LSX3R_VVV<0x70210000>; 418def VSUBWEV_Q_D : LSX3R_VVV<0x70218000>; 419def VSUBWOD_H_B : LSX3R_VVV<0x70240000>; 420def VSUBWOD_W_H : LSX3R_VVV<0x70248000>; 421def VSUBWOD_D_W : LSX3R_VVV<0x70250000>; 422def VSUBWOD_Q_D : LSX3R_VVV<0x70258000>; 423 424def VADDWEV_H_BU : LSX3R_VVV<0x702e0000>; 425def VADDWEV_W_HU : LSX3R_VVV<0x702e8000>; 426def VADDWEV_D_WU : LSX3R_VVV<0x702f0000>; 427def VADDWEV_Q_DU : LSX3R_VVV<0x702f8000>; 428def VADDWOD_H_BU : LSX3R_VVV<0x70320000>; 429def VADDWOD_W_HU : LSX3R_VVV<0x70328000>; 430def VADDWOD_D_WU : LSX3R_VVV<0x70330000>; 431def VADDWOD_Q_DU : LSX3R_VVV<0x70338000>; 432 433def VSUBWEV_H_BU : LSX3R_VVV<0x70300000>; 434def VSUBWEV_W_HU : LSX3R_VVV<0x70308000>; 435def VSUBWEV_D_WU : LSX3R_VVV<0x70310000>; 436def VSUBWEV_Q_DU : LSX3R_VVV<0x70318000>; 437def VSUBWOD_H_BU : LSX3R_VVV<0x70340000>; 438def VSUBWOD_W_HU : LSX3R_VVV<0x70348000>; 439def VSUBWOD_D_WU : LSX3R_VVV<0x70350000>; 440def VSUBWOD_Q_DU : LSX3R_VVV<0x70358000>; 441 442def VADDWEV_H_BU_B : LSX3R_VVV<0x703e0000>; 443def VADDWEV_W_HU_H : LSX3R_VVV<0x703e8000>; 444def VADDWEV_D_WU_W : LSX3R_VVV<0x703f0000>; 445def VADDWEV_Q_DU_D : LSX3R_VVV<0x703f8000>; 446def VADDWOD_H_BU_B : LSX3R_VVV<0x70400000>; 447def VADDWOD_W_HU_H : LSX3R_VVV<0x70408000>; 448def VADDWOD_D_WU_W : LSX3R_VVV<0x70410000>; 449def VADDWOD_Q_DU_D : LSX3R_VVV<0x70418000>; 450 451def VAVG_B : LSX3R_VVV<0x70640000>; 452def VAVG_H : LSX3R_VVV<0x70648000>; 453def VAVG_W : LSX3R_VVV<0x70650000>; 454def VAVG_D : LSX3R_VVV<0x70658000>; 455def VAVG_BU : LSX3R_VVV<0x70660000>; 456def VAVG_HU : LSX3R_VVV<0x70668000>; 457def VAVG_WU : LSX3R_VVV<0x70670000>; 458def VAVG_DU : LSX3R_VVV<0x70678000>; 459def VAVGR_B : LSX3R_VVV<0x70680000>; 460def VAVGR_H : LSX3R_VVV<0x70688000>; 461def VAVGR_W : LSX3R_VVV<0x70690000>; 462def VAVGR_D : LSX3R_VVV<0x70698000>; 463def VAVGR_BU : LSX3R_VVV<0x706a0000>; 464def VAVGR_HU : LSX3R_VVV<0x706a8000>; 465def VAVGR_WU : LSX3R_VVV<0x706b0000>; 466def VAVGR_DU : LSX3R_VVV<0x706b8000>; 467 468def VABSD_B : LSX3R_VVV<0x70600000>; 469def VABSD_H : LSX3R_VVV<0x70608000>; 470def VABSD_W : LSX3R_VVV<0x70610000>; 471def VABSD_D : LSX3R_VVV<0x70618000>; 472def VABSD_BU : LSX3R_VVV<0x70620000>; 473def VABSD_HU : LSX3R_VVV<0x70628000>; 474def VABSD_WU : LSX3R_VVV<0x70630000>; 475def VABSD_DU : LSX3R_VVV<0x70638000>; 476 477def VADDA_B : LSX3R_VVV<0x705c0000>; 478def VADDA_H : LSX3R_VVV<0x705c8000>; 479def VADDA_W : LSX3R_VVV<0x705d0000>; 480def VADDA_D : LSX3R_VVV<0x705d8000>; 481 482def VMAX_B : LSX3R_VVV<0x70700000>; 483def VMAX_H : LSX3R_VVV<0x70708000>; 484def VMAX_W : LSX3R_VVV<0x70710000>; 485def VMAX_D : LSX3R_VVV<0x70718000>; 486def VMAXI_B : LSX2RI5_VVI<0x72900000, simm5>; 487def VMAXI_H : LSX2RI5_VVI<0x72908000, simm5>; 488def VMAXI_W : LSX2RI5_VVI<0x72910000, simm5>; 489def VMAXI_D : LSX2RI5_VVI<0x72918000, simm5>; 490def VMAX_BU : LSX3R_VVV<0x70740000>; 491def VMAX_HU : LSX3R_VVV<0x70748000>; 492def VMAX_WU : LSX3R_VVV<0x70750000>; 493def VMAX_DU : LSX3R_VVV<0x70758000>; 494def VMAXI_BU : LSX2RI5_VVI<0x72940000>; 495def VMAXI_HU : LSX2RI5_VVI<0x72948000>; 496def VMAXI_WU : LSX2RI5_VVI<0x72950000>; 497def VMAXI_DU : LSX2RI5_VVI<0x72958000>; 498 499def VMIN_B : LSX3R_VVV<0x70720000>; 500def VMIN_H : LSX3R_VVV<0x70728000>; 501def VMIN_W : LSX3R_VVV<0x70730000>; 502def VMIN_D : LSX3R_VVV<0x70738000>; 503def VMINI_B : LSX2RI5_VVI<0x72920000, simm5>; 504def VMINI_H : LSX2RI5_VVI<0x72928000, simm5>; 505def VMINI_W : LSX2RI5_VVI<0x72930000, simm5>; 506def VMINI_D : LSX2RI5_VVI<0x72938000, simm5>; 507def VMIN_BU : LSX3R_VVV<0x70760000>; 508def VMIN_HU : LSX3R_VVV<0x70768000>; 509def VMIN_WU : LSX3R_VVV<0x70770000>; 510def VMIN_DU : LSX3R_VVV<0x70778000>; 511def VMINI_BU : LSX2RI5_VVI<0x72960000>; 512def VMINI_HU : LSX2RI5_VVI<0x72968000>; 513def VMINI_WU : LSX2RI5_VVI<0x72970000>; 514def VMINI_DU : LSX2RI5_VVI<0x72978000>; 515 516def VMUL_B : LSX3R_VVV<0x70840000>; 517def VMUL_H : LSX3R_VVV<0x70848000>; 518def VMUL_W : LSX3R_VVV<0x70850000>; 519def VMUL_D : LSX3R_VVV<0x70858000>; 520 521def VMUH_B : LSX3R_VVV<0x70860000>; 522def VMUH_H : LSX3R_VVV<0x70868000>; 523def VMUH_W : LSX3R_VVV<0x70870000>; 524def VMUH_D : LSX3R_VVV<0x70878000>; 525def VMUH_BU : LSX3R_VVV<0x70880000>; 526def VMUH_HU : LSX3R_VVV<0x70888000>; 527def VMUH_WU : LSX3R_VVV<0x70890000>; 528def VMUH_DU : LSX3R_VVV<0x70898000>; 529 530def VMULWEV_H_B : LSX3R_VVV<0x70900000>; 531def VMULWEV_W_H : LSX3R_VVV<0x70908000>; 532def VMULWEV_D_W : LSX3R_VVV<0x70910000>; 533def VMULWEV_Q_D : LSX3R_VVV<0x70918000>; 534def VMULWOD_H_B : LSX3R_VVV<0x70920000>; 535def VMULWOD_W_H : LSX3R_VVV<0x70928000>; 536def VMULWOD_D_W : LSX3R_VVV<0x70930000>; 537def VMULWOD_Q_D : LSX3R_VVV<0x70938000>; 538def VMULWEV_H_BU : LSX3R_VVV<0x70980000>; 539def VMULWEV_W_HU : LSX3R_VVV<0x70988000>; 540def VMULWEV_D_WU : LSX3R_VVV<0x70990000>; 541def VMULWEV_Q_DU : LSX3R_VVV<0x70998000>; 542def VMULWOD_H_BU : LSX3R_VVV<0x709a0000>; 543def VMULWOD_W_HU : LSX3R_VVV<0x709a8000>; 544def VMULWOD_D_WU : LSX3R_VVV<0x709b0000>; 545def VMULWOD_Q_DU : LSX3R_VVV<0x709b8000>; 546def VMULWEV_H_BU_B : LSX3R_VVV<0x70a00000>; 547def VMULWEV_W_HU_H : LSX3R_VVV<0x70a08000>; 548def VMULWEV_D_WU_W : LSX3R_VVV<0x70a10000>; 549def VMULWEV_Q_DU_D : LSX3R_VVV<0x70a18000>; 550def VMULWOD_H_BU_B : LSX3R_VVV<0x70a20000>; 551def VMULWOD_W_HU_H : LSX3R_VVV<0x70a28000>; 552def VMULWOD_D_WU_W : LSX3R_VVV<0x70a30000>; 553def VMULWOD_Q_DU_D : LSX3R_VVV<0x70a38000>; 554 555def VMADD_B : LSX3R_VVVV<0x70a80000>; 556def VMADD_H : LSX3R_VVVV<0x70a88000>; 557def VMADD_W : LSX3R_VVVV<0x70a90000>; 558def VMADD_D : LSX3R_VVVV<0x70a98000>; 559 560def VMSUB_B : LSX3R_VVVV<0x70aa0000>; 561def VMSUB_H : LSX3R_VVVV<0x70aa8000>; 562def VMSUB_W : LSX3R_VVVV<0x70ab0000>; 563def VMSUB_D : LSX3R_VVVV<0x70ab8000>; 564 565def VMADDWEV_H_B : LSX3R_VVVV<0x70ac0000>; 566def VMADDWEV_W_H : LSX3R_VVVV<0x70ac8000>; 567def VMADDWEV_D_W : LSX3R_VVVV<0x70ad0000>; 568def VMADDWEV_Q_D : LSX3R_VVVV<0x70ad8000>; 569def VMADDWOD_H_B : LSX3R_VVVV<0x70ae0000>; 570def VMADDWOD_W_H : LSX3R_VVVV<0x70ae8000>; 571def VMADDWOD_D_W : LSX3R_VVVV<0x70af0000>; 572def VMADDWOD_Q_D : LSX3R_VVVV<0x70af8000>; 573def VMADDWEV_H_BU : LSX3R_VVVV<0x70b40000>; 574def VMADDWEV_W_HU : LSX3R_VVVV<0x70b48000>; 575def VMADDWEV_D_WU : LSX3R_VVVV<0x70b50000>; 576def VMADDWEV_Q_DU : LSX3R_VVVV<0x70b58000>; 577def VMADDWOD_H_BU : LSX3R_VVVV<0x70b60000>; 578def VMADDWOD_W_HU : LSX3R_VVVV<0x70b68000>; 579def VMADDWOD_D_WU : LSX3R_VVVV<0x70b70000>; 580def VMADDWOD_Q_DU : LSX3R_VVVV<0x70b78000>; 581def VMADDWEV_H_BU_B : LSX3R_VVVV<0x70bc0000>; 582def VMADDWEV_W_HU_H : LSX3R_VVVV<0x70bc8000>; 583def VMADDWEV_D_WU_W : LSX3R_VVVV<0x70bd0000>; 584def VMADDWEV_Q_DU_D : LSX3R_VVVV<0x70bd8000>; 585def VMADDWOD_H_BU_B : LSX3R_VVVV<0x70be0000>; 586def VMADDWOD_W_HU_H : LSX3R_VVVV<0x70be8000>; 587def VMADDWOD_D_WU_W : LSX3R_VVVV<0x70bf0000>; 588def VMADDWOD_Q_DU_D : LSX3R_VVVV<0x70bf8000>; 589 590def VDIV_B : LSX3R_VVV<0x70e00000>; 591def VDIV_H : LSX3R_VVV<0x70e08000>; 592def VDIV_W : LSX3R_VVV<0x70e10000>; 593def VDIV_D : LSX3R_VVV<0x70e18000>; 594def VDIV_BU : LSX3R_VVV<0x70e40000>; 595def VDIV_HU : LSX3R_VVV<0x70e48000>; 596def VDIV_WU : LSX3R_VVV<0x70e50000>; 597def VDIV_DU : LSX3R_VVV<0x70e58000>; 598 599def VMOD_B : LSX3R_VVV<0x70e20000>; 600def VMOD_H : LSX3R_VVV<0x70e28000>; 601def VMOD_W : LSX3R_VVV<0x70e30000>; 602def VMOD_D : LSX3R_VVV<0x70e38000>; 603def VMOD_BU : LSX3R_VVV<0x70e60000>; 604def VMOD_HU : LSX3R_VVV<0x70e68000>; 605def VMOD_WU : LSX3R_VVV<0x70e70000>; 606def VMOD_DU : LSX3R_VVV<0x70e78000>; 607 608def VSAT_B : LSX2RI3_VVI<0x73242000>; 609def VSAT_H : LSX2RI4_VVI<0x73244000>; 610def VSAT_W : LSX2RI5_VVI<0x73248000>; 611def VSAT_D : LSX2RI6_VVI<0x73250000>; 612def VSAT_BU : LSX2RI3_VVI<0x73282000>; 613def VSAT_HU : LSX2RI4_VVI<0x73284000>; 614def VSAT_WU : LSX2RI5_VVI<0x73288000>; 615def VSAT_DU : LSX2RI6_VVI<0x73290000>; 616 617def VEXTH_H_B : LSX2R_VV<0x729ee000>; 618def VEXTH_W_H : LSX2R_VV<0x729ee400>; 619def VEXTH_D_W : LSX2R_VV<0x729ee800>; 620def VEXTH_Q_D : LSX2R_VV<0x729eec00>; 621def VEXTH_HU_BU : LSX2R_VV<0x729ef000>; 622def VEXTH_WU_HU : LSX2R_VV<0x729ef400>; 623def VEXTH_DU_WU : LSX2R_VV<0x729ef800>; 624def VEXTH_QU_DU : LSX2R_VV<0x729efc00>; 625 626def VSIGNCOV_B : LSX3R_VVV<0x712e0000>; 627def VSIGNCOV_H : LSX3R_VVV<0x712e8000>; 628def VSIGNCOV_W : LSX3R_VVV<0x712f0000>; 629def VSIGNCOV_D : LSX3R_VVV<0x712f8000>; 630 631def VMSKLTZ_B : LSX2R_VV<0x729c4000>; 632def VMSKLTZ_H : LSX2R_VV<0x729c4400>; 633def VMSKLTZ_W : LSX2R_VV<0x729c4800>; 634def VMSKLTZ_D : LSX2R_VV<0x729c4c00>; 635 636def VMSKGEZ_B : LSX2R_VV<0x729c5000>; 637 638def VMSKNZ_B : LSX2R_VV<0x729c6000>; 639 640def VLDI : LSX1RI13_VI<0x73e00000>; 641 642def VAND_V : LSX3R_VVV<0x71260000>; 643def VOR_V : LSX3R_VVV<0x71268000>; 644def VXOR_V : LSX3R_VVV<0x71270000>; 645def VNOR_V : LSX3R_VVV<0x71278000>; 646def VANDN_V : LSX3R_VVV<0x71280000>; 647def VORN_V : LSX3R_VVV<0x71288000>; 648 649def VANDI_B : LSX2RI8_VVI<0x73d00000>; 650def VORI_B : LSX2RI8_VVI<0x73d40000>; 651def VXORI_B : LSX2RI8_VVI<0x73d80000>; 652def VNORI_B : LSX2RI8_VVI<0x73dc0000>; 653 654def VSLL_B : LSX3R_VVV<0x70e80000>; 655def VSLL_H : LSX3R_VVV<0x70e88000>; 656def VSLL_W : LSX3R_VVV<0x70e90000>; 657def VSLL_D : LSX3R_VVV<0x70e98000>; 658def VSLLI_B : LSX2RI3_VVI<0x732c2000>; 659def VSLLI_H : LSX2RI4_VVI<0x732c4000>; 660def VSLLI_W : LSX2RI5_VVI<0x732c8000>; 661def VSLLI_D : LSX2RI6_VVI<0x732d0000>; 662 663def VSRL_B : LSX3R_VVV<0x70ea0000>; 664def VSRL_H : LSX3R_VVV<0x70ea8000>; 665def VSRL_W : LSX3R_VVV<0x70eb0000>; 666def VSRL_D : LSX3R_VVV<0x70eb8000>; 667def VSRLI_B : LSX2RI3_VVI<0x73302000>; 668def VSRLI_H : LSX2RI4_VVI<0x73304000>; 669def VSRLI_W : LSX2RI5_VVI<0x73308000>; 670def VSRLI_D : LSX2RI6_VVI<0x73310000>; 671 672def VSRA_B : LSX3R_VVV<0x70ec0000>; 673def VSRA_H : LSX3R_VVV<0x70ec8000>; 674def VSRA_W : LSX3R_VVV<0x70ed0000>; 675def VSRA_D : LSX3R_VVV<0x70ed8000>; 676def VSRAI_B : LSX2RI3_VVI<0x73342000>; 677def VSRAI_H : LSX2RI4_VVI<0x73344000>; 678def VSRAI_W : LSX2RI5_VVI<0x73348000>; 679def VSRAI_D : LSX2RI6_VVI<0x73350000>; 680 681def VROTR_B : LSX3R_VVV<0x70ee0000>; 682def VROTR_H : LSX3R_VVV<0x70ee8000>; 683def VROTR_W : LSX3R_VVV<0x70ef0000>; 684def VROTR_D : LSX3R_VVV<0x70ef8000>; 685def VROTRI_B : LSX2RI3_VVI<0x72a02000>; 686def VROTRI_H : LSX2RI4_VVI<0x72a04000>; 687def VROTRI_W : LSX2RI5_VVI<0x72a08000>; 688def VROTRI_D : LSX2RI6_VVI<0x72a10000>; 689 690def VSLLWIL_H_B : LSX2RI3_VVI<0x73082000>; 691def VSLLWIL_W_H : LSX2RI4_VVI<0x73084000>; 692def VSLLWIL_D_W : LSX2RI5_VVI<0x73088000>; 693def VEXTL_Q_D : LSX2R_VV<0x73090000>; 694def VSLLWIL_HU_BU : LSX2RI3_VVI<0x730c2000>; 695def VSLLWIL_WU_HU : LSX2RI4_VVI<0x730c4000>; 696def VSLLWIL_DU_WU : LSX2RI5_VVI<0x730c8000>; 697def VEXTL_QU_DU : LSX2R_VV<0x730d0000>; 698 699def VSRLR_B : LSX3R_VVV<0x70f00000>; 700def VSRLR_H : LSX3R_VVV<0x70f08000>; 701def VSRLR_W : LSX3R_VVV<0x70f10000>; 702def VSRLR_D : LSX3R_VVV<0x70f18000>; 703def VSRLRI_B : LSX2RI3_VVI<0x72a42000>; 704def VSRLRI_H : LSX2RI4_VVI<0x72a44000>; 705def VSRLRI_W : LSX2RI5_VVI<0x72a48000>; 706def VSRLRI_D : LSX2RI6_VVI<0x72a50000>; 707 708def VSRAR_B : LSX3R_VVV<0x70f20000>; 709def VSRAR_H : LSX3R_VVV<0x70f28000>; 710def VSRAR_W : LSX3R_VVV<0x70f30000>; 711def VSRAR_D : LSX3R_VVV<0x70f38000>; 712def VSRARI_B : LSX2RI3_VVI<0x72a82000>; 713def VSRARI_H : LSX2RI4_VVI<0x72a84000>; 714def VSRARI_W : LSX2RI5_VVI<0x72a88000>; 715def VSRARI_D : LSX2RI6_VVI<0x72a90000>; 716 717def VSRLN_B_H : LSX3R_VVV<0x70f48000>; 718def VSRLN_H_W : LSX3R_VVV<0x70f50000>; 719def VSRLN_W_D : LSX3R_VVV<0x70f58000>; 720def VSRAN_B_H : LSX3R_VVV<0x70f68000>; 721def VSRAN_H_W : LSX3R_VVV<0x70f70000>; 722def VSRAN_W_D : LSX3R_VVV<0x70f78000>; 723 724def VSRLNI_B_H : LSX2RI4_VVVI<0x73404000>; 725def VSRLNI_H_W : LSX2RI5_VVVI<0x73408000>; 726def VSRLNI_W_D : LSX2RI6_VVVI<0x73410000>; 727def VSRLNI_D_Q : LSX2RI7_VVVI<0x73420000>; 728def VSRANI_B_H : LSX2RI4_VVVI<0x73584000>; 729def VSRANI_H_W : LSX2RI5_VVVI<0x73588000>; 730def VSRANI_W_D : LSX2RI6_VVVI<0x73590000>; 731def VSRANI_D_Q : LSX2RI7_VVVI<0x735a0000>; 732 733def VSRLRN_B_H : LSX3R_VVV<0x70f88000>; 734def VSRLRN_H_W : LSX3R_VVV<0x70f90000>; 735def VSRLRN_W_D : LSX3R_VVV<0x70f98000>; 736def VSRARN_B_H : LSX3R_VVV<0x70fa8000>; 737def VSRARN_H_W : LSX3R_VVV<0x70fb0000>; 738def VSRARN_W_D : LSX3R_VVV<0x70fb8000>; 739 740def VSRLRNI_B_H : LSX2RI4_VVVI<0x73444000>; 741def VSRLRNI_H_W : LSX2RI5_VVVI<0x73448000>; 742def VSRLRNI_W_D : LSX2RI6_VVVI<0x73450000>; 743def VSRLRNI_D_Q : LSX2RI7_VVVI<0x73460000>; 744def VSRARNI_B_H : LSX2RI4_VVVI<0x735c4000>; 745def VSRARNI_H_W : LSX2RI5_VVVI<0x735c8000>; 746def VSRARNI_W_D : LSX2RI6_VVVI<0x735d0000>; 747def VSRARNI_D_Q : LSX2RI7_VVVI<0x735e0000>; 748 749def VSSRLN_B_H : LSX3R_VVV<0x70fc8000>; 750def VSSRLN_H_W : LSX3R_VVV<0x70fd0000>; 751def VSSRLN_W_D : LSX3R_VVV<0x70fd8000>; 752def VSSRAN_B_H : LSX3R_VVV<0x70fe8000>; 753def VSSRAN_H_W : LSX3R_VVV<0x70ff0000>; 754def VSSRAN_W_D : LSX3R_VVV<0x70ff8000>; 755def VSSRLN_BU_H : LSX3R_VVV<0x71048000>; 756def VSSRLN_HU_W : LSX3R_VVV<0x71050000>; 757def VSSRLN_WU_D : LSX3R_VVV<0x71058000>; 758def VSSRAN_BU_H : LSX3R_VVV<0x71068000>; 759def VSSRAN_HU_W : LSX3R_VVV<0x71070000>; 760def VSSRAN_WU_D : LSX3R_VVV<0x71078000>; 761 762def VSSRLNI_B_H : LSX2RI4_VVVI<0x73484000>; 763def VSSRLNI_H_W : LSX2RI5_VVVI<0x73488000>; 764def VSSRLNI_W_D : LSX2RI6_VVVI<0x73490000>; 765def VSSRLNI_D_Q : LSX2RI7_VVVI<0x734a0000>; 766def VSSRANI_B_H : LSX2RI4_VVVI<0x73604000>; 767def VSSRANI_H_W : LSX2RI5_VVVI<0x73608000>; 768def VSSRANI_W_D : LSX2RI6_VVVI<0x73610000>; 769def VSSRANI_D_Q : LSX2RI7_VVVI<0x73620000>; 770def VSSRLNI_BU_H : LSX2RI4_VVVI<0x734c4000>; 771def VSSRLNI_HU_W : LSX2RI5_VVVI<0x734c8000>; 772def VSSRLNI_WU_D : LSX2RI6_VVVI<0x734d0000>; 773def VSSRLNI_DU_Q : LSX2RI7_VVVI<0x734e0000>; 774def VSSRANI_BU_H : LSX2RI4_VVVI<0x73644000>; 775def VSSRANI_HU_W : LSX2RI5_VVVI<0x73648000>; 776def VSSRANI_WU_D : LSX2RI6_VVVI<0x73650000>; 777def VSSRANI_DU_Q : LSX2RI7_VVVI<0x73660000>; 778 779def VSSRLRN_B_H : LSX3R_VVV<0x71008000>; 780def VSSRLRN_H_W : LSX3R_VVV<0x71010000>; 781def VSSRLRN_W_D : LSX3R_VVV<0x71018000>; 782def VSSRARN_B_H : LSX3R_VVV<0x71028000>; 783def VSSRARN_H_W : LSX3R_VVV<0x71030000>; 784def VSSRARN_W_D : LSX3R_VVV<0x71038000>; 785def VSSRLRN_BU_H : LSX3R_VVV<0x71088000>; 786def VSSRLRN_HU_W : LSX3R_VVV<0x71090000>; 787def VSSRLRN_WU_D : LSX3R_VVV<0x71098000>; 788def VSSRARN_BU_H : LSX3R_VVV<0x710a8000>; 789def VSSRARN_HU_W : LSX3R_VVV<0x710b0000>; 790def VSSRARN_WU_D : LSX3R_VVV<0x710b8000>; 791 792def VSSRLRNI_B_H : LSX2RI4_VVVI<0x73504000>; 793def VSSRLRNI_H_W : LSX2RI5_VVVI<0x73508000>; 794def VSSRLRNI_W_D : LSX2RI6_VVVI<0x73510000>; 795def VSSRLRNI_D_Q : LSX2RI7_VVVI<0x73520000>; 796def VSSRARNI_B_H : LSX2RI4_VVVI<0x73684000>; 797def VSSRARNI_H_W : LSX2RI5_VVVI<0x73688000>; 798def VSSRARNI_W_D : LSX2RI6_VVVI<0x73690000>; 799def VSSRARNI_D_Q : LSX2RI7_VVVI<0x736a0000>; 800def VSSRLRNI_BU_H : LSX2RI4_VVVI<0x73544000>; 801def VSSRLRNI_HU_W : LSX2RI5_VVVI<0x73548000>; 802def VSSRLRNI_WU_D : LSX2RI6_VVVI<0x73550000>; 803def VSSRLRNI_DU_Q : LSX2RI7_VVVI<0x73560000>; 804def VSSRARNI_BU_H : LSX2RI4_VVVI<0x736c4000>; 805def VSSRARNI_HU_W : LSX2RI5_VVVI<0x736c8000>; 806def VSSRARNI_WU_D : LSX2RI6_VVVI<0x736d0000>; 807def VSSRARNI_DU_Q : LSX2RI7_VVVI<0x736e0000>; 808 809def VCLO_B : LSX2R_VV<0x729c0000>; 810def VCLO_H : LSX2R_VV<0x729c0400>; 811def VCLO_W : LSX2R_VV<0x729c0800>; 812def VCLO_D : LSX2R_VV<0x729c0c00>; 813def VCLZ_B : LSX2R_VV<0x729c1000>; 814def VCLZ_H : LSX2R_VV<0x729c1400>; 815def VCLZ_W : LSX2R_VV<0x729c1800>; 816def VCLZ_D : LSX2R_VV<0x729c1c00>; 817 818def VPCNT_B : LSX2R_VV<0x729c2000>; 819def VPCNT_H : LSX2R_VV<0x729c2400>; 820def VPCNT_W : LSX2R_VV<0x729c2800>; 821def VPCNT_D : LSX2R_VV<0x729c2c00>; 822 823def VBITCLR_B : LSX3R_VVV<0x710c0000>; 824def VBITCLR_H : LSX3R_VVV<0x710c8000>; 825def VBITCLR_W : LSX3R_VVV<0x710d0000>; 826def VBITCLR_D : LSX3R_VVV<0x710d8000>; 827def VBITCLRI_B : LSX2RI3_VVI<0x73102000>; 828def VBITCLRI_H : LSX2RI4_VVI<0x73104000>; 829def VBITCLRI_W : LSX2RI5_VVI<0x73108000>; 830def VBITCLRI_D : LSX2RI6_VVI<0x73110000>; 831 832def VBITSET_B : LSX3R_VVV<0x710e0000>; 833def VBITSET_H : LSX3R_VVV<0x710e8000>; 834def VBITSET_W : LSX3R_VVV<0x710f0000>; 835def VBITSET_D : LSX3R_VVV<0x710f8000>; 836def VBITSETI_B : LSX2RI3_VVI<0x73142000>; 837def VBITSETI_H : LSX2RI4_VVI<0x73144000>; 838def VBITSETI_W : LSX2RI5_VVI<0x73148000>; 839def VBITSETI_D : LSX2RI6_VVI<0x73150000>; 840 841def VBITREV_B : LSX3R_VVV<0x71100000>; 842def VBITREV_H : LSX3R_VVV<0x71108000>; 843def VBITREV_W : LSX3R_VVV<0x71110000>; 844def VBITREV_D : LSX3R_VVV<0x71118000>; 845def VBITREVI_B : LSX2RI3_VVI<0x73182000>; 846def VBITREVI_H : LSX2RI4_VVI<0x73184000>; 847def VBITREVI_W : LSX2RI5_VVI<0x73188000>; 848def VBITREVI_D : LSX2RI6_VVI<0x73190000>; 849 850def VFRSTP_B : LSX3R_VVVV<0x712b0000>; 851def VFRSTP_H : LSX3R_VVVV<0x712b8000>; 852def VFRSTPI_B : LSX2RI5_VVVI<0x729a0000>; 853def VFRSTPI_H : LSX2RI5_VVVI<0x729a8000>; 854 855def VFADD_S : LSX3R_VVV<0x71308000>; 856def VFADD_D : LSX3R_VVV<0x71310000>; 857def VFSUB_S : LSX3R_VVV<0x71328000>; 858def VFSUB_D : LSX3R_VVV<0x71330000>; 859def VFMUL_S : LSX3R_VVV<0x71388000>; 860def VFMUL_D : LSX3R_VVV<0x71390000>; 861def VFDIV_S : LSX3R_VVV<0x713a8000>; 862def VFDIV_D : LSX3R_VVV<0x713b0000>; 863 864def VFMADD_S : LSX4R_VVVV<0x09100000>; 865def VFMADD_D : LSX4R_VVVV<0x09200000>; 866def VFMSUB_S : LSX4R_VVVV<0x09500000>; 867def VFMSUB_D : LSX4R_VVVV<0x09600000>; 868def VFNMADD_S : LSX4R_VVVV<0x09900000>; 869def VFNMADD_D : LSX4R_VVVV<0x09a00000>; 870def VFNMSUB_S : LSX4R_VVVV<0x09d00000>; 871def VFNMSUB_D : LSX4R_VVVV<0x09e00000>; 872 873def VFMAX_S : LSX3R_VVV<0x713c8000>; 874def VFMAX_D : LSX3R_VVV<0x713d0000>; 875def VFMIN_S : LSX3R_VVV<0x713e8000>; 876def VFMIN_D : LSX3R_VVV<0x713f0000>; 877 878def VFMAXA_S : LSX3R_VVV<0x71408000>; 879def VFMAXA_D : LSX3R_VVV<0x71410000>; 880def VFMINA_S : LSX3R_VVV<0x71428000>; 881def VFMINA_D : LSX3R_VVV<0x71430000>; 882 883def VFLOGB_S : LSX2R_VV<0x729cc400>; 884def VFLOGB_D : LSX2R_VV<0x729cc800>; 885 886def VFCLASS_S : LSX2R_VV<0x729cd400>; 887def VFCLASS_D : LSX2R_VV<0x729cd800>; 888 889def VFSQRT_S : LSX2R_VV<0x729ce400>; 890def VFSQRT_D : LSX2R_VV<0x729ce800>; 891def VFRECIP_S : LSX2R_VV<0x729cf400>; 892def VFRECIP_D : LSX2R_VV<0x729cf800>; 893def VFRSQRT_S : LSX2R_VV<0x729d0400>; 894def VFRSQRT_D : LSX2R_VV<0x729d0800>; 895 896def VFCVTL_S_H : LSX2R_VV<0x729de800>; 897def VFCVTH_S_H : LSX2R_VV<0x729dec00>; 898def VFCVTL_D_S : LSX2R_VV<0x729df000>; 899def VFCVTH_D_S : LSX2R_VV<0x729df400>; 900def VFCVT_H_S : LSX3R_VVV<0x71460000>; 901def VFCVT_S_D : LSX3R_VVV<0x71468000>; 902 903def VFRINTRNE_S : LSX2R_VV<0x729d7400>; 904def VFRINTRNE_D : LSX2R_VV<0x729d7800>; 905def VFRINTRZ_S : LSX2R_VV<0x729d6400>; 906def VFRINTRZ_D : LSX2R_VV<0x729d6800>; 907def VFRINTRP_S : LSX2R_VV<0x729d5400>; 908def VFRINTRP_D : LSX2R_VV<0x729d5800>; 909def VFRINTRM_S : LSX2R_VV<0x729d4400>; 910def VFRINTRM_D : LSX2R_VV<0x729d4800>; 911def VFRINT_S : LSX2R_VV<0x729d3400>; 912def VFRINT_D : LSX2R_VV<0x729d3800>; 913 914def VFTINTRNE_W_S : LSX2R_VV<0x729e5000>; 915def VFTINTRNE_L_D : LSX2R_VV<0x729e5400>; 916def VFTINTRZ_W_S : LSX2R_VV<0x729e4800>; 917def VFTINTRZ_L_D : LSX2R_VV<0x729e4c00>; 918def VFTINTRP_W_S : LSX2R_VV<0x729e4000>; 919def VFTINTRP_L_D : LSX2R_VV<0x729e4400>; 920def VFTINTRM_W_S : LSX2R_VV<0x729e3800>; 921def VFTINTRM_L_D : LSX2R_VV<0x729e3c00>; 922def VFTINT_W_S : LSX2R_VV<0x729e3000>; 923def VFTINT_L_D : LSX2R_VV<0x729e3400>; 924def VFTINTRZ_WU_S : LSX2R_VV<0x729e7000>; 925def VFTINTRZ_LU_D : LSX2R_VV<0x729e7400>; 926def VFTINT_WU_S : LSX2R_VV<0x729e5800>; 927def VFTINT_LU_D : LSX2R_VV<0x729e5c00>; 928 929def VFTINTRNE_W_D : LSX3R_VVV<0x714b8000>; 930def VFTINTRZ_W_D : LSX3R_VVV<0x714b0000>; 931def VFTINTRP_W_D : LSX3R_VVV<0x714a8000>; 932def VFTINTRM_W_D : LSX3R_VVV<0x714a0000>; 933def VFTINT_W_D : LSX3R_VVV<0x71498000>; 934 935def VFTINTRNEL_L_S : LSX2R_VV<0x729ea000>; 936def VFTINTRNEH_L_S : LSX2R_VV<0x729ea400>; 937def VFTINTRZL_L_S : LSX2R_VV<0x729e9800>; 938def VFTINTRZH_L_S : LSX2R_VV<0x729e9c00>; 939def VFTINTRPL_L_S : LSX2R_VV<0x729e9000>; 940def VFTINTRPH_L_S : LSX2R_VV<0x729e9400>; 941def VFTINTRML_L_S : LSX2R_VV<0x729e8800>; 942def VFTINTRMH_L_S : LSX2R_VV<0x729e8c00>; 943def VFTINTL_L_S : LSX2R_VV<0x729e8000>; 944def VFTINTH_L_S : LSX2R_VV<0x729e8400>; 945 946def VFFINT_S_W : LSX2R_VV<0x729e0000>; 947def VFFINT_D_L : LSX2R_VV<0x729e0800>; 948def VFFINT_S_WU : LSX2R_VV<0x729e0400>; 949def VFFINT_D_LU : LSX2R_VV<0x729e0c00>; 950def VFFINTL_D_W : LSX2R_VV<0x729e1000>; 951def VFFINTH_D_W : LSX2R_VV<0x729e1400>; 952def VFFINT_S_L : LSX3R_VVV<0x71480000>; 953 954def VSEQ_B : LSX3R_VVV<0x70000000>; 955def VSEQ_H : LSX3R_VVV<0x70008000>; 956def VSEQ_W : LSX3R_VVV<0x70010000>; 957def VSEQ_D : LSX3R_VVV<0x70018000>; 958def VSEQI_B : LSX2RI5_VVI<0x72800000, simm5>; 959def VSEQI_H : LSX2RI5_VVI<0x72808000, simm5>; 960def VSEQI_W : LSX2RI5_VVI<0x72810000, simm5>; 961def VSEQI_D : LSX2RI5_VVI<0x72818000, simm5>; 962 963def VSLE_B : LSX3R_VVV<0x70020000>; 964def VSLE_H : LSX3R_VVV<0x70028000>; 965def VSLE_W : LSX3R_VVV<0x70030000>; 966def VSLE_D : LSX3R_VVV<0x70038000>; 967def VSLEI_B : LSX2RI5_VVI<0x72820000, simm5>; 968def VSLEI_H : LSX2RI5_VVI<0x72828000, simm5>; 969def VSLEI_W : LSX2RI5_VVI<0x72830000, simm5>; 970def VSLEI_D : LSX2RI5_VVI<0x72838000, simm5>; 971 972def VSLE_BU : LSX3R_VVV<0x70040000>; 973def VSLE_HU : LSX3R_VVV<0x70048000>; 974def VSLE_WU : LSX3R_VVV<0x70050000>; 975def VSLE_DU : LSX3R_VVV<0x70058000>; 976def VSLEI_BU : LSX2RI5_VVI<0x72840000>; 977def VSLEI_HU : LSX2RI5_VVI<0x72848000>; 978def VSLEI_WU : LSX2RI5_VVI<0x72850000>; 979def VSLEI_DU : LSX2RI5_VVI<0x72858000>; 980 981def VSLT_B : LSX3R_VVV<0x70060000>; 982def VSLT_H : LSX3R_VVV<0x70068000>; 983def VSLT_W : LSX3R_VVV<0x70070000>; 984def VSLT_D : LSX3R_VVV<0x70078000>; 985def VSLTI_B : LSX2RI5_VVI<0x72860000, simm5>; 986def VSLTI_H : LSX2RI5_VVI<0x72868000, simm5>; 987def VSLTI_W : LSX2RI5_VVI<0x72870000, simm5>; 988def VSLTI_D : LSX2RI5_VVI<0x72878000, simm5>; 989 990def VSLT_BU : LSX3R_VVV<0x70080000>; 991def VSLT_HU : LSX3R_VVV<0x70088000>; 992def VSLT_WU : LSX3R_VVV<0x70090000>; 993def VSLT_DU : LSX3R_VVV<0x70098000>; 994def VSLTI_BU : LSX2RI5_VVI<0x72880000>; 995def VSLTI_HU : LSX2RI5_VVI<0x72888000>; 996def VSLTI_WU : LSX2RI5_VVI<0x72890000>; 997def VSLTI_DU : LSX2RI5_VVI<0x72898000>; 998 999def VFCMP_CAF_S : LSX3R_VVV<0x0c500000>; 1000def VFCMP_SAF_S : LSX3R_VVV<0x0c508000>; 1001def VFCMP_CLT_S : LSX3R_VVV<0x0c510000>; 1002def VFCMP_SLT_S : LSX3R_VVV<0x0c518000>; 1003def VFCMP_CEQ_S : LSX3R_VVV<0x0c520000>; 1004def VFCMP_SEQ_S : LSX3R_VVV<0x0c528000>; 1005def VFCMP_CLE_S : LSX3R_VVV<0x0c530000>; 1006def VFCMP_SLE_S : LSX3R_VVV<0x0c538000>; 1007def VFCMP_CUN_S : LSX3R_VVV<0x0c540000>; 1008def VFCMP_SUN_S : LSX3R_VVV<0x0c548000>; 1009def VFCMP_CULT_S : LSX3R_VVV<0x0c550000>; 1010def VFCMP_SULT_S : LSX3R_VVV<0x0c558000>; 1011def VFCMP_CUEQ_S : LSX3R_VVV<0x0c560000>; 1012def VFCMP_SUEQ_S : LSX3R_VVV<0x0c568000>; 1013def VFCMP_CULE_S : LSX3R_VVV<0x0c570000>; 1014def VFCMP_SULE_S : LSX3R_VVV<0x0c578000>; 1015def VFCMP_CNE_S : LSX3R_VVV<0x0c580000>; 1016def VFCMP_SNE_S : LSX3R_VVV<0x0c588000>; 1017def VFCMP_COR_S : LSX3R_VVV<0x0c5a0000>; 1018def VFCMP_SOR_S : LSX3R_VVV<0x0c5a8000>; 1019def VFCMP_CUNE_S : LSX3R_VVV<0x0c5c0000>; 1020def VFCMP_SUNE_S : LSX3R_VVV<0x0c5c8000>; 1021 1022def VFCMP_CAF_D : LSX3R_VVV<0x0c600000>; 1023def VFCMP_SAF_D : LSX3R_VVV<0x0c608000>; 1024def VFCMP_CLT_D : LSX3R_VVV<0x0c610000>; 1025def VFCMP_SLT_D : LSX3R_VVV<0x0c618000>; 1026def VFCMP_CEQ_D : LSX3R_VVV<0x0c620000>; 1027def VFCMP_SEQ_D : LSX3R_VVV<0x0c628000>; 1028def VFCMP_CLE_D : LSX3R_VVV<0x0c630000>; 1029def VFCMP_SLE_D : LSX3R_VVV<0x0c638000>; 1030def VFCMP_CUN_D : LSX3R_VVV<0x0c640000>; 1031def VFCMP_SUN_D : LSX3R_VVV<0x0c648000>; 1032def VFCMP_CULT_D : LSX3R_VVV<0x0c650000>; 1033def VFCMP_SULT_D : LSX3R_VVV<0x0c658000>; 1034def VFCMP_CUEQ_D : LSX3R_VVV<0x0c660000>; 1035def VFCMP_SUEQ_D : LSX3R_VVV<0x0c668000>; 1036def VFCMP_CULE_D : LSX3R_VVV<0x0c670000>; 1037def VFCMP_SULE_D : LSX3R_VVV<0x0c678000>; 1038def VFCMP_CNE_D : LSX3R_VVV<0x0c680000>; 1039def VFCMP_SNE_D : LSX3R_VVV<0x0c688000>; 1040def VFCMP_COR_D : LSX3R_VVV<0x0c6a0000>; 1041def VFCMP_SOR_D : LSX3R_VVV<0x0c6a8000>; 1042def VFCMP_CUNE_D : LSX3R_VVV<0x0c6c0000>; 1043def VFCMP_SUNE_D : LSX3R_VVV<0x0c6c8000>; 1044 1045def VBITSEL_V : LSX4R_VVVV<0x0d100000>; 1046 1047def VBITSELI_B : LSX2RI8_VVVI<0x73c40000>; 1048 1049def VSETEQZ_V : LSX2R_CV<0x729c9800>; 1050def VSETNEZ_V : LSX2R_CV<0x729c9c00>; 1051def VSETANYEQZ_B : LSX2R_CV<0x729ca000>; 1052def VSETANYEQZ_H : LSX2R_CV<0x729ca400>; 1053def VSETANYEQZ_W : LSX2R_CV<0x729ca800>; 1054def VSETANYEQZ_D : LSX2R_CV<0x729cac00>; 1055def VSETALLNEZ_B : LSX2R_CV<0x729cb000>; 1056def VSETALLNEZ_H : LSX2R_CV<0x729cb400>; 1057def VSETALLNEZ_W : LSX2R_CV<0x729cb800>; 1058def VSETALLNEZ_D : LSX2R_CV<0x729cbc00>; 1059 1060def VINSGR2VR_B : LSX2RI4_VVRI<0x72eb8000>; 1061def VINSGR2VR_H : LSX2RI3_VVRI<0x72ebc000>; 1062def VINSGR2VR_W : LSX2RI2_VVRI<0x72ebe000>; 1063def VINSGR2VR_D : LSX2RI1_VVRI<0x72ebf000>; 1064def VPICKVE2GR_B : LSX2RI4_RVI<0x72ef8000>; 1065def VPICKVE2GR_H : LSX2RI3_RVI<0x72efc000>; 1066def VPICKVE2GR_W : LSX2RI2_RVI<0x72efe000>; 1067def VPICKVE2GR_D : LSX2RI1_RVI<0x72eff000>; 1068def VPICKVE2GR_BU : LSX2RI4_RVI<0x72f38000>; 1069def VPICKVE2GR_HU : LSX2RI3_RVI<0x72f3c000>; 1070def VPICKVE2GR_WU : LSX2RI2_RVI<0x72f3e000>; 1071def VPICKVE2GR_DU : LSX2RI1_RVI<0x72f3f000>; 1072 1073def VREPLGR2VR_B : LSX2R_VR<0x729f0000>; 1074def VREPLGR2VR_H : LSX2R_VR<0x729f0400>; 1075def VREPLGR2VR_W : LSX2R_VR<0x729f0800>; 1076def VREPLGR2VR_D : LSX2R_VR<0x729f0c00>; 1077 1078def VREPLVE_B : LSX3R_VVR<0x71220000>; 1079def VREPLVE_H : LSX3R_VVR<0x71228000>; 1080def VREPLVE_W : LSX3R_VVR<0x71230000>; 1081def VREPLVE_D : LSX3R_VVR<0x71238000>; 1082def VREPLVEI_B : LSX2RI4_VVI<0x72f78000>; 1083def VREPLVEI_H : LSX2RI3_VVI<0x72f7c000>; 1084def VREPLVEI_W : LSX2RI2_VVI<0x72f7e000>; 1085def VREPLVEI_D : LSX2RI1_VVI<0x72f7f000>; 1086 1087def VBSLL_V : LSX2RI5_VVI<0x728e0000>; 1088def VBSRL_V : LSX2RI5_VVI<0x728e8000>; 1089 1090def VPACKEV_B : LSX3R_VVV<0x71160000>; 1091def VPACKEV_H : LSX3R_VVV<0x71168000>; 1092def VPACKEV_W : LSX3R_VVV<0x71170000>; 1093def VPACKEV_D : LSX3R_VVV<0x71178000>; 1094def VPACKOD_B : LSX3R_VVV<0x71180000>; 1095def VPACKOD_H : LSX3R_VVV<0x71188000>; 1096def VPACKOD_W : LSX3R_VVV<0x71190000>; 1097def VPACKOD_D : LSX3R_VVV<0x71198000>; 1098 1099def VPICKEV_B : LSX3R_VVV<0x711e0000>; 1100def VPICKEV_H : LSX3R_VVV<0x711e8000>; 1101def VPICKEV_W : LSX3R_VVV<0x711f0000>; 1102def VPICKEV_D : LSX3R_VVV<0x711f8000>; 1103def VPICKOD_B : LSX3R_VVV<0x71200000>; 1104def VPICKOD_H : LSX3R_VVV<0x71208000>; 1105def VPICKOD_W : LSX3R_VVV<0x71210000>; 1106def VPICKOD_D : LSX3R_VVV<0x71218000>; 1107 1108def VILVL_B : LSX3R_VVV<0x711a0000>; 1109def VILVL_H : LSX3R_VVV<0x711a8000>; 1110def VILVL_W : LSX3R_VVV<0x711b0000>; 1111def VILVL_D : LSX3R_VVV<0x711b8000>; 1112def VILVH_B : LSX3R_VVV<0x711c0000>; 1113def VILVH_H : LSX3R_VVV<0x711c8000>; 1114def VILVH_W : LSX3R_VVV<0x711d0000>; 1115def VILVH_D : LSX3R_VVV<0x711d8000>; 1116 1117def VSHUF_B : LSX4R_VVVV<0x0d500000>; 1118 1119def VSHUF_H : LSX3R_VVVV<0x717a8000>; 1120def VSHUF_W : LSX3R_VVVV<0x717b0000>; 1121def VSHUF_D : LSX3R_VVVV<0x717b8000>; 1122 1123def VSHUF4I_B : LSX2RI8_VVI<0x73900000>; 1124def VSHUF4I_H : LSX2RI8_VVI<0x73940000>; 1125def VSHUF4I_W : LSX2RI8_VVI<0x73980000>; 1126def VSHUF4I_D : LSX2RI8_VVVI<0x739c0000>; 1127 1128def VPERMI_W : LSX2RI8_VVVI<0x73e40000>; 1129 1130def VEXTRINS_D : LSX2RI8_VVVI<0x73800000>; 1131def VEXTRINS_W : LSX2RI8_VVVI<0x73840000>; 1132def VEXTRINS_H : LSX2RI8_VVVI<0x73880000>; 1133def VEXTRINS_B : LSX2RI8_VVVI<0x738c0000>; 1134} // mayLoad = 0, mayStore = 0 1135 1136let mayLoad = 1, mayStore = 0 in { 1137def VLD : LSX2RI12_Load<0x2c000000>; 1138def VLDX : LSX3R_Load<0x38400000>; 1139 1140def VLDREPL_B : LSX2RI12_Load<0x30800000>; 1141def VLDREPL_H : LSX2RI11_Load<0x30400000>; 1142def VLDREPL_W : LSX2RI10_Load<0x30200000>; 1143def VLDREPL_D : LSX2RI9_Load<0x30100000>; 1144} // mayLoad = 1, mayStore = 0 1145 1146let mayLoad = 0, mayStore = 1 in { 1147def VST : LSX2RI12_Store<0x2c400000>; 1148def VSTX : LSX3R_Store<0x38440000>; 1149 1150def VSTELM_B : LSX2RI8I4_VRII<0x31800000>; 1151def VSTELM_H : LSX2RI8I3_VRII<0x31400000, simm8_lsl1>; 1152def VSTELM_W : LSX2RI8I2_VRII<0x31200000, simm8_lsl2>; 1153def VSTELM_D : LSX2RI8I1_VRII<0x31100000, simm8_lsl3>; 1154} // mayLoad = 0, mayStore = 1 1155 1156} // hasSideEffects = 0, Predicates = [HasExtLSX] 1157 1158/// Pseudo-instructions 1159 1160let Predicates = [HasExtLSX] in { 1161 1162let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 0, 1163 isAsmParserOnly = 1 in { 1164def PseudoVREPLI_B : Pseudo<(outs LSX128:$vd), (ins simm10:$imm), [], 1165 "vrepli.b", "$vd, $imm">; 1166def PseudoVREPLI_H : Pseudo<(outs LSX128:$vd), (ins simm10:$imm), [], 1167 "vrepli.h", "$vd, $imm">; 1168def PseudoVREPLI_W : Pseudo<(outs LSX128:$vd), (ins simm10:$imm), [], 1169 "vrepli.w", "$vd, $imm">; 1170def PseudoVREPLI_D : Pseudo<(outs LSX128:$vd), (ins simm10:$imm), [], 1171 "vrepli.d", "$vd, $imm">; 1172} 1173 1174def PseudoVBNZ_B : VecCond<loongarch_vall_nonzero, v16i8>; 1175def PseudoVBNZ_H : VecCond<loongarch_vall_nonzero, v8i16>; 1176def PseudoVBNZ_W : VecCond<loongarch_vall_nonzero, v4i32>; 1177def PseudoVBNZ_D : VecCond<loongarch_vall_nonzero, v2i64>; 1178def PseudoVBNZ : VecCond<loongarch_vany_nonzero, v16i8>; 1179 1180def PseudoVBZ_B : VecCond<loongarch_vall_zero, v16i8>; 1181def PseudoVBZ_H : VecCond<loongarch_vall_zero, v8i16>; 1182def PseudoVBZ_W : VecCond<loongarch_vall_zero, v4i32>; 1183def PseudoVBZ_D : VecCond<loongarch_vall_zero, v2i64>; 1184def PseudoVBZ : VecCond<loongarch_vany_zero, v16i8>; 1185 1186} // Predicates = [HasExtLSX] 1187 1188multiclass PatVr<SDPatternOperator OpNode, string Inst> { 1189 def : Pat<(v16i8 (OpNode (v16i8 LSX128:$vj))), 1190 (!cast<LAInst>(Inst#"_B") LSX128:$vj)>; 1191 def : Pat<(v8i16 (OpNode (v8i16 LSX128:$vj))), 1192 (!cast<LAInst>(Inst#"_H") LSX128:$vj)>; 1193 def : Pat<(v4i32 (OpNode (v4i32 LSX128:$vj))), 1194 (!cast<LAInst>(Inst#"_W") LSX128:$vj)>; 1195 def : Pat<(v2i64 (OpNode (v2i64 LSX128:$vj))), 1196 (!cast<LAInst>(Inst#"_D") LSX128:$vj)>; 1197} 1198 1199multiclass PatVrF<SDPatternOperator OpNode, string Inst> { 1200 def : Pat<(v4f32 (OpNode (v4f32 LSX128:$vj))), 1201 (!cast<LAInst>(Inst#"_S") LSX128:$vj)>; 1202 def : Pat<(v2f64 (OpNode (v2f64 LSX128:$vj))), 1203 (!cast<LAInst>(Inst#"_D") LSX128:$vj)>; 1204} 1205 1206multiclass PatVrVr<SDPatternOperator OpNode, string Inst> { 1207 def : Pat<(OpNode (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)), 1208 (!cast<LAInst>(Inst#"_B") LSX128:$vj, LSX128:$vk)>; 1209 def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)), 1210 (!cast<LAInst>(Inst#"_H") LSX128:$vj, LSX128:$vk)>; 1211 def : Pat<(OpNode (v4i32 LSX128:$vj), (v4i32 LSX128:$vk)), 1212 (!cast<LAInst>(Inst#"_W") LSX128:$vj, LSX128:$vk)>; 1213 def : Pat<(OpNode (v2i64 LSX128:$vj), (v2i64 LSX128:$vk)), 1214 (!cast<LAInst>(Inst#"_D") LSX128:$vj, LSX128:$vk)>; 1215} 1216 1217multiclass PatVrVrF<SDPatternOperator OpNode, string Inst> { 1218 def : Pat<(OpNode (v4f32 LSX128:$vj), (v4f32 LSX128:$vk)), 1219 (!cast<LAInst>(Inst#"_S") LSX128:$vj, LSX128:$vk)>; 1220 def : Pat<(OpNode (v2f64 LSX128:$vj), (v2f64 LSX128:$vk)), 1221 (!cast<LAInst>(Inst#"_D") LSX128:$vj, LSX128:$vk)>; 1222} 1223 1224multiclass PatVrVrU<SDPatternOperator OpNode, string Inst> { 1225 def : Pat<(OpNode (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)), 1226 (!cast<LAInst>(Inst#"_BU") LSX128:$vj, LSX128:$vk)>; 1227 def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)), 1228 (!cast<LAInst>(Inst#"_HU") LSX128:$vj, LSX128:$vk)>; 1229 def : Pat<(OpNode (v4i32 LSX128:$vj), (v4i32 LSX128:$vk)), 1230 (!cast<LAInst>(Inst#"_WU") LSX128:$vj, LSX128:$vk)>; 1231 def : Pat<(OpNode (v2i64 LSX128:$vj), (v2i64 LSX128:$vk)), 1232 (!cast<LAInst>(Inst#"_DU") LSX128:$vj, LSX128:$vk)>; 1233} 1234 1235multiclass PatVrSimm5<SDPatternOperator OpNode, string Inst> { 1236 def : Pat<(OpNode (v16i8 LSX128:$vj), (v16i8 (SplatPat_simm5 simm5:$imm))), 1237 (!cast<LAInst>(Inst#"_B") LSX128:$vj, simm5:$imm)>; 1238 def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 (SplatPat_simm5 simm5:$imm))), 1239 (!cast<LAInst>(Inst#"_H") LSX128:$vj, simm5:$imm)>; 1240 def : Pat<(OpNode (v4i32 LSX128:$vj), (v4i32 (SplatPat_simm5 simm5:$imm))), 1241 (!cast<LAInst>(Inst#"_W") LSX128:$vj, simm5:$imm)>; 1242 def : Pat<(OpNode (v2i64 LSX128:$vj), (v2i64 (SplatPat_simm5 simm5:$imm))), 1243 (!cast<LAInst>(Inst#"_D") LSX128:$vj, simm5:$imm)>; 1244} 1245 1246multiclass PatVrUimm5<SDPatternOperator OpNode, string Inst> { 1247 def : Pat<(OpNode (v16i8 LSX128:$vj), (v16i8 (SplatPat_uimm5 uimm5:$imm))), 1248 (!cast<LAInst>(Inst#"_BU") LSX128:$vj, uimm5:$imm)>; 1249 def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 (SplatPat_uimm5 uimm5:$imm))), 1250 (!cast<LAInst>(Inst#"_HU") LSX128:$vj, uimm5:$imm)>; 1251 def : Pat<(OpNode (v4i32 LSX128:$vj), (v4i32 (SplatPat_uimm5 uimm5:$imm))), 1252 (!cast<LAInst>(Inst#"_WU") LSX128:$vj, uimm5:$imm)>; 1253 def : Pat<(OpNode (v2i64 LSX128:$vj), (v2i64 (SplatPat_uimm5 uimm5:$imm))), 1254 (!cast<LAInst>(Inst#"_DU") LSX128:$vj, uimm5:$imm)>; 1255} 1256 1257multiclass PatVrVrVr<SDPatternOperator OpNode, string Inst> { 1258 def : Pat<(OpNode (v16i8 LSX128:$vd), (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)), 1259 (!cast<LAInst>(Inst#"_B") LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 1260 def : Pat<(OpNode (v8i16 LSX128:$vd), (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)), 1261 (!cast<LAInst>(Inst#"_H") LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 1262 def : Pat<(OpNode (v4i32 LSX128:$vd), (v4i32 LSX128:$vj), (v4i32 LSX128:$vk)), 1263 (!cast<LAInst>(Inst#"_W") LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 1264 def : Pat<(OpNode (v2i64 LSX128:$vd), (v2i64 LSX128:$vj), (v2i64 LSX128:$vk)), 1265 (!cast<LAInst>(Inst#"_D") LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 1266} 1267 1268multiclass PatShiftVrVr<SDPatternOperator OpNode, string Inst> { 1269 def : Pat<(OpNode (v16i8 LSX128:$vj), (and vsplati8_imm_eq_7, 1270 (v16i8 LSX128:$vk))), 1271 (!cast<LAInst>(Inst#"_B") LSX128:$vj, LSX128:$vk)>; 1272 def : Pat<(OpNode (v8i16 LSX128:$vj), (and vsplati16_imm_eq_15, 1273 (v8i16 LSX128:$vk))), 1274 (!cast<LAInst>(Inst#"_H") LSX128:$vj, LSX128:$vk)>; 1275 def : Pat<(OpNode (v4i32 LSX128:$vj), (and vsplati32_imm_eq_31, 1276 (v4i32 LSX128:$vk))), 1277 (!cast<LAInst>(Inst#"_W") LSX128:$vj, LSX128:$vk)>; 1278 def : Pat<(OpNode (v2i64 LSX128:$vj), (and vsplati64_imm_eq_63, 1279 (v2i64 LSX128:$vk))), 1280 (!cast<LAInst>(Inst#"_D") LSX128:$vj, LSX128:$vk)>; 1281} 1282 1283multiclass PatShiftVrUimm<SDPatternOperator OpNode, string Inst> { 1284 def : Pat<(OpNode (v16i8 LSX128:$vj), (v16i8 (SplatPat_uimm3 uimm3:$imm))), 1285 (!cast<LAInst>(Inst#"_B") LSX128:$vj, uimm3:$imm)>; 1286 def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 (SplatPat_uimm4 uimm4:$imm))), 1287 (!cast<LAInst>(Inst#"_H") LSX128:$vj, uimm4:$imm)>; 1288 def : Pat<(OpNode (v4i32 LSX128:$vj), (v4i32 (SplatPat_uimm5 uimm5:$imm))), 1289 (!cast<LAInst>(Inst#"_W") LSX128:$vj, uimm5:$imm)>; 1290 def : Pat<(OpNode (v2i64 LSX128:$vj), (v2i64 (SplatPat_uimm6 uimm6:$imm))), 1291 (!cast<LAInst>(Inst#"_D") LSX128:$vj, uimm6:$imm)>; 1292} 1293 1294multiclass PatCCVrSimm5<CondCode CC, string Inst> { 1295 def : Pat<(v16i8 (setcc (v16i8 LSX128:$vj), 1296 (v16i8 (SplatPat_simm5 simm5:$imm)), CC)), 1297 (!cast<LAInst>(Inst#"_B") LSX128:$vj, simm5:$imm)>; 1298 def : Pat<(v8i16 (setcc (v8i16 LSX128:$vj), 1299 (v8i16 (SplatPat_simm5 simm5:$imm)), CC)), 1300 (!cast<LAInst>(Inst#"_H") LSX128:$vj, simm5:$imm)>; 1301 def : Pat<(v4i32 (setcc (v4i32 LSX128:$vj), 1302 (v4i32 (SplatPat_simm5 simm5:$imm)), CC)), 1303 (!cast<LAInst>(Inst#"_W") LSX128:$vj, simm5:$imm)>; 1304 def : Pat<(v2i64 (setcc (v2i64 LSX128:$vj), 1305 (v2i64 (SplatPat_simm5 simm5:$imm)), CC)), 1306 (!cast<LAInst>(Inst#"_D") LSX128:$vj, simm5:$imm)>; 1307} 1308 1309multiclass PatCCVrUimm5<CondCode CC, string Inst> { 1310 def : Pat<(v16i8 (setcc (v16i8 LSX128:$vj), 1311 (v16i8 (SplatPat_uimm5 uimm5:$imm)), CC)), 1312 (!cast<LAInst>(Inst#"_BU") LSX128:$vj, uimm5:$imm)>; 1313 def : Pat<(v8i16 (setcc (v8i16 LSX128:$vj), 1314 (v8i16 (SplatPat_uimm5 uimm5:$imm)), CC)), 1315 (!cast<LAInst>(Inst#"_HU") LSX128:$vj, uimm5:$imm)>; 1316 def : Pat<(v4i32 (setcc (v4i32 LSX128:$vj), 1317 (v4i32 (SplatPat_uimm5 uimm5:$imm)), CC)), 1318 (!cast<LAInst>(Inst#"_WU") LSX128:$vj, uimm5:$imm)>; 1319 def : Pat<(v2i64 (setcc (v2i64 LSX128:$vj), 1320 (v2i64 (SplatPat_uimm5 uimm5:$imm)), CC)), 1321 (!cast<LAInst>(Inst#"_DU") LSX128:$vj, uimm5:$imm)>; 1322} 1323 1324multiclass PatCCVrVr<CondCode CC, string Inst> { 1325 def : Pat<(v16i8 (setcc (v16i8 LSX128:$vj), (v16i8 LSX128:$vk), CC)), 1326 (!cast<LAInst>(Inst#"_B") LSX128:$vj, LSX128:$vk)>; 1327 def : Pat<(v8i16 (setcc (v8i16 LSX128:$vj), (v8i16 LSX128:$vk), CC)), 1328 (!cast<LAInst>(Inst#"_H") LSX128:$vj, LSX128:$vk)>; 1329 def : Pat<(v4i32 (setcc (v4i32 LSX128:$vj), (v4i32 LSX128:$vk), CC)), 1330 (!cast<LAInst>(Inst#"_W") LSX128:$vj, LSX128:$vk)>; 1331 def : Pat<(v2i64 (setcc (v2i64 LSX128:$vj), (v2i64 LSX128:$vk), CC)), 1332 (!cast<LAInst>(Inst#"_D") LSX128:$vj, LSX128:$vk)>; 1333} 1334 1335multiclass PatCCVrVrU<CondCode CC, string Inst> { 1336 def : Pat<(v16i8 (setcc (v16i8 LSX128:$vj), (v16i8 LSX128:$vk), CC)), 1337 (!cast<LAInst>(Inst#"_BU") LSX128:$vj, LSX128:$vk)>; 1338 def : Pat<(v8i16 (setcc (v8i16 LSX128:$vj), (v8i16 LSX128:$vk), CC)), 1339 (!cast<LAInst>(Inst#"_HU") LSX128:$vj, LSX128:$vk)>; 1340 def : Pat<(v4i32 (setcc (v4i32 LSX128:$vj), (v4i32 LSX128:$vk), CC)), 1341 (!cast<LAInst>(Inst#"_WU") LSX128:$vj, LSX128:$vk)>; 1342 def : Pat<(v2i64 (setcc (v2i64 LSX128:$vj), (v2i64 LSX128:$vk), CC)), 1343 (!cast<LAInst>(Inst#"_DU") LSX128:$vj, LSX128:$vk)>; 1344} 1345 1346multiclass PatCCVrVrF<CondCode CC, string Inst> { 1347 def : Pat<(v4i32 (setcc (v4f32 LSX128:$vj), (v4f32 LSX128:$vk), CC)), 1348 (!cast<LAInst>(Inst#"_S") LSX128:$vj, LSX128:$vk)>; 1349 def : Pat<(v2i64 (setcc (v2f64 LSX128:$vj), (v2f64 LSX128:$vk), CC)), 1350 (!cast<LAInst>(Inst#"_D") LSX128:$vj, LSX128:$vk)>; 1351} 1352 1353let Predicates = [HasExtLSX] in { 1354 1355// VADD_{B/H/W/D} 1356defm : PatVrVr<add, "VADD">; 1357// VSUB_{B/H/W/D} 1358defm : PatVrVr<sub, "VSUB">; 1359 1360// VADDI_{B/H/W/D}U 1361defm : PatVrUimm5<add, "VADDI">; 1362// VSUBI_{B/H/W/D}U 1363defm : PatVrUimm5<sub, "VSUBI">; 1364 1365// VNEG_{B/H/W/D} 1366def : Pat<(sub immAllZerosV, (v16i8 LSX128:$vj)), (VNEG_B LSX128:$vj)>; 1367def : Pat<(sub immAllZerosV, (v8i16 LSX128:$vj)), (VNEG_H LSX128:$vj)>; 1368def : Pat<(sub immAllZerosV, (v4i32 LSX128:$vj)), (VNEG_W LSX128:$vj)>; 1369def : Pat<(sub immAllZerosV, (v2i64 LSX128:$vj)), (VNEG_D LSX128:$vj)>; 1370 1371// VMAX[I]_{B/H/W/D}[U] 1372defm : PatVrVr<smax, "VMAX">; 1373defm : PatVrVrU<umax, "VMAX">; 1374defm : PatVrSimm5<smax, "VMAXI">; 1375defm : PatVrUimm5<umax, "VMAXI">; 1376 1377// VMIN[I]_{B/H/W/D}[U] 1378defm : PatVrVr<smin, "VMIN">; 1379defm : PatVrVrU<umin, "VMIN">; 1380defm : PatVrSimm5<smin, "VMINI">; 1381defm : PatVrUimm5<umin, "VMINI">; 1382 1383// VMUL_{B/H/W/D} 1384defm : PatVrVr<mul, "VMUL">; 1385 1386// VMUH_{B/H/W/D}[U] 1387defm : PatVrVr<mulhs, "VMUH">; 1388defm : PatVrVrU<mulhu, "VMUH">; 1389 1390// VMADD_{B/H/W/D} 1391defm : PatVrVrVr<muladd, "VMADD">; 1392// VMSUB_{B/H/W/D} 1393defm : PatVrVrVr<mulsub, "VMSUB">; 1394 1395// VDIV_{B/H/W/D}[U] 1396defm : PatVrVr<sdiv, "VDIV">; 1397defm : PatVrVrU<udiv, "VDIV">; 1398 1399// VMOD_{B/H/W/D}[U] 1400defm : PatVrVr<srem, "VMOD">; 1401defm : PatVrVrU<urem, "VMOD">; 1402 1403// VAND_V 1404foreach vt = [v16i8, v8i16, v4i32, v2i64] in 1405def : Pat<(and (vt LSX128:$vj), (vt LSX128:$vk)), 1406 (VAND_V LSX128:$vj, LSX128:$vk)>; 1407// VOR_V 1408foreach vt = [v16i8, v8i16, v4i32, v2i64] in 1409def : Pat<(or (vt LSX128:$vj), (vt LSX128:$vk)), 1410 (VOR_V LSX128:$vj, LSX128:$vk)>; 1411// VXOR_V 1412foreach vt = [v16i8, v8i16, v4i32, v2i64] in 1413def : Pat<(xor (vt LSX128:$vj), (vt LSX128:$vk)), 1414 (VXOR_V LSX128:$vj, LSX128:$vk)>; 1415// VNOR_V 1416foreach vt = [v16i8, v8i16, v4i32, v2i64] in 1417def : Pat<(vnot (or (vt LSX128:$vj), (vt LSX128:$vk))), 1418 (VNOR_V LSX128:$vj, LSX128:$vk)>; 1419 1420// VANDI_B 1421def : Pat<(and (v16i8 LSX128:$vj), (v16i8 (SplatPat_uimm8 uimm8:$imm))), 1422 (VANDI_B LSX128:$vj, uimm8:$imm)>; 1423// VORI_B 1424def : Pat<(or (v16i8 LSX128:$vj), (v16i8 (SplatPat_uimm8 uimm8:$imm))), 1425 (VORI_B LSX128:$vj, uimm8:$imm)>; 1426 1427// VXORI_B 1428def : Pat<(xor (v16i8 LSX128:$vj), (v16i8 (SplatPat_uimm8 uimm8:$imm))), 1429 (VXORI_B LSX128:$vj, uimm8:$imm)>; 1430 1431// VSLL[I]_{B/H/W/D} 1432defm : PatVrVr<shl, "VSLL">; 1433defm : PatShiftVrVr<shl, "VSLL">; 1434defm : PatShiftVrUimm<shl, "VSLLI">; 1435 1436// VSRL[I]_{B/H/W/D} 1437defm : PatVrVr<srl, "VSRL">; 1438defm : PatShiftVrVr<srl, "VSRL">; 1439defm : PatShiftVrUimm<srl, "VSRLI">; 1440 1441// VSRA[I]_{B/H/W/D} 1442defm : PatVrVr<sra, "VSRA">; 1443defm : PatShiftVrVr<sra, "VSRA">; 1444defm : PatShiftVrUimm<sra, "VSRAI">; 1445 1446// VCLZ_{B/H/W/D} 1447defm : PatVr<ctlz, "VCLZ">; 1448 1449// VPCNT_{B/H/W/D} 1450defm : PatVr<ctpop, "VPCNT">; 1451 1452// VBITCLR_{B/H/W/D} 1453def : Pat<(and v16i8:$vj, (vnot (shl vsplat_imm_eq_1, v16i8:$vk))), 1454 (v16i8 (VBITCLR_B v16i8:$vj, v16i8:$vk))>; 1455def : Pat<(and v8i16:$vj, (vnot (shl vsplat_imm_eq_1, v8i16:$vk))), 1456 (v8i16 (VBITCLR_H v8i16:$vj, v8i16:$vk))>; 1457def : Pat<(and v4i32:$vj, (vnot (shl vsplat_imm_eq_1, v4i32:$vk))), 1458 (v4i32 (VBITCLR_W v4i32:$vj, v4i32:$vk))>; 1459def : Pat<(and v2i64:$vj, (vnot (shl vsplat_imm_eq_1, v2i64:$vk))), 1460 (v2i64 (VBITCLR_D v2i64:$vj, v2i64:$vk))>; 1461def : Pat<(and v16i8:$vj, (vnot (shl vsplat_imm_eq_1, 1462 (vsplati8imm7 v16i8:$vk)))), 1463 (v16i8 (VBITCLR_B v16i8:$vj, v16i8:$vk))>; 1464def : Pat<(and v8i16:$vj, (vnot (shl vsplat_imm_eq_1, 1465 (vsplati16imm15 v8i16:$vk)))), 1466 (v8i16 (VBITCLR_H v8i16:$vj, v8i16:$vk))>; 1467def : Pat<(and v4i32:$vj, (vnot (shl vsplat_imm_eq_1, 1468 (vsplati32imm31 v4i32:$vk)))), 1469 (v4i32 (VBITCLR_W v4i32:$vj, v4i32:$vk))>; 1470def : Pat<(and v2i64:$vj, (vnot (shl vsplat_imm_eq_1, 1471 (vsplati64imm63 v2i64:$vk)))), 1472 (v2i64 (VBITCLR_D v2i64:$vj, v2i64:$vk))>; 1473 1474// VBITCLRI_{B/H/W/D} 1475def : Pat<(and (v16i8 LSX128:$vj), (v16i8 (vsplat_uimm_inv_pow2 uimm3:$imm))), 1476 (VBITCLRI_B LSX128:$vj, uimm3:$imm)>; 1477def : Pat<(and (v8i16 LSX128:$vj), (v8i16 (vsplat_uimm_inv_pow2 uimm4:$imm))), 1478 (VBITCLRI_H LSX128:$vj, uimm4:$imm)>; 1479def : Pat<(and (v4i32 LSX128:$vj), (v4i32 (vsplat_uimm_inv_pow2 uimm5:$imm))), 1480 (VBITCLRI_W LSX128:$vj, uimm5:$imm)>; 1481def : Pat<(and (v2i64 LSX128:$vj), (v2i64 (vsplat_uimm_inv_pow2 uimm6:$imm))), 1482 (VBITCLRI_D LSX128:$vj, uimm6:$imm)>; 1483 1484// VBITSET_{B/H/W/D} 1485def : Pat<(or v16i8:$vj, (shl vsplat_imm_eq_1, v16i8:$vk)), 1486 (v16i8 (VBITSET_B v16i8:$vj, v16i8:$vk))>; 1487def : Pat<(or v8i16:$vj, (shl vsplat_imm_eq_1, v8i16:$vk)), 1488 (v8i16 (VBITSET_H v8i16:$vj, v8i16:$vk))>; 1489def : Pat<(or v4i32:$vj, (shl vsplat_imm_eq_1, v4i32:$vk)), 1490 (v4i32 (VBITSET_W v4i32:$vj, v4i32:$vk))>; 1491def : Pat<(or v2i64:$vj, (shl vsplat_imm_eq_1, v2i64:$vk)), 1492 (v2i64 (VBITSET_D v2i64:$vj, v2i64:$vk))>; 1493def : Pat<(or v16i8:$vj, (shl vsplat_imm_eq_1, (vsplati8imm7 v16i8:$vk))), 1494 (v16i8 (VBITSET_B v16i8:$vj, v16i8:$vk))>; 1495def : Pat<(or v8i16:$vj, (shl vsplat_imm_eq_1, (vsplati16imm15 v8i16:$vk))), 1496 (v8i16 (VBITSET_H v8i16:$vj, v8i16:$vk))>; 1497def : Pat<(or v4i32:$vj, (shl vsplat_imm_eq_1, (vsplati32imm31 v4i32:$vk))), 1498 (v4i32 (VBITSET_W v4i32:$vj, v4i32:$vk))>; 1499def : Pat<(or v2i64:$vj, (shl vsplat_imm_eq_1, (vsplati64imm63 v2i64:$vk))), 1500 (v2i64 (VBITSET_D v2i64:$vj, v2i64:$vk))>; 1501 1502// VBITSETI_{B/H/W/D} 1503def : Pat<(or (v16i8 LSX128:$vj), (v16i8 (vsplat_uimm_pow2 uimm3:$imm))), 1504 (VBITSETI_B LSX128:$vj, uimm3:$imm)>; 1505def : Pat<(or (v8i16 LSX128:$vj), (v8i16 (vsplat_uimm_pow2 uimm4:$imm))), 1506 (VBITSETI_H LSX128:$vj, uimm4:$imm)>; 1507def : Pat<(or (v4i32 LSX128:$vj), (v4i32 (vsplat_uimm_pow2 uimm5:$imm))), 1508 (VBITSETI_W LSX128:$vj, uimm5:$imm)>; 1509def : Pat<(or (v2i64 LSX128:$vj), (v2i64 (vsplat_uimm_pow2 uimm6:$imm))), 1510 (VBITSETI_D LSX128:$vj, uimm6:$imm)>; 1511 1512// VBITREV_{B/H/W/D} 1513def : Pat<(xor v16i8:$vj, (shl vsplat_imm_eq_1, v16i8:$vk)), 1514 (v16i8 (VBITREV_B v16i8:$vj, v16i8:$vk))>; 1515def : Pat<(xor v8i16:$vj, (shl vsplat_imm_eq_1, v8i16:$vk)), 1516 (v8i16 (VBITREV_H v8i16:$vj, v8i16:$vk))>; 1517def : Pat<(xor v4i32:$vj, (shl vsplat_imm_eq_1, v4i32:$vk)), 1518 (v4i32 (VBITREV_W v4i32:$vj, v4i32:$vk))>; 1519def : Pat<(xor v2i64:$vj, (shl vsplat_imm_eq_1, v2i64:$vk)), 1520 (v2i64 (VBITREV_D v2i64:$vj, v2i64:$vk))>; 1521def : Pat<(xor v16i8:$vj, (shl vsplat_imm_eq_1, (vsplati8imm7 v16i8:$vk))), 1522 (v16i8 (VBITREV_B v16i8:$vj, v16i8:$vk))>; 1523def : Pat<(xor v8i16:$vj, (shl vsplat_imm_eq_1, (vsplati16imm15 v8i16:$vk))), 1524 (v8i16 (VBITREV_H v8i16:$vj, v8i16:$vk))>; 1525def : Pat<(xor v4i32:$vj, (shl vsplat_imm_eq_1, (vsplati32imm31 v4i32:$vk))), 1526 (v4i32 (VBITREV_W v4i32:$vj, v4i32:$vk))>; 1527def : Pat<(xor v2i64:$vj, (shl vsplat_imm_eq_1, (vsplati64imm63 v2i64:$vk))), 1528 (v2i64 (VBITREV_D v2i64:$vj, v2i64:$vk))>; 1529 1530// VBITREVI_{B/H/W/D} 1531def : Pat<(xor (v16i8 LSX128:$vj), (v16i8 (vsplat_uimm_pow2 uimm3:$imm))), 1532 (VBITREVI_B LSX128:$vj, uimm3:$imm)>; 1533def : Pat<(xor (v8i16 LSX128:$vj), (v8i16 (vsplat_uimm_pow2 uimm4:$imm))), 1534 (VBITREVI_H LSX128:$vj, uimm4:$imm)>; 1535def : Pat<(xor (v4i32 LSX128:$vj), (v4i32 (vsplat_uimm_pow2 uimm5:$imm))), 1536 (VBITREVI_W LSX128:$vj, uimm5:$imm)>; 1537def : Pat<(xor (v2i64 LSX128:$vj), (v2i64 (vsplat_uimm_pow2 uimm6:$imm))), 1538 (VBITREVI_D LSX128:$vj, uimm6:$imm)>; 1539 1540// VFADD_{S/D} 1541defm : PatVrVrF<fadd, "VFADD">; 1542 1543// VFSUB_{S/D} 1544defm : PatVrVrF<fsub, "VFSUB">; 1545 1546// VFMUL_{S/D} 1547defm : PatVrVrF<fmul, "VFMUL">; 1548 1549// VFDIV_{S/D} 1550defm : PatVrVrF<fdiv, "VFDIV">; 1551 1552// VFMADD_{S/D} 1553def : Pat<(fma v4f32:$vj, v4f32:$vk, v4f32:$va), 1554 (VFMADD_S v4f32:$vj, v4f32:$vk, v4f32:$va)>; 1555def : Pat<(fma v2f64:$vj, v2f64:$vk, v2f64:$va), 1556 (VFMADD_D v2f64:$vj, v2f64:$vk, v2f64:$va)>; 1557 1558// VFMSUB_{S/D} 1559def : Pat<(fma v4f32:$vj, v4f32:$vk, (fneg v4f32:$va)), 1560 (VFMSUB_S v4f32:$vj, v4f32:$vk, v4f32:$va)>; 1561def : Pat<(fma v2f64:$vj, v2f64:$vk, (fneg v2f64:$va)), 1562 (VFMSUB_D v2f64:$vj, v2f64:$vk, v2f64:$va)>; 1563 1564// VFNMADD_{S/D} 1565def : Pat<(fneg (fma v4f32:$vj, v4f32:$vk, v4f32:$va)), 1566 (VFNMADD_S v4f32:$vj, v4f32:$vk, v4f32:$va)>; 1567def : Pat<(fneg (fma v2f64:$vj, v2f64:$vk, v2f64:$va)), 1568 (VFNMADD_D v2f64:$vj, v2f64:$vk, v2f64:$va)>; 1569def : Pat<(fma_nsz (fneg v4f32:$vj), v4f32:$vk, (fneg v4f32:$va)), 1570 (VFNMADD_S v4f32:$vj, v4f32:$vk, v4f32:$va)>; 1571def : Pat<(fma_nsz (fneg v2f64:$vj), v2f64:$vk, (fneg v2f64:$va)), 1572 (VFNMADD_D v2f64:$vj, v2f64:$vk, v2f64:$va)>; 1573 1574// VFNMSUB_{S/D} 1575def : Pat<(fneg (fma v4f32:$vj, v4f32:$vk, (fneg v4f32:$va))), 1576 (VFNMSUB_S v4f32:$vj, v4f32:$vk, v4f32:$va)>; 1577def : Pat<(fneg (fma v2f64:$vj, v2f64:$vk, (fneg v2f64:$va))), 1578 (VFNMSUB_D v2f64:$vj, v2f64:$vk, v2f64:$va)>; 1579def : Pat<(fma_nsz (fneg v4f32:$vj), v4f32:$vk, v4f32:$va), 1580 (VFNMSUB_S v4f32:$vj, v4f32:$vk, v4f32:$va)>; 1581def : Pat<(fma_nsz (fneg v2f64:$vj), v2f64:$vk, v2f64:$va), 1582 (VFNMSUB_D v2f64:$vj, v2f64:$vk, v2f64:$va)>; 1583 1584// VFSQRT_{S/D} 1585defm : PatVrF<fsqrt, "VFSQRT">; 1586 1587// VFRECIP_{S/D} 1588def : Pat<(fdiv vsplatf32_fpimm_eq_1, v4f32:$vj), 1589 (VFRECIP_S v4f32:$vj)>; 1590def : Pat<(fdiv vsplatf64_fpimm_eq_1, v2f64:$vj), 1591 (VFRECIP_D v2f64:$vj)>; 1592 1593// VFRSQRT_{S/D} 1594def : Pat<(fdiv vsplatf32_fpimm_eq_1, (fsqrt v4f32:$vj)), 1595 (VFRSQRT_S v4f32:$vj)>; 1596def : Pat<(fdiv vsplatf64_fpimm_eq_1, (fsqrt v2f64:$vj)), 1597 (VFRSQRT_D v2f64:$vj)>; 1598 1599// VSEQ[I]_{B/H/W/D} 1600defm : PatCCVrSimm5<SETEQ, "VSEQI">; 1601defm : PatCCVrVr<SETEQ, "VSEQ">; 1602 1603// VSLE[I]_{B/H/W/D}[U] 1604defm : PatCCVrSimm5<SETLE, "VSLEI">; 1605defm : PatCCVrUimm5<SETULE, "VSLEI">; 1606defm : PatCCVrVr<SETLE, "VSLE">; 1607defm : PatCCVrVrU<SETULE, "VSLE">; 1608 1609// VSLT[I]_{B/H/W/D}[U] 1610defm : PatCCVrSimm5<SETLT, "VSLTI">; 1611defm : PatCCVrUimm5<SETULT, "VSLTI">; 1612defm : PatCCVrVr<SETLT, "VSLT">; 1613defm : PatCCVrVrU<SETULT, "VSLT">; 1614 1615// VFCMP.cond.{S/D} 1616defm : PatCCVrVrF<SETEQ, "VFCMP_CEQ">; 1617defm : PatCCVrVrF<SETOEQ, "VFCMP_CEQ">; 1618defm : PatCCVrVrF<SETUEQ, "VFCMP_CUEQ">; 1619 1620defm : PatCCVrVrF<SETLE, "VFCMP_CLE">; 1621defm : PatCCVrVrF<SETOLE, "VFCMP_CLE">; 1622defm : PatCCVrVrF<SETULE, "VFCMP_CULE">; 1623 1624defm : PatCCVrVrF<SETLT, "VFCMP_CLT">; 1625defm : PatCCVrVrF<SETOLT, "VFCMP_CLT">; 1626defm : PatCCVrVrF<SETULT, "VFCMP_CULT">; 1627 1628defm : PatCCVrVrF<SETNE, "VFCMP_CNE">; 1629defm : PatCCVrVrF<SETONE, "VFCMP_CNE">; 1630defm : PatCCVrVrF<SETUNE, "VFCMP_CUNE">; 1631 1632defm : PatCCVrVrF<SETO, "VFCMP_COR">; 1633defm : PatCCVrVrF<SETUO, "VFCMP_CUN">; 1634 1635// VINSGR2VR_{B/H/W/D} 1636def : Pat<(vector_insert v16i8:$vd, GRLenVT:$rj, uimm4:$imm), 1637 (VINSGR2VR_B v16i8:$vd, GRLenVT:$rj, uimm4:$imm)>; 1638def : Pat<(vector_insert v8i16:$vd, GRLenVT:$rj, uimm3:$imm), 1639 (VINSGR2VR_H v8i16:$vd, GRLenVT:$rj, uimm3:$imm)>; 1640def : Pat<(vector_insert v4i32:$vd, GRLenVT:$rj, uimm2:$imm), 1641 (VINSGR2VR_W v4i32:$vd, GRLenVT:$rj, uimm2:$imm)>; 1642def : Pat<(vector_insert v2i64:$vd, GRLenVT:$rj, uimm1:$imm), 1643 (VINSGR2VR_D v2i64:$vd, GRLenVT:$rj, uimm1:$imm)>; 1644 1645def : Pat<(vector_insert v4f32:$vd, FPR32:$fj, uimm2:$imm), 1646 (VINSGR2VR_W $vd, (COPY_TO_REGCLASS FPR32:$fj, GPR), uimm2:$imm)>; 1647def : Pat<(vector_insert v2f64:$vd, FPR64:$fj, uimm1:$imm), 1648 (VINSGR2VR_D $vd, (COPY_TO_REGCLASS FPR64:$fj, GPR), uimm1:$imm)>; 1649 1650// VPICKVE2GR_{B/H/W}[U] 1651def : Pat<(loongarch_vpick_sext_elt v16i8:$vd, uimm4:$imm, i8), 1652 (VPICKVE2GR_B v16i8:$vd, uimm4:$imm)>; 1653def : Pat<(loongarch_vpick_sext_elt v8i16:$vd, uimm3:$imm, i16), 1654 (VPICKVE2GR_H v8i16:$vd, uimm3:$imm)>; 1655def : Pat<(loongarch_vpick_sext_elt v4i32:$vd, uimm2:$imm, i32), 1656 (VPICKVE2GR_W v4i32:$vd, uimm2:$imm)>; 1657 1658def : Pat<(loongarch_vpick_zext_elt v16i8:$vd, uimm4:$imm, i8), 1659 (VPICKVE2GR_BU v16i8:$vd, uimm4:$imm)>; 1660def : Pat<(loongarch_vpick_zext_elt v8i16:$vd, uimm3:$imm, i16), 1661 (VPICKVE2GR_HU v8i16:$vd, uimm3:$imm)>; 1662def : Pat<(loongarch_vpick_zext_elt v4i32:$vd, uimm2:$imm, i32), 1663 (VPICKVE2GR_WU v4i32:$vd, uimm2:$imm)>; 1664 1665// VREPLGR2VR_{B/H/W/D} 1666def : Pat<(lsxsplati8 GPR:$rj), (VREPLGR2VR_B GPR:$rj)>; 1667def : Pat<(lsxsplati16 GPR:$rj), (VREPLGR2VR_H GPR:$rj)>; 1668def : Pat<(lsxsplati32 GPR:$rj), (VREPLGR2VR_W GPR:$rj)>; 1669def : Pat<(lsxsplati64 GPR:$rj), (VREPLGR2VR_D GPR:$rj)>; 1670 1671// VREPLVE_{B/H/W/D} 1672def : Pat<(loongarch_vreplve v16i8:$vj, GRLenVT:$rk), 1673 (VREPLVE_B v16i8:$vj, GRLenVT:$rk)>; 1674def : Pat<(loongarch_vreplve v8i16:$vj, GRLenVT:$rk), 1675 (VREPLVE_H v8i16:$vj, GRLenVT:$rk)>; 1676def : Pat<(loongarch_vreplve v4i32:$vj, GRLenVT:$rk), 1677 (VREPLVE_W v4i32:$vj, GRLenVT:$rk)>; 1678def : Pat<(loongarch_vreplve v2i64:$vj, GRLenVT:$rk), 1679 (VREPLVE_D v2i64:$vj, GRLenVT:$rk)>; 1680 1681// VREPLVEI_{W/D} 1682def : Pat<(lsxsplatf32 FPR32:$fj), 1683 (VREPLVEI_W (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32), 0)>; 1684def : Pat<(lsxsplatf64 FPR64:$fj), 1685 (VREPLVEI_D (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), 0)>; 1686 1687// Loads/Stores 1688foreach vt = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in { 1689 defm : LdPat<load, VLD, vt>; 1690 def : RegRegLdPat<load, VLDX, vt>; 1691 defm : StPat<store, VST, LSX128, vt>; 1692 def : RegRegStPat<store, VSTX, LSX128, vt>; 1693} 1694 1695// Vector extraction with constant index. 1696def : Pat<(i64 (vector_extract v16i8:$vj, uimm4:$imm)), 1697 (VPICKVE2GR_B v16i8:$vj, uimm4:$imm)>; 1698def : Pat<(i64 (vector_extract v8i16:$vj, uimm3:$imm)), 1699 (VPICKVE2GR_H v8i16:$vj, uimm3:$imm)>; 1700def : Pat<(i64 (vector_extract v4i32:$vj, uimm2:$imm)), 1701 (VPICKVE2GR_W v4i32:$vj, uimm2:$imm)>; 1702def : Pat<(i64 (vector_extract v2i64:$vj, uimm1:$imm)), 1703 (VPICKVE2GR_D v2i64:$vj, uimm1:$imm)>; 1704def : Pat<(f32 (vector_extract v4f32:$vj, uimm2:$imm)), 1705 (f32 (EXTRACT_SUBREG (VREPLVEI_W v4f32:$vj, uimm2:$imm), sub_32))>; 1706def : Pat<(f64 (vector_extract v2f64:$vj, uimm1:$imm)), 1707 (f64 (EXTRACT_SUBREG (VREPLVEI_D v2f64:$vj, uimm1:$imm), sub_64))>; 1708 1709// Vector extraction with variable index. 1710def : Pat<(i64 (vector_extract v16i8:$vj, i64:$rk)), 1711 (SRAI_W (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG (VREPLVE_B v16i8:$vj, 1712 i64:$rk), 1713 sub_32)), 1714 GPR), (i64 24))>; 1715def : Pat<(i64 (vector_extract v8i16:$vj, i64:$rk)), 1716 (SRAI_W (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG (VREPLVE_H v8i16:$vj, 1717 i64:$rk), 1718 sub_32)), 1719 GPR), (i64 16))>; 1720def : Pat<(i64 (vector_extract v4i32:$vj, i64:$rk)), 1721 (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG (VREPLVE_W v4i32:$vj, i64:$rk), 1722 sub_32)), 1723 GPR)>; 1724def : Pat<(i64 (vector_extract v2i64:$vj, i64:$rk)), 1725 (COPY_TO_REGCLASS (f64 (EXTRACT_SUBREG (VREPLVE_D v2i64:$vj, i64:$rk), 1726 sub_64)), 1727 GPR)>; 1728def : Pat<(f32 (vector_extract v4f32:$vj, i64:$rk)), 1729 (f32 (EXTRACT_SUBREG (VREPLVE_W v4f32:$vj, i64:$rk), sub_32))>; 1730def : Pat<(f64 (vector_extract v2f64:$vj, i64:$rk)), 1731 (f64 (EXTRACT_SUBREG (VREPLVE_D v2f64:$vj, i64:$rk), sub_64))>; 1732 1733// vselect 1734def : Pat<(v16i8 (vselect LSX128:$vj, LSX128:$vd, 1735 (v16i8 (SplatPat_uimm8 uimm8:$imm)))), 1736 (VBITSELI_B LSX128:$vd, LSX128:$vj, uimm8:$imm)>; 1737foreach vt = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in 1738 def : Pat<(vt (vselect LSX128:$va, LSX128:$vk, LSX128:$vj)), 1739 (VBITSEL_V LSX128:$vj, LSX128:$vk, LSX128:$va)>; 1740 1741// fneg 1742def : Pat<(fneg (v4f32 LSX128:$vj)), (VBITREVI_W LSX128:$vj, 31)>; 1743def : Pat<(fneg (v2f64 LSX128:$vj)), (VBITREVI_D LSX128:$vj, 63)>; 1744 1745} // Predicates = [HasExtLSX] 1746 1747/// Intrinsic pattern 1748 1749class deriveLSXIntrinsic<string Inst> { 1750 Intrinsic ret = !cast<Intrinsic>(!tolower("int_loongarch_lsx_"#Inst)); 1751} 1752 1753let Predicates = [HasExtLSX] in { 1754 1755// vty: v16i8/v8i16/v4i32/v2i64 1756// Pat<(Intrinsic vty:$vj, vty:$vk), 1757// (LAInst vty:$vj, vty:$vk)>; 1758foreach Inst = ["VSADD_B", "VSADD_BU", "VSSUB_B", "VSSUB_BU", 1759 "VHADDW_H_B", "VHADDW_HU_BU", "VHSUBW_H_B", "VHSUBW_HU_BU", 1760 "VADDWEV_H_B", "VADDWOD_H_B", "VSUBWEV_H_B", "VSUBWOD_H_B", 1761 "VADDWEV_H_BU", "VADDWOD_H_BU", "VSUBWEV_H_BU", "VSUBWOD_H_BU", 1762 "VADDWEV_H_BU_B", "VADDWOD_H_BU_B", 1763 "VAVG_B", "VAVG_BU", "VAVGR_B", "VAVGR_BU", 1764 "VABSD_B", "VABSD_BU", "VADDA_B", "VMUH_B", "VMUH_BU", 1765 "VMULWEV_H_B", "VMULWOD_H_B", "VMULWEV_H_BU", "VMULWOD_H_BU", 1766 "VMULWEV_H_BU_B", "VMULWOD_H_BU_B", "VSIGNCOV_B", 1767 "VANDN_V", "VORN_V", "VROTR_B", "VSRLR_B", "VSRAR_B", 1768 "VSEQ_B", "VSLE_B", "VSLE_BU", "VSLT_B", "VSLT_BU", 1769 "VPACKEV_B", "VPACKOD_B", "VPICKEV_B", "VPICKOD_B", 1770 "VILVL_B", "VILVH_B"] in 1771 def : Pat<(deriveLSXIntrinsic<Inst>.ret 1772 (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)), 1773 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk)>; 1774foreach Inst = ["VSADD_H", "VSADD_HU", "VSSUB_H", "VSSUB_HU", 1775 "VHADDW_W_H", "VHADDW_WU_HU", "VHSUBW_W_H", "VHSUBW_WU_HU", 1776 "VADDWEV_W_H", "VADDWOD_W_H", "VSUBWEV_W_H", "VSUBWOD_W_H", 1777 "VADDWEV_W_HU", "VADDWOD_W_HU", "VSUBWEV_W_HU", "VSUBWOD_W_HU", 1778 "VADDWEV_W_HU_H", "VADDWOD_W_HU_H", 1779 "VAVG_H", "VAVG_HU", "VAVGR_H", "VAVGR_HU", 1780 "VABSD_H", "VABSD_HU", "VADDA_H", "VMUH_H", "VMUH_HU", 1781 "VMULWEV_W_H", "VMULWOD_W_H", "VMULWEV_W_HU", "VMULWOD_W_HU", 1782 "VMULWEV_W_HU_H", "VMULWOD_W_HU_H", "VSIGNCOV_H", "VROTR_H", 1783 "VSRLR_H", "VSRAR_H", "VSRLN_B_H", "VSRAN_B_H", "VSRLRN_B_H", 1784 "VSRARN_B_H", "VSSRLN_B_H", "VSSRAN_B_H", "VSSRLN_BU_H", 1785 "VSSRAN_BU_H", "VSSRLRN_B_H", "VSSRARN_B_H", "VSSRLRN_BU_H", 1786 "VSSRARN_BU_H", 1787 "VSEQ_H", "VSLE_H", "VSLE_HU", "VSLT_H", "VSLT_HU", 1788 "VPACKEV_H", "VPACKOD_H", "VPICKEV_H", "VPICKOD_H", 1789 "VILVL_H", "VILVH_H"] in 1790 def : Pat<(deriveLSXIntrinsic<Inst>.ret 1791 (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)), 1792 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk)>; 1793foreach Inst = ["VSADD_W", "VSADD_WU", "VSSUB_W", "VSSUB_WU", 1794 "VHADDW_D_W", "VHADDW_DU_WU", "VHSUBW_D_W", "VHSUBW_DU_WU", 1795 "VADDWEV_D_W", "VADDWOD_D_W", "VSUBWEV_D_W", "VSUBWOD_D_W", 1796 "VADDWEV_D_WU", "VADDWOD_D_WU", "VSUBWEV_D_WU", "VSUBWOD_D_WU", 1797 "VADDWEV_D_WU_W", "VADDWOD_D_WU_W", 1798 "VAVG_W", "VAVG_WU", "VAVGR_W", "VAVGR_WU", 1799 "VABSD_W", "VABSD_WU", "VADDA_W", "VMUH_W", "VMUH_WU", 1800 "VMULWEV_D_W", "VMULWOD_D_W", "VMULWEV_D_WU", "VMULWOD_D_WU", 1801 "VMULWEV_D_WU_W", "VMULWOD_D_WU_W", "VSIGNCOV_W", "VROTR_W", 1802 "VSRLR_W", "VSRAR_W", "VSRLN_H_W", "VSRAN_H_W", "VSRLRN_H_W", 1803 "VSRARN_H_W", "VSSRLN_H_W", "VSSRAN_H_W", "VSSRLN_HU_W", 1804 "VSSRAN_HU_W", "VSSRLRN_H_W", "VSSRARN_H_W", "VSSRLRN_HU_W", 1805 "VSSRARN_HU_W", 1806 "VSEQ_W", "VSLE_W", "VSLE_WU", "VSLT_W", "VSLT_WU", 1807 "VPACKEV_W", "VPACKOD_W", "VPICKEV_W", "VPICKOD_W", 1808 "VILVL_W", "VILVH_W"] in 1809 def : Pat<(deriveLSXIntrinsic<Inst>.ret 1810 (v4i32 LSX128:$vj), (v4i32 LSX128:$vk)), 1811 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk)>; 1812foreach Inst = ["VADD_Q", "VSUB_Q", 1813 "VSADD_D", "VSADD_DU", "VSSUB_D", "VSSUB_DU", 1814 "VHADDW_Q_D", "VHADDW_QU_DU", "VHSUBW_Q_D", "VHSUBW_QU_DU", 1815 "VADDWEV_Q_D", "VADDWOD_Q_D", "VSUBWEV_Q_D", "VSUBWOD_Q_D", 1816 "VADDWEV_Q_DU", "VADDWOD_Q_DU", "VSUBWEV_Q_DU", "VSUBWOD_Q_DU", 1817 "VADDWEV_Q_DU_D", "VADDWOD_Q_DU_D", 1818 "VAVG_D", "VAVG_DU", "VAVGR_D", "VAVGR_DU", 1819 "VABSD_D", "VABSD_DU", "VADDA_D", "VMUH_D", "VMUH_DU", 1820 "VMULWEV_Q_D", "VMULWOD_Q_D", "VMULWEV_Q_DU", "VMULWOD_Q_DU", 1821 "VMULWEV_Q_DU_D", "VMULWOD_Q_DU_D", "VSIGNCOV_D", "VROTR_D", 1822 "VSRLR_D", "VSRAR_D", "VSRLN_W_D", "VSRAN_W_D", "VSRLRN_W_D", 1823 "VSRARN_W_D", "VSSRLN_W_D", "VSSRAN_W_D", "VSSRLN_WU_D", 1824 "VSSRAN_WU_D", "VSSRLRN_W_D", "VSSRARN_W_D", "VSSRLRN_WU_D", 1825 "VSSRARN_WU_D", "VFFINT_S_L", 1826 "VSEQ_D", "VSLE_D", "VSLE_DU", "VSLT_D", "VSLT_DU", 1827 "VPACKEV_D", "VPACKOD_D", "VPICKEV_D", "VPICKOD_D", 1828 "VILVL_D", "VILVH_D"] in 1829 def : Pat<(deriveLSXIntrinsic<Inst>.ret 1830 (v2i64 LSX128:$vj), (v2i64 LSX128:$vk)), 1831 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk)>; 1832 1833// vty: v16i8/v8i16/v4i32/v2i64 1834// Pat<(Intrinsic vty:$vd, vty:$vj, vty:$vk), 1835// (LAInst vty:$vd, vty:$vj, vty:$vk)>; 1836foreach Inst = ["VMADDWEV_H_B", "VMADDWOD_H_B", "VMADDWEV_H_BU", 1837 "VMADDWOD_H_BU", "VMADDWEV_H_BU_B", "VMADDWOD_H_BU_B"] in 1838 def : Pat<(deriveLSXIntrinsic<Inst>.ret 1839 (v8i16 LSX128:$vd), (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)), 1840 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 1841foreach Inst = ["VMADDWEV_W_H", "VMADDWOD_W_H", "VMADDWEV_W_HU", 1842 "VMADDWOD_W_HU", "VMADDWEV_W_HU_H", "VMADDWOD_W_HU_H"] in 1843 def : Pat<(deriveLSXIntrinsic<Inst>.ret 1844 (v4i32 LSX128:$vd), (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)), 1845 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 1846foreach Inst = ["VMADDWEV_D_W", "VMADDWOD_D_W", "VMADDWEV_D_WU", 1847 "VMADDWOD_D_WU", "VMADDWEV_D_WU_W", "VMADDWOD_D_WU_W"] in 1848 def : Pat<(deriveLSXIntrinsic<Inst>.ret 1849 (v2i64 LSX128:$vd), (v4i32 LSX128:$vj), (v4i32 LSX128:$vk)), 1850 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 1851foreach Inst = ["VMADDWEV_Q_D", "VMADDWOD_Q_D", "VMADDWEV_Q_DU", 1852 "VMADDWOD_Q_DU", "VMADDWEV_Q_DU_D", "VMADDWOD_Q_DU_D"] in 1853 def : Pat<(deriveLSXIntrinsic<Inst>.ret 1854 (v2i64 LSX128:$vd), (v2i64 LSX128:$vj), (v2i64 LSX128:$vk)), 1855 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 1856 1857// vty: v16i8/v8i16/v4i32/v2i64 1858// Pat<(Intrinsic vty:$vj), 1859// (LAInst vty:$vj)>; 1860foreach Inst = ["VEXTH_H_B", "VEXTH_HU_BU", 1861 "VMSKLTZ_B", "VMSKGEZ_B", "VMSKNZ_B", 1862 "VCLO_B"] in 1863 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v16i8 LSX128:$vj)), 1864 (!cast<LAInst>(Inst) LSX128:$vj)>; 1865foreach Inst = ["VEXTH_W_H", "VEXTH_WU_HU", "VMSKLTZ_H", 1866 "VCLO_H", "VFCVTL_S_H", "VFCVTH_S_H"] in 1867 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v8i16 LSX128:$vj)), 1868 (!cast<LAInst>(Inst) LSX128:$vj)>; 1869foreach Inst = ["VEXTH_D_W", "VEXTH_DU_WU", "VMSKLTZ_W", 1870 "VCLO_W", "VFFINT_S_W", "VFFINT_S_WU", 1871 "VFFINTL_D_W", "VFFINTH_D_W"] in 1872 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v4i32 LSX128:$vj)), 1873 (!cast<LAInst>(Inst) LSX128:$vj)>; 1874foreach Inst = ["VEXTH_Q_D", "VEXTH_QU_DU", "VMSKLTZ_D", 1875 "VEXTL_Q_D", "VEXTL_QU_DU", 1876 "VCLO_D", "VFFINT_D_L", "VFFINT_D_LU"] in 1877 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v2i64 LSX128:$vj)), 1878 (!cast<LAInst>(Inst) LSX128:$vj)>; 1879 1880// Pat<(Intrinsic timm:$imm) 1881// (LAInst timm:$imm)>; 1882def : Pat<(int_loongarch_lsx_vldi timm:$imm), 1883 (VLDI (to_valid_timm timm:$imm))>; 1884foreach Inst = ["VREPLI_B", "VREPLI_H", "VREPLI_W", "VREPLI_D"] in 1885 def : Pat<(deriveLSXIntrinsic<Inst>.ret timm:$imm), 1886 (!cast<LAInst>("Pseudo"#Inst) (to_valid_timm timm:$imm))>; 1887 1888// vty: v16i8/v8i16/v4i32/v2i64 1889// Pat<(Intrinsic vty:$vj, timm:$imm) 1890// (LAInst vty:$vj, timm:$imm)>; 1891foreach Inst = ["VSAT_B", "VSAT_BU", "VNORI_B", "VROTRI_B", "VSLLWIL_H_B", 1892 "VSLLWIL_HU_BU", "VSRLRI_B", "VSRARI_B", 1893 "VSEQI_B", "VSLEI_B", "VSLEI_BU", "VSLTI_B", "VSLTI_BU", 1894 "VREPLVEI_B", "VBSLL_V", "VBSRL_V", "VSHUF4I_B"] in 1895 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v16i8 LSX128:$vj), timm:$imm), 1896 (!cast<LAInst>(Inst) LSX128:$vj, (to_valid_timm timm:$imm))>; 1897foreach Inst = ["VSAT_H", "VSAT_HU", "VROTRI_H", "VSLLWIL_W_H", 1898 "VSLLWIL_WU_HU", "VSRLRI_H", "VSRARI_H", 1899 "VSEQI_H", "VSLEI_H", "VSLEI_HU", "VSLTI_H", "VSLTI_HU", 1900 "VREPLVEI_H", "VSHUF4I_H"] in 1901 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v8i16 LSX128:$vj), timm:$imm), 1902 (!cast<LAInst>(Inst) LSX128:$vj, (to_valid_timm timm:$imm))>; 1903foreach Inst = ["VSAT_W", "VSAT_WU", "VROTRI_W", "VSLLWIL_D_W", 1904 "VSLLWIL_DU_WU", "VSRLRI_W", "VSRARI_W", 1905 "VSEQI_W", "VSLEI_W", "VSLEI_WU", "VSLTI_W", "VSLTI_WU", 1906 "VREPLVEI_W", "VSHUF4I_W"] in 1907 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v4i32 LSX128:$vj), timm:$imm), 1908 (!cast<LAInst>(Inst) LSX128:$vj, (to_valid_timm timm:$imm))>; 1909foreach Inst = ["VSAT_D", "VSAT_DU", "VROTRI_D", "VSRLRI_D", "VSRARI_D", 1910 "VSEQI_D", "VSLEI_D", "VSLEI_DU", "VSLTI_D", "VSLTI_DU", 1911 "VPICKVE2GR_D", "VPICKVE2GR_DU", 1912 "VREPLVEI_D"] in 1913 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v2i64 LSX128:$vj), timm:$imm), 1914 (!cast<LAInst>(Inst) LSX128:$vj, (to_valid_timm timm:$imm))>; 1915 1916// vty: v16i8/v8i16/v4i32/v2i64 1917// Pat<(Intrinsic vty:$vd, vty:$vj, timm:$imm) 1918// (LAInst vty:$vd, vty:$vj, timm:$imm)>; 1919foreach Inst = ["VSRLNI_B_H", "VSRANI_B_H", "VSRLRNI_B_H", "VSRARNI_B_H", 1920 "VSSRLNI_B_H", "VSSRANI_B_H", "VSSRLNI_BU_H", "VSSRANI_BU_H", 1921 "VSSRLRNI_B_H", "VSSRARNI_B_H", "VSSRLRNI_BU_H", "VSSRARNI_BU_H", 1922 "VFRSTPI_B", "VBITSELI_B", "VEXTRINS_B"] in 1923 def : Pat<(deriveLSXIntrinsic<Inst>.ret 1924 (v16i8 LSX128:$vd), (v16i8 LSX128:$vj), timm:$imm), 1925 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, 1926 (to_valid_timm timm:$imm))>; 1927foreach Inst = ["VSRLNI_H_W", "VSRANI_H_W", "VSRLRNI_H_W", "VSRARNI_H_W", 1928 "VSSRLNI_H_W", "VSSRANI_H_W", "VSSRLNI_HU_W", "VSSRANI_HU_W", 1929 "VSSRLRNI_H_W", "VSSRARNI_H_W", "VSSRLRNI_HU_W", "VSSRARNI_HU_W", 1930 "VFRSTPI_H", "VEXTRINS_H"] in 1931 def : Pat<(deriveLSXIntrinsic<Inst>.ret 1932 (v8i16 LSX128:$vd), (v8i16 LSX128:$vj), timm:$imm), 1933 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, 1934 (to_valid_timm timm:$imm))>; 1935foreach Inst = ["VSRLNI_W_D", "VSRANI_W_D", "VSRLRNI_W_D", "VSRARNI_W_D", 1936 "VSSRLNI_W_D", "VSSRANI_W_D", "VSSRLNI_WU_D", "VSSRANI_WU_D", 1937 "VSSRLRNI_W_D", "VSSRARNI_W_D", "VSSRLRNI_WU_D", "VSSRARNI_WU_D", 1938 "VPERMI_W", "VEXTRINS_W"] in 1939 def : Pat<(deriveLSXIntrinsic<Inst>.ret 1940 (v4i32 LSX128:$vd), (v4i32 LSX128:$vj), timm:$imm), 1941 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, 1942 (to_valid_timm timm:$imm))>; 1943foreach Inst = ["VSRLNI_D_Q", "VSRANI_D_Q", "VSRLRNI_D_Q", "VSRARNI_D_Q", 1944 "VSSRLNI_D_Q", "VSSRANI_D_Q", "VSSRLNI_DU_Q", "VSSRANI_DU_Q", 1945 "VSSRLRNI_D_Q", "VSSRARNI_D_Q", "VSSRLRNI_DU_Q", "VSSRARNI_DU_Q", 1946 "VSHUF4I_D", "VEXTRINS_D"] in 1947 def : Pat<(deriveLSXIntrinsic<Inst>.ret 1948 (v2i64 LSX128:$vd), (v2i64 LSX128:$vj), timm:$imm), 1949 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, 1950 (to_valid_timm timm:$imm))>; 1951 1952// vty: v16i8/v8i16/v4i32/v2i64 1953// Pat<(Intrinsic vty:$vd, vty:$vj, vty:$vk), 1954// (LAInst vty:$vd, vty:$vj, vty:$vk)>; 1955foreach Inst = ["VFRSTP_B", "VBITSEL_V", "VSHUF_B"] in 1956 def : Pat<(deriveLSXIntrinsic<Inst>.ret 1957 (v16i8 LSX128:$vd), (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)), 1958 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 1959foreach Inst = ["VFRSTP_H", "VSHUF_H"] in 1960 def : Pat<(deriveLSXIntrinsic<Inst>.ret 1961 (v8i16 LSX128:$vd), (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)), 1962 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 1963def : Pat<(int_loongarch_lsx_vshuf_w (v4i32 LSX128:$vd), (v4i32 LSX128:$vj), 1964 (v4i32 LSX128:$vk)), 1965 (VSHUF_W LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 1966def : Pat<(int_loongarch_lsx_vshuf_d (v2i64 LSX128:$vd), (v2i64 LSX128:$vj), 1967 (v2i64 LSX128:$vk)), 1968 (VSHUF_D LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 1969 1970// vty: v4f32/v2f64 1971// Pat<(Intrinsic vty:$vj, vty:$vk, vty:$va), 1972// (LAInst vty:$vj, vty:$vk, vty:$va)>; 1973foreach Inst = ["VFMSUB_S", "VFNMADD_S", "VFNMSUB_S"] in 1974 def : Pat<(deriveLSXIntrinsic<Inst>.ret 1975 (v4f32 LSX128:$vj), (v4f32 LSX128:$vk), (v4f32 LSX128:$va)), 1976 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk, LSX128:$va)>; 1977foreach Inst = ["VFMSUB_D", "VFNMADD_D", "VFNMSUB_D"] in 1978 def : Pat<(deriveLSXIntrinsic<Inst>.ret 1979 (v2f64 LSX128:$vj), (v2f64 LSX128:$vk), (v2f64 LSX128:$va)), 1980 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk, LSX128:$va)>; 1981 1982// vty: v4f32/v2f64 1983// Pat<(Intrinsic vty:$vj, vty:$vk), 1984// (LAInst vty:$vj, vty:$vk)>; 1985foreach Inst = ["VFMAX_S", "VFMIN_S", "VFMAXA_S", "VFMINA_S", "VFCVT_H_S", 1986 "VFCMP_CAF_S", "VFCMP_CUN_S", "VFCMP_CEQ_S", "VFCMP_CUEQ_S", 1987 "VFCMP_CLT_S", "VFCMP_CULT_S", "VFCMP_CLE_S", "VFCMP_CULE_S", 1988 "VFCMP_CNE_S", "VFCMP_COR_S", "VFCMP_CUNE_S", 1989 "VFCMP_SAF_S", "VFCMP_SUN_S", "VFCMP_SEQ_S", "VFCMP_SUEQ_S", 1990 "VFCMP_SLT_S", "VFCMP_SULT_S", "VFCMP_SLE_S", "VFCMP_SULE_S", 1991 "VFCMP_SNE_S", "VFCMP_SOR_S", "VFCMP_SUNE_S"] in 1992 def : Pat<(deriveLSXIntrinsic<Inst>.ret 1993 (v4f32 LSX128:$vj), (v4f32 LSX128:$vk)), 1994 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk)>; 1995foreach Inst = ["VFMAX_D", "VFMIN_D", "VFMAXA_D", "VFMINA_D", "VFCVT_S_D", 1996 "VFTINTRNE_W_D", "VFTINTRZ_W_D", "VFTINTRP_W_D", "VFTINTRM_W_D", 1997 "VFTINT_W_D", 1998 "VFCMP_CAF_D", "VFCMP_CUN_D", "VFCMP_CEQ_D", "VFCMP_CUEQ_D", 1999 "VFCMP_CLT_D", "VFCMP_CULT_D", "VFCMP_CLE_D", "VFCMP_CULE_D", 2000 "VFCMP_CNE_D", "VFCMP_COR_D", "VFCMP_CUNE_D", 2001 "VFCMP_SAF_D", "VFCMP_SUN_D", "VFCMP_SEQ_D", "VFCMP_SUEQ_D", 2002 "VFCMP_SLT_D", "VFCMP_SULT_D", "VFCMP_SLE_D", "VFCMP_SULE_D", 2003 "VFCMP_SNE_D", "VFCMP_SOR_D", "VFCMP_SUNE_D"] in 2004 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2005 (v2f64 LSX128:$vj), (v2f64 LSX128:$vk)), 2006 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk)>; 2007 2008// vty: v4f32/v2f64 2009// Pat<(Intrinsic vty:$vj), 2010// (LAInst vty:$vj)>; 2011foreach Inst = ["VFLOGB_S", "VFCLASS_S", "VFSQRT_S", "VFRECIP_S", "VFRSQRT_S", 2012 "VFRINT_S", "VFCVTL_D_S", "VFCVTH_D_S", 2013 "VFRINTRNE_S", "VFRINTRZ_S", "VFRINTRP_S", "VFRINTRM_S", 2014 "VFTINTRNE_W_S", "VFTINTRZ_W_S", "VFTINTRP_W_S", "VFTINTRM_W_S", 2015 "VFTINT_W_S", "VFTINTRZ_WU_S", "VFTINT_WU_S", 2016 "VFTINTRNEL_L_S", "VFTINTRNEH_L_S", "VFTINTRZL_L_S", 2017 "VFTINTRZH_L_S", "VFTINTRPL_L_S", "VFTINTRPH_L_S", 2018 "VFTINTRML_L_S", "VFTINTRMH_L_S", "VFTINTL_L_S", 2019 "VFTINTH_L_S"] in 2020 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v4f32 LSX128:$vj)), 2021 (!cast<LAInst>(Inst) LSX128:$vj)>; 2022foreach Inst = ["VFLOGB_D", "VFCLASS_D", "VFSQRT_D", "VFRECIP_D", "VFRSQRT_D", 2023 "VFRINT_D", 2024 "VFRINTRNE_D", "VFRINTRZ_D", "VFRINTRP_D", "VFRINTRM_D", 2025 "VFTINTRNE_L_D", "VFTINTRZ_L_D", "VFTINTRP_L_D", "VFTINTRM_L_D", 2026 "VFTINT_L_D", "VFTINTRZ_LU_D", "VFTINT_LU_D"] in 2027 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v2f64 LSX128:$vj)), 2028 (!cast<LAInst>(Inst) LSX128:$vj)>; 2029 2030// load 2031def : Pat<(int_loongarch_lsx_vld GPR:$rj, timm:$imm), 2032 (VLD GPR:$rj, (to_valid_timm timm:$imm))>; 2033def : Pat<(int_loongarch_lsx_vldx GPR:$rj, GPR:$rk), 2034 (VLDX GPR:$rj, GPR:$rk)>; 2035 2036def : Pat<(int_loongarch_lsx_vldrepl_b GPR:$rj, timm:$imm), 2037 (VLDREPL_B GPR:$rj, (to_valid_timm timm:$imm))>; 2038def : Pat<(int_loongarch_lsx_vldrepl_h GPR:$rj, timm:$imm), 2039 (VLDREPL_H GPR:$rj, (to_valid_timm timm:$imm))>; 2040def : Pat<(int_loongarch_lsx_vldrepl_w GPR:$rj, timm:$imm), 2041 (VLDREPL_W GPR:$rj, (to_valid_timm timm:$imm))>; 2042def : Pat<(int_loongarch_lsx_vldrepl_d GPR:$rj, timm:$imm), 2043 (VLDREPL_D GPR:$rj, (to_valid_timm timm:$imm))>; 2044 2045// store 2046def : Pat<(int_loongarch_lsx_vst LSX128:$vd, GPR:$rj, timm:$imm), 2047 (VST LSX128:$vd, GPR:$rj, (to_valid_timm timm:$imm))>; 2048def : Pat<(int_loongarch_lsx_vstx LSX128:$vd, GPR:$rj, GPR:$rk), 2049 (VSTX LSX128:$vd, GPR:$rj, GPR:$rk)>; 2050 2051def : Pat<(int_loongarch_lsx_vstelm_b v16i8:$vd, GPR:$rj, timm:$imm, timm:$idx), 2052 (VSTELM_B v16i8:$vd, GPR:$rj, (to_valid_timm timm:$imm), 2053 (to_valid_timm timm:$idx))>; 2054def : Pat<(int_loongarch_lsx_vstelm_h v8i16:$vd, GPR:$rj, timm:$imm, timm:$idx), 2055 (VSTELM_H v8i16:$vd, GPR:$rj, (to_valid_timm timm:$imm), 2056 (to_valid_timm timm:$idx))>; 2057def : Pat<(int_loongarch_lsx_vstelm_w v4i32:$vd, GPR:$rj, timm:$imm, timm:$idx), 2058 (VSTELM_W v4i32:$vd, GPR:$rj, (to_valid_timm timm:$imm), 2059 (to_valid_timm timm:$idx))>; 2060def : Pat<(int_loongarch_lsx_vstelm_d v2i64:$vd, GPR:$rj, timm:$imm, timm:$idx), 2061 (VSTELM_D v2i64:$vd, GPR:$rj, (to_valid_timm timm:$imm), 2062 (to_valid_timm timm:$idx))>; 2063 2064} // Predicates = [HasExtLSX] 2065