1//===-- LoongArchRegisterInfo.td - LoongArch Register defs -*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10//  Declarations that describe the LoongArch register files
11//===----------------------------------------------------------------------===//
12
13let Namespace = "LoongArch" in {
14class LoongArchReg<bits<16> Enc, string n, list<string> alt = []>
15    : Register<n> {
16  let HWEncoding = Enc;
17  let AltNames = alt;
18}
19
20class LoongArchReg32<bits<16> Enc, string n, list<string> alt = []>
21    : Register<n> {
22  let HWEncoding = Enc;
23  let AltNames = alt;
24}
25
26def sub_32 : SubRegIndex<32>;
27class LoongArchReg64<LoongArchReg32 subreg>
28    : Register<""> {
29  let HWEncoding = subreg.HWEncoding;
30  let SubRegs = [subreg];
31  let SubRegIndices = [sub_32];
32  let AsmName = subreg.AsmName;
33  let AltNames = subreg.AltNames;
34}
35
36let FallbackRegAltNameIndex = NoRegAltName in
37def RegAliasName : RegAltNameIndex;
38} // Namespace = "LoongArch"
39
40// Integer registers
41
42let RegAltNameIndices = [RegAliasName] in {
43  let isConstant = true in
44  def R0  : LoongArchReg<0,  "r0", ["zero"]>, DwarfRegNum<[0]>;
45  def R1  : LoongArchReg<1,  "r1", ["ra"]>, DwarfRegNum<[1]>;
46  def R2  : LoongArchReg<2,  "r2", ["tp"]>, DwarfRegNum<[2]>;
47  def R3  : LoongArchReg<3,  "r3", ["sp"]>, DwarfRegNum<[3]>;
48  def R4  : LoongArchReg<4,  "r4", ["a0"]>, DwarfRegNum<[4]>;
49  def R5  : LoongArchReg<5,  "r5", ["a1"]>, DwarfRegNum<[5]>;
50  def R6  : LoongArchReg<6,  "r6", ["a2"]>, DwarfRegNum<[6]>;
51  def R7  : LoongArchReg<7,  "r7", ["a3"]>, DwarfRegNum<[7]>;
52  def R8  : LoongArchReg<8,  "r8", ["a4"]>, DwarfRegNum<[8]>;
53  def R9  : LoongArchReg<9,  "r9", ["a5"]>, DwarfRegNum<[9]>;
54  def R10 : LoongArchReg<10, "r10", ["a6"]>, DwarfRegNum<[10]>;
55  def R11 : LoongArchReg<11, "r11", ["a7"]>, DwarfRegNum<[11]>;
56  def R12 : LoongArchReg<12, "r12", ["t0"]>, DwarfRegNum<[12]>;
57  def R13 : LoongArchReg<13, "r13", ["t1"]>, DwarfRegNum<[13]>;
58  def R14 : LoongArchReg<14, "r14", ["t2"]>, DwarfRegNum<[14]>;
59  def R15 : LoongArchReg<15, "r15", ["t3"]>, DwarfRegNum<[15]>;
60  def R16 : LoongArchReg<16, "r16", ["t4"]>, DwarfRegNum<[16]>;
61  def R17 : LoongArchReg<17, "r17", ["t5"]>, DwarfRegNum<[17]>;
62  def R18 : LoongArchReg<18, "r18", ["t6"]>, DwarfRegNum<[18]>;
63  def R19 : LoongArchReg<19, "r19", ["t7"]>, DwarfRegNum<[19]>;
64  def R20 : LoongArchReg<20, "r20", ["t8"]>, DwarfRegNum<[20]>;
65  def R21 : LoongArchReg<21, "r21", [""]>, DwarfRegNum<[21]>;
66  def R22 : LoongArchReg<22, "r22", ["fp", "s9"]>, DwarfRegNum<[22]>;
67  def R23 : LoongArchReg<23, "r23", ["s0"]>, DwarfRegNum<[23]>;
68  def R24 : LoongArchReg<24, "r24", ["s1"]>, DwarfRegNum<[24]>;
69  def R25 : LoongArchReg<25, "r25", ["s2"]>, DwarfRegNum<[25]>;
70  def R26 : LoongArchReg<26, "r26", ["s3"]>, DwarfRegNum<[26]>;
71  def R27 : LoongArchReg<27, "r27", ["s4"]>, DwarfRegNum<[27]>;
72  def R28 : LoongArchReg<28, "r28", ["s5"]>, DwarfRegNum<[28]>;
73  def R29 : LoongArchReg<29, "r29", ["s6"]>, DwarfRegNum<[29]>;
74  def R30 : LoongArchReg<30, "r30", ["s7"]>, DwarfRegNum<[30]>;
75  def R31 : LoongArchReg<31, "r31", ["s8"]>, DwarfRegNum<[31]>;
76} // RegAltNameIndices = [RegAliasName]
77
78def GRLenVT : ValueTypeByHwMode<[LA32, LA64],
79                                [i32,  i64]>;
80def GRLenRI : RegInfoByHwMode<
81      [LA32,              LA64],
82      [RegInfo<32,32,32>, RegInfo<64,64,64>]>;
83
84// The order of registers represents the preferred allocation sequence.
85// Registers are listed in the order caller-save, callee-save, specials.
86def GPR : RegisterClass<"LoongArch", [GRLenVT], 32, (add
87    // Argument registers (a0...a7)
88    (sequence "R%u", 4, 11),
89    // Temporary registers (t0...t8)
90    (sequence "R%u", 12, 20),
91    // Static register (s9/fp, s0...s8)
92    (sequence "R%u", 22, 31),
93    // Specials (r0, ra, tp, sp)
94    (sequence "R%u", 0, 3),
95    // Reserved (Non-allocatable)
96    R21
97  )> {
98  let RegInfos = GRLenRI;
99}
100
101// GPR for indirect tail calls. We can't use callee-saved registers, as they are
102// restored to the saved value before the tail call, which would clobber a call
103// address.
104def GPRT : RegisterClass<"LoongArch", [GRLenVT], 32, (add
105    // a0...a7, t0...t8
106    (sequence "R%u", 4, 20)
107  )> {
108  let RegInfos = GRLenRI;
109}
110
111// Floating point registers
112
113let RegAltNameIndices = [RegAliasName] in {
114  def F0  : LoongArchReg32<0, "f0", ["fa0"]>, DwarfRegNum<[32]>;
115  def F1  : LoongArchReg32<1, "f1", ["fa1"]>, DwarfRegNum<[33]>;
116  def F2  : LoongArchReg32<2, "f2", ["fa2"]>, DwarfRegNum<[34]>;
117  def F3  : LoongArchReg32<3, "f3", ["fa3"]>, DwarfRegNum<[35]>;
118  def F4  : LoongArchReg32<4, "f4", ["fa4"]>, DwarfRegNum<[36]>;
119  def F5  : LoongArchReg32<5, "f5", ["fa5"]>, DwarfRegNum<[37]>;
120  def F6  : LoongArchReg32<6, "f6", ["fa6"]>, DwarfRegNum<[38]>;
121  def F7  : LoongArchReg32<7, "f7", ["fa7"]>, DwarfRegNum<[39]>;
122  def F8  : LoongArchReg32<8, "f8", ["ft0"]>, DwarfRegNum<[40]>;
123  def F9  : LoongArchReg32<9, "f9", ["ft1"]>, DwarfRegNum<[41]>;
124  def F10 : LoongArchReg32<10,"f10", ["ft2"]>, DwarfRegNum<[42]>;
125  def F11 : LoongArchReg32<11,"f11", ["ft3"]>, DwarfRegNum<[43]>;
126  def F12 : LoongArchReg32<12,"f12", ["ft4"]>, DwarfRegNum<[44]>;
127  def F13 : LoongArchReg32<13,"f13", ["ft5"]>, DwarfRegNum<[45]>;
128  def F14 : LoongArchReg32<14,"f14", ["ft6"]>, DwarfRegNum<[46]>;
129  def F15 : LoongArchReg32<15,"f15", ["ft7"]>, DwarfRegNum<[47]>;
130  def F16 : LoongArchReg32<16,"f16", ["ft8"]>, DwarfRegNum<[48]>;
131  def F17 : LoongArchReg32<17,"f17", ["ft9"]>, DwarfRegNum<[49]>;
132  def F18 : LoongArchReg32<18,"f18", ["ft10"]>, DwarfRegNum<[50]>;
133  def F19 : LoongArchReg32<19,"f19", ["ft11"]>, DwarfRegNum<[51]>;
134  def F20 : LoongArchReg32<20,"f20", ["ft12"]>, DwarfRegNum<[52]>;
135  def F21 : LoongArchReg32<21,"f21", ["ft13"]>, DwarfRegNum<[53]>;
136  def F22 : LoongArchReg32<22,"f22", ["ft14"]>, DwarfRegNum<[54]>;
137  def F23 : LoongArchReg32<23,"f23", ["ft15"]>, DwarfRegNum<[55]>;
138  def F24 : LoongArchReg32<24,"f24", ["fs0"]>, DwarfRegNum<[56]>;
139  def F25 : LoongArchReg32<25,"f25", ["fs1"]>, DwarfRegNum<[57]>;
140  def F26 : LoongArchReg32<26,"f26", ["fs2"]>, DwarfRegNum<[58]>;
141  def F27 : LoongArchReg32<27,"f27", ["fs3"]>, DwarfRegNum<[59]>;
142  def F28 : LoongArchReg32<28,"f28", ["fs4"]>, DwarfRegNum<[60]>;
143  def F29 : LoongArchReg32<29,"f29", ["fs5"]>, DwarfRegNum<[61]>;
144  def F30 : LoongArchReg32<30,"f30", ["fs6"]>, DwarfRegNum<[62]>;
145  def F31 : LoongArchReg32<31,"f31", ["fs7"]>, DwarfRegNum<[63]>;
146
147  foreach I = 0-31 in {
148    def F#I#_64 : LoongArchReg64<!cast<LoongArchReg32>("F"#I)>,
149      DwarfRegNum<[!add(I, 32)]>;
150  }
151}
152
153// The order of registers represents the preferred allocation sequence.
154def FPR32 : RegisterClass<"LoongArch", [f32], 32, (sequence "F%u", 0, 31)>;
155def FPR64 : RegisterClass<"LoongArch", [f64], 64, (sequence "F%u_64", 0, 31)>;
156
157// Condition flag registers
158
159foreach I = 0-7 in
160def FCC#I : LoongArchReg<I, "fcc"#I>;
161
162def CFR : RegisterClass<"LoongArch", [GRLenVT], 32, (sequence "FCC%u", 0, 7)> {
163  let RegInfos = GRLenRI;
164}
165
166// Control and status registers
167
168foreach I = 0-3 in
169def FCSR#I : LoongArchReg<I, "fcsr"#I>;
170
171let isAllocatable = false in
172def FCSR : RegisterClass<"LoongArch", [i32], 32, (sequence "FCSR%u", 0, 3)>;
173