1//===-- M68kInstrShiftRotate.td - Logical Instrs -----------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file describes the logical instructions in the M68k architecture.
11/// Here is the current status of the file:
12///
13///  Machine:
14///
15///    SHL     [~]   ASR     [~]   LSR      [~]   SWAP     [ ]
16///    ROL     [~]   ROR     [~]   ROXL     [ ]   ROXR     [ ]
17///
18///  Map:
19///
20///   [ ] - was not touched at all
21///   [!] - requires extarnal stuff implemented
22///   [~] - in progress but usable
23///   [x] - done
24///
25//===----------------------------------------------------------------------===//
26
27def MxRODI_R : MxBead1Bit<0>;
28def MxRODI_L : MxBead1Bit<1>;
29
30def MxROOP_AS  : MxBead2Bits<0b00>;
31def MxROOP_LS  : MxBead2Bits<0b01>;
32def MxROOP_ROX : MxBead2Bits<0b10>;
33def MxROOP_RO  : MxBead2Bits<0b11>;
34
35/// ------------+---------+---+------+---+------+---------
36///  F  E  D  C | B  A  9 | 8 | 7  6 | 5 | 4  3 | 2  1  0
37/// ------------+---------+---+------+---+------+---------
38///  1  1  1  0 | REG/IMM | D | SIZE |R/I|  OP  |   REG
39/// ------------+---------+---+------+---+------+---------
40class MxSREncoding_R<MxBead1Bit DIRECTION, MxBead2Bits ROOP, MxEncSize SIZE>
41    : MxEncoding<MxBeadDReg<0>, ROOP, MxBead1Bit<1>, SIZE, DIRECTION,
42                 MxBeadDReg<2>, MxBead4Bits<0b1110>>;
43
44class MxSREncoding_I<MxBead1Bit DIRECTION, MxBead2Bits ROOP, MxEncSize SIZE>
45    : MxEncoding<MxBeadDReg<0>, ROOP, MxBead1Bit<0>, SIZE, DIRECTION,
46                 MxBead3Imm<2, 1>, MxBead4Bits<0b1110>>;
47
48// $reg <- $reg op $reg
49class MxSR_DD<string MN, MxType TYPE, SDNode NODE,
50              MxBead1Bit RODI, MxBead2Bits ROOP>
51    : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, TYPE.ROp:$opd),
52             MN#"."#TYPE.Prefix#"\t$opd, $dst",
53             [(set TYPE.VT:$dst, (NODE TYPE.VT:$src, TYPE.VT:$opd))],
54             MxSREncoding_R<RODI, ROOP,
55                            !cast<MxEncSize>("MxEncSize"#TYPE.Size)>>;
56
57// $reg <- $reg op $imm
58class MxSR_DI<string MN, MxType TYPE, SDNode NODE,
59              MxBead1Bit RODI, MxBead2Bits ROOP>
60    : MxInst<(outs TYPE.ROp:$dst),
61             (ins TYPE.ROp:$src, !cast<Operand>("Mxi"#TYPE.Size#"imm"):$opd),
62             MN#"."#TYPE.Prefix#"\t$opd, $dst",
63             [(set TYPE.VT:$dst,
64                   (NODE TYPE.VT:$src,
65                         !cast<ImmLeaf>("Mximm"#TYPE.Size#"_1to8"):$opd))],
66             MxSREncoding_I<RODI, ROOP,
67                            !cast<MxEncSize>("MxEncSize"#TYPE.Size)>>;
68
69multiclass MxSROp<string MN, SDNode NODE, MxBead1Bit RODI, MxBead2Bits ROOP> {
70
71  let Defs = [CCR] in {
72  let Constraints = "$src = $dst" in {
73
74  def NAME#"8dd"  : MxSR_DD<MN, MxType8d,  NODE, RODI, ROOP>;
75  def NAME#"16dd" : MxSR_DD<MN, MxType16d, NODE, RODI, ROOP>;
76  def NAME#"32dd" : MxSR_DD<MN, MxType32d, NODE, RODI, ROOP>;
77
78  def NAME#"8di"  : MxSR_DI<MN, MxType8d,  NODE, RODI, ROOP>;
79  def NAME#"16di" : MxSR_DI<MN, MxType16d, NODE, RODI, ROOP>;
80  def NAME#"32di" : MxSR_DI<MN, MxType32d, NODE, RODI, ROOP>;
81
82  } // $src = $dst
83  } // Defs = [CCR]
84
85} // MxBiArOp_RF
86
87defm SHL : MxSROp<"lsl", shl, MxRODI_L, MxROOP_LS>;
88defm LSR : MxSROp<"lsr", srl, MxRODI_R, MxROOP_LS>;
89defm ASR : MxSROp<"asr", sra, MxRODI_R, MxROOP_AS>;
90
91defm ROL : MxSROp<"rol", rotl, MxRODI_L, MxROOP_RO>;
92defm ROR : MxSROp<"ror", rotr, MxRODI_R, MxROOP_RO>;
93