1 //===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file is part of the Mips Disassembler. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MCTargetDesc/MipsMCTargetDesc.h" 14 #include "Mips.h" 15 #include "TargetInfo/MipsTargetInfo.h" 16 #include "llvm/ADT/ArrayRef.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDecoderOps.h" 19 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCRegisterInfo.h" 22 #include "llvm/MC/MCSubtargetInfo.h" 23 #include "llvm/MC/TargetRegistry.h" 24 #include "llvm/Support/Compiler.h" 25 #include "llvm/Support/Debug.h" 26 #include "llvm/Support/ErrorHandling.h" 27 #include "llvm/Support/MathExtras.h" 28 #include "llvm/Support/raw_ostream.h" 29 #include <cassert> 30 #include <cstdint> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "mips-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 class MipsDisassembler : public MCDisassembler { 41 bool IsMicroMips; 42 bool IsBigEndian; 43 44 public: 45 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) 46 : MCDisassembler(STI, Ctx), 47 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), 48 IsBigEndian(IsBigEndian) {} 49 50 bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; } 51 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } 52 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } 53 54 bool hasMips32r6() const { 55 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 56 } 57 58 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; } 59 60 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } 61 62 bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; } 63 64 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } 65 66 bool hasCnMipsP() const { return STI.getFeatureBits()[Mips::FeatureCnMipsP]; } 67 68 bool hasCOP3() const { 69 // Only present in MIPS-I and MIPS-II 70 return !hasMips32() && !hasMips3(); 71 } 72 73 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 74 ArrayRef<uint8_t> Bytes, uint64_t Address, 75 raw_ostream &CStream) const override; 76 }; 77 78 } // end anonymous namespace 79 80 // Forward declare these because the autogenerated code will reference them. 81 // Definitions are further down. 82 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 83 uint64_t Address, 84 const MCDisassembler *Decoder); 85 86 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, 87 uint64_t Address, 88 const MCDisassembler *Decoder); 89 90 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo, 91 uint64_t Address, 92 const MCDisassembler *Decoder); 93 94 static DecodeStatus 95 DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 96 const MCDisassembler *Decoder); 97 98 static DecodeStatus 99 DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 100 const MCDisassembler *Decoder); 101 102 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 103 uint64_t Address, 104 const MCDisassembler *Decoder); 105 106 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned Insn, 107 uint64_t Address, 108 const MCDisassembler *Decoder); 109 110 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo, 111 uint64_t Address, 112 const MCDisassembler *Decoder); 113 114 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, 115 uint64_t Address, 116 const MCDisassembler *Decoder); 117 118 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, 119 uint64_t Address, 120 const MCDisassembler *Decoder); 121 122 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, 123 uint64_t Address, 124 const MCDisassembler *Decoder); 125 126 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo, 127 uint64_t Address, 128 const MCDisassembler *Decoder); 129 130 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 131 uint64_t Address, 132 const MCDisassembler *Decoder); 133 134 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned Insn, 135 uint64_t Address, 136 const MCDisassembler *Decoder); 137 138 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, 139 uint64_t Address, 140 const MCDisassembler *Decoder); 141 142 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo, 143 uint64_t Address, 144 const MCDisassembler *Decoder); 145 146 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo, 147 uint64_t Address, 148 const MCDisassembler *Decoder); 149 150 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo, 151 uint64_t Address, 152 const MCDisassembler *Decoder); 153 154 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo, 155 uint64_t Address, 156 const MCDisassembler *Decoder); 157 158 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo, 159 uint64_t Address, 160 const MCDisassembler *Decoder); 161 162 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo, 163 uint64_t Address, 164 const MCDisassembler *Decoder); 165 166 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo, 167 uint64_t Address, 168 const MCDisassembler *Decoder); 169 170 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo, 171 uint64_t Address, 172 const MCDisassembler *Decoder); 173 174 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo, 175 uint64_t Address, 176 const MCDisassembler *Decoder); 177 178 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo, 179 uint64_t Address, 180 const MCDisassembler *Decoder); 181 182 static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset, 183 uint64_t Address, 184 const MCDisassembler *Decoder); 185 186 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset, 187 uint64_t Address, 188 const MCDisassembler *Decoder); 189 190 static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn, 191 uint64_t Address, 192 const MCDisassembler *Decoder); 193 194 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset, 195 uint64_t Address, 196 const MCDisassembler *Decoder); 197 198 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset, 199 uint64_t Address, 200 const MCDisassembler *Decoder); 201 202 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset, 203 uint64_t Address, 204 const MCDisassembler *Decoder); 205 206 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 207 // shifted left by 1 bit. 208 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset, 209 uint64_t Address, 210 const MCDisassembler *Decoder); 211 212 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 213 // shifted left by 1 bit. 214 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset, 215 uint64_t Address, 216 const MCDisassembler *Decoder); 217 218 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 219 // shifted left by 1 bit. 220 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset, 221 uint64_t Address, 222 const MCDisassembler *Decoder); 223 224 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is 225 // shifted left by 1 bit. 226 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset, 227 uint64_t Address, 228 const MCDisassembler *Decoder); 229 230 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 231 // shifted left by 1 bit. 232 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn, 233 uint64_t Address, 234 const MCDisassembler *Decoder); 235 236 // DecodeJumpTargetXMM - Decode microMIPS jump and link exchange target, 237 // which is shifted left by 2 bit. 238 static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, unsigned Insn, 239 uint64_t Address, 240 const MCDisassembler *Decoder); 241 242 static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, 243 const MCDisassembler *Decoder); 244 245 static DecodeStatus DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address, 246 const MCDisassembler *Decoder); 247 248 static DecodeStatus DecodeLoadByte15(MCInst &Inst, unsigned Insn, 249 uint64_t Address, 250 const MCDisassembler *Decoder); 251 252 static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, 253 const MCDisassembler *Decoder); 254 255 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn, 256 uint64_t Address, 257 const MCDisassembler *Decoder); 258 259 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn, 260 uint64_t Address, 261 const MCDisassembler *Decoder); 262 263 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, unsigned Insn, 264 uint64_t Address, 265 const MCDisassembler *Decoder); 266 267 static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address, 268 const MCDisassembler *Decoder); 269 270 static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn, 271 uint64_t Address, 272 const MCDisassembler *Decoder); 273 274 static DecodeStatus DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address, 275 const MCDisassembler *Decoder); 276 277 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 278 uint64_t Address, 279 const MCDisassembler *Decoder); 280 281 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, unsigned Insn, 282 uint64_t Address, 283 const MCDisassembler *Decoder); 284 285 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn, 286 uint64_t Address, 287 const MCDisassembler *Decoder); 288 289 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn, 290 uint64_t Address, 291 const MCDisassembler *Decoder); 292 293 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn, 294 uint64_t Address, 295 const MCDisassembler *Decoder); 296 297 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, unsigned Insn, 298 uint64_t Address, 299 const MCDisassembler *Decoder); 300 301 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn, 302 uint64_t Address, 303 const MCDisassembler *Decoder); 304 305 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, unsigned Insn, 306 uint64_t Address, 307 const MCDisassembler *Decoder); 308 309 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, 310 const MCDisassembler *Decoder); 311 312 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 313 uint64_t Address, 314 const MCDisassembler *Decoder); 315 316 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, 317 const MCDisassembler *Decoder); 318 319 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, 320 const MCDisassembler *Decoder); 321 322 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 323 uint64_t Address, 324 const MCDisassembler *Decoder); 325 326 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 327 uint64_t Address, 328 const MCDisassembler *Decoder); 329 330 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, 331 uint64_t Address, 332 const MCDisassembler *Decoder); 333 334 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value, 335 uint64_t Address, 336 const MCDisassembler *Decoder); 337 338 static DecodeStatus DecodeLi16Imm(MCInst &Inst, unsigned Value, 339 uint64_t Address, 340 const MCDisassembler *Decoder); 341 342 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value, 343 uint64_t Address, 344 const MCDisassembler *Decoder); 345 346 template <unsigned Bits, int Offset, int Scale> 347 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 348 uint64_t Address, 349 const MCDisassembler *Decoder); 350 351 template <unsigned Bits, int Offset> 352 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, 353 uint64_t Address, 354 const MCDisassembler *Decoder) { 355 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address, 356 Decoder); 357 } 358 359 template <unsigned Bits, int Offset = 0, int ScaleBy = 1> 360 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 361 uint64_t Address, 362 const MCDisassembler *Decoder); 363 364 static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, 365 const MCDisassembler *Decoder); 366 367 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 368 uint64_t Address, 369 const MCDisassembler *Decoder); 370 371 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 372 uint64_t Address, 373 const MCDisassembler *Decoder); 374 375 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address, 376 const MCDisassembler *Decoder); 377 378 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 379 uint64_t Address, 380 const MCDisassembler *Decoder); 381 382 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 383 uint64_t Address, 384 const MCDisassembler *Decoder); 385 386 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 387 /// handle. 388 template <typename InsnType> 389 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 390 const MCDisassembler *Decoder); 391 392 template <typename InsnType> 393 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, 394 uint64_t Address, 395 const MCDisassembler *Decoder); 396 397 template <typename InsnType> 398 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 399 const MCDisassembler *Decoder); 400 401 template <typename InsnType> 402 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 403 uint64_t Address, 404 const MCDisassembler *Decoder); 405 406 template <typename InsnType> 407 static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, 408 uint64_t Address, 409 const MCDisassembler *Decoder); 410 411 template <typename InsnType> 412 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 413 uint64_t Address, 414 const MCDisassembler *Decoder); 415 416 template <typename InsnType> 417 static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, 418 uint64_t Address, 419 const MCDisassembler *Decoder); 420 421 template <typename InsnType> 422 static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, 423 uint64_t Address, 424 const MCDisassembler *Decoder); 425 426 template <typename InsnType> 427 static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, 428 uint64_t Address, 429 const MCDisassembler *Decoder); 430 431 template <typename InsnType> 432 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 433 uint64_t Address, 434 const MCDisassembler *Decoder); 435 436 template <typename InsnType> 437 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 438 uint64_t Address, 439 const MCDisassembler *Decoder); 440 441 template <typename InsnType> 442 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 443 uint64_t Address, 444 const MCDisassembler *Decoder); 445 446 template <typename InsnType> 447 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 448 uint64_t Address, 449 const MCDisassembler *Decoder); 450 451 template <typename InsnType> 452 static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, 453 uint64_t Address, 454 const MCDisassembler *Decoder); 455 456 template <typename InsnType> 457 static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, 458 uint64_t Address, 459 const MCDisassembler *Decoder); 460 461 template <typename InsnType> 462 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, 463 const MCDisassembler *Decoder); 464 465 template <typename InsnType> 466 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, 467 const MCDisassembler *Decoder); 468 469 template <typename InsnType> 470 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, 471 const MCDisassembler *Decoder); 472 473 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 474 uint64_t Address, 475 const MCDisassembler *Decoder); 476 477 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 478 uint64_t Address, 479 const MCDisassembler *Decoder); 480 481 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, 482 uint64_t Address, 483 const MCDisassembler *Decoder); 484 485 static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn, 486 uint64_t Address, 487 const MCDisassembler *Decoder); 488 489 static MCDisassembler *createMipsDisassembler( 490 const Target &T, 491 const MCSubtargetInfo &STI, 492 MCContext &Ctx) { 493 return new MipsDisassembler(STI, Ctx, true); 494 } 495 496 static MCDisassembler *createMipselDisassembler( 497 const Target &T, 498 const MCSubtargetInfo &STI, 499 MCContext &Ctx) { 500 return new MipsDisassembler(STI, Ctx, false); 501 } 502 503 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsDisassembler() { 504 // Register the disassembler. 505 TargetRegistry::RegisterMCDisassembler(getTheMipsTarget(), 506 createMipsDisassembler); 507 TargetRegistry::RegisterMCDisassembler(getTheMipselTarget(), 508 createMipselDisassembler); 509 TargetRegistry::RegisterMCDisassembler(getTheMips64Target(), 510 createMipsDisassembler); 511 TargetRegistry::RegisterMCDisassembler(getTheMips64elTarget(), 512 createMipselDisassembler); 513 } 514 515 #include "MipsGenDisassemblerTables.inc" 516 517 static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo) { 518 const MCRegisterInfo *RegInfo = D->getContext().getRegisterInfo(); 519 return *(RegInfo->getRegClass(RC).begin() + RegNo); 520 } 521 522 template <typename InsnType> 523 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 524 const MCDisassembler *Decoder) { 525 using DecodeFN = 526 DecodeStatus (*)(MCInst &, unsigned, uint64_t, const MCDisassembler *); 527 528 // The size of the n field depends on the element size 529 // The register class also depends on this. 530 InsnType tmp = fieldFromInstruction(insn, 17, 5); 531 unsigned NSize = 0; 532 DecodeFN RegDecoder = nullptr; 533 if ((tmp & 0x18) == 0x00) { // INSVE_B 534 NSize = 4; 535 RegDecoder = DecodeMSA128BRegisterClass; 536 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 537 NSize = 3; 538 RegDecoder = DecodeMSA128HRegisterClass; 539 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 540 NSize = 2; 541 RegDecoder = DecodeMSA128WRegisterClass; 542 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 543 NSize = 1; 544 RegDecoder = DecodeMSA128DRegisterClass; 545 } else 546 llvm_unreachable("Invalid encoding"); 547 548 assert(NSize != 0 && RegDecoder != nullptr); 549 550 // $wd 551 tmp = fieldFromInstruction(insn, 6, 5); 552 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 553 return MCDisassembler::Fail; 554 // $wd_in 555 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 556 return MCDisassembler::Fail; 557 // $n 558 tmp = fieldFromInstruction(insn, 16, NSize); 559 MI.addOperand(MCOperand::createImm(tmp)); 560 // $ws 561 tmp = fieldFromInstruction(insn, 11, 5); 562 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 563 return MCDisassembler::Fail; 564 // $n2 565 MI.addOperand(MCOperand::createImm(0)); 566 567 return MCDisassembler::Success; 568 } 569 570 template <typename InsnType> 571 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, 572 uint64_t Address, 573 const MCDisassembler *Decoder) { 574 InsnType Rs = fieldFromInstruction(insn, 16, 5); 575 InsnType Imm = fieldFromInstruction(insn, 0, 16); 576 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 577 Rs))); 578 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 579 Rs))); 580 MI.addOperand(MCOperand::createImm(Imm)); 581 582 return MCDisassembler::Success; 583 } 584 585 template <typename InsnType> 586 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 587 const MCDisassembler *Decoder) { 588 InsnType Rs = fieldFromInstruction(insn, 21, 5); 589 InsnType Imm = fieldFromInstruction(insn, 0, 16); 590 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 591 Rs))); 592 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 593 Rs))); 594 MI.addOperand(MCOperand::createImm(Imm)); 595 596 return MCDisassembler::Success; 597 } 598 599 template <typename InsnType> 600 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 601 uint64_t Address, 602 const MCDisassembler *Decoder) { 603 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 604 // (otherwise we would have matched the ADDI instruction from the earlier 605 // ISA's instead). 606 // 607 // We have: 608 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 609 // BOVC if rs >= rt 610 // BEQZALC if rs == 0 && rt != 0 611 // BEQC if rs < rt && rs != 0 612 613 InsnType Rs = fieldFromInstruction(insn, 21, 5); 614 InsnType Rt = fieldFromInstruction(insn, 16, 5); 615 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 616 bool HasRs = false; 617 618 if (Rs >= Rt) { 619 MI.setOpcode(Mips::BOVC); 620 HasRs = true; 621 } else if (Rs != 0 && Rs < Rt) { 622 MI.setOpcode(Mips::BEQC); 623 HasRs = true; 624 } else 625 MI.setOpcode(Mips::BEQZALC); 626 627 if (HasRs) 628 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 629 Rs))); 630 631 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 632 Rt))); 633 MI.addOperand(MCOperand::createImm(Imm)); 634 635 return MCDisassembler::Success; 636 } 637 638 template <typename InsnType> 639 static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, 640 uint64_t Address, 641 const MCDisassembler *Decoder) { 642 InsnType Rt = fieldFromInstruction(insn, 21, 5); 643 InsnType Rs = fieldFromInstruction(insn, 16, 5); 644 int64_t Imm = 0; 645 646 if (Rs >= Rt) { 647 MI.setOpcode(Mips::BOVC_MMR6); 648 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 649 Rt))); 650 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 651 Rs))); 652 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 653 } else if (Rs != 0 && Rs < Rt) { 654 MI.setOpcode(Mips::BEQC_MMR6); 655 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 656 Rs))); 657 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 658 Rt))); 659 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 660 } else { 661 MI.setOpcode(Mips::BEQZALC_MMR6); 662 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 663 Rt))); 664 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 665 } 666 667 MI.addOperand(MCOperand::createImm(Imm)); 668 669 return MCDisassembler::Success; 670 } 671 672 template <typename InsnType> 673 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 674 uint64_t Address, 675 const MCDisassembler *Decoder) { 676 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 677 // (otherwise we would have matched the ADDI instruction from the earlier 678 // ISA's instead). 679 // 680 // We have: 681 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 682 // BNVC if rs >= rt 683 // BNEZALC if rs == 0 && rt != 0 684 // BNEC if rs < rt && rs != 0 685 686 InsnType Rs = fieldFromInstruction(insn, 21, 5); 687 InsnType Rt = fieldFromInstruction(insn, 16, 5); 688 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 689 bool HasRs = false; 690 691 if (Rs >= Rt) { 692 MI.setOpcode(Mips::BNVC); 693 HasRs = true; 694 } else if (Rs != 0 && Rs < Rt) { 695 MI.setOpcode(Mips::BNEC); 696 HasRs = true; 697 } else 698 MI.setOpcode(Mips::BNEZALC); 699 700 if (HasRs) 701 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 702 Rs))); 703 704 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 705 Rt))); 706 MI.addOperand(MCOperand::createImm(Imm)); 707 708 return MCDisassembler::Success; 709 } 710 711 template <typename InsnType> 712 static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, 713 uint64_t Address, 714 const MCDisassembler *Decoder) { 715 InsnType Rt = fieldFromInstruction(insn, 21, 5); 716 InsnType Rs = fieldFromInstruction(insn, 16, 5); 717 int64_t Imm = 0; 718 719 if (Rs >= Rt) { 720 MI.setOpcode(Mips::BNVC_MMR6); 721 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 722 Rt))); 723 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 724 Rs))); 725 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 726 } else if (Rs != 0 && Rs < Rt) { 727 MI.setOpcode(Mips::BNEC_MMR6); 728 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 729 Rs))); 730 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 731 Rt))); 732 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 733 } else { 734 MI.setOpcode(Mips::BNEZALC_MMR6); 735 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 736 Rt))); 737 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 738 } 739 740 MI.addOperand(MCOperand::createImm(Imm)); 741 742 return MCDisassembler::Success; 743 } 744 745 template <typename InsnType> 746 static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, 747 uint64_t Address, 748 const MCDisassembler *Decoder) { 749 // We have: 750 // 0b110101 ttttt sssss iiiiiiiiiiiiiiii 751 // Invalid if rt == 0 752 // BGTZC_MMR6 if rs == 0 && rt != 0 753 // BLTZC_MMR6 if rs == rt && rt != 0 754 // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0 755 756 InsnType Rt = fieldFromInstruction(insn, 21, 5); 757 InsnType Rs = fieldFromInstruction(insn, 16, 5); 758 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 759 bool HasRs = false; 760 761 if (Rt == 0) 762 return MCDisassembler::Fail; 763 else if (Rs == 0) 764 MI.setOpcode(Mips::BGTZC_MMR6); 765 else if (Rs == Rt) 766 MI.setOpcode(Mips::BLTZC_MMR6); 767 else { 768 MI.setOpcode(Mips::BLTC_MMR6); 769 HasRs = true; 770 } 771 772 if (HasRs) 773 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 774 Rs))); 775 776 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 777 Rt))); 778 779 MI.addOperand(MCOperand::createImm(Imm)); 780 781 return MCDisassembler::Success; 782 } 783 784 template <typename InsnType> 785 static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, 786 uint64_t Address, 787 const MCDisassembler *Decoder) { 788 // We have: 789 // 0b111101 ttttt sssss iiiiiiiiiiiiiiii 790 // Invalid if rt == 0 791 // BLEZC_MMR6 if rs == 0 && rt != 0 792 // BGEZC_MMR6 if rs == rt && rt != 0 793 // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0 794 795 InsnType Rt = fieldFromInstruction(insn, 21, 5); 796 InsnType Rs = fieldFromInstruction(insn, 16, 5); 797 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 798 bool HasRs = false; 799 800 if (Rt == 0) 801 return MCDisassembler::Fail; 802 else if (Rs == 0) 803 MI.setOpcode(Mips::BLEZC_MMR6); 804 else if (Rs == Rt) 805 MI.setOpcode(Mips::BGEZC_MMR6); 806 else { 807 HasRs = true; 808 MI.setOpcode(Mips::BGEC_MMR6); 809 } 810 811 if (HasRs) 812 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 813 Rs))); 814 815 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 816 Rt))); 817 818 MI.addOperand(MCOperand::createImm(Imm)); 819 820 return MCDisassembler::Success; 821 } 822 823 template <typename InsnType> 824 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 825 uint64_t Address, 826 const MCDisassembler *Decoder) { 827 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 828 // (otherwise we would have matched the BLEZL instruction from the earlier 829 // ISA's instead). 830 // 831 // We have: 832 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 833 // Invalid if rs == 0 834 // BLEZC if rs == 0 && rt != 0 835 // BGEZC if rs == rt && rt != 0 836 // BGEC if rs != rt && rs != 0 && rt != 0 837 838 InsnType Rs = fieldFromInstruction(insn, 21, 5); 839 InsnType Rt = fieldFromInstruction(insn, 16, 5); 840 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 841 bool HasRs = false; 842 843 if (Rt == 0) 844 return MCDisassembler::Fail; 845 else if (Rs == 0) 846 MI.setOpcode(Mips::BLEZC); 847 else if (Rs == Rt) 848 MI.setOpcode(Mips::BGEZC); 849 else { 850 HasRs = true; 851 MI.setOpcode(Mips::BGEC); 852 } 853 854 if (HasRs) 855 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 856 Rs))); 857 858 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 859 Rt))); 860 861 MI.addOperand(MCOperand::createImm(Imm)); 862 863 return MCDisassembler::Success; 864 } 865 866 template <typename InsnType> 867 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 868 uint64_t Address, 869 const MCDisassembler *Decoder) { 870 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 871 // (otherwise we would have matched the BGTZL instruction from the earlier 872 // ISA's instead). 873 // 874 // We have: 875 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 876 // Invalid if rs == 0 877 // BGTZC if rs == 0 && rt != 0 878 // BLTZC if rs == rt && rt != 0 879 // BLTC if rs != rt && rs != 0 && rt != 0 880 881 bool HasRs = false; 882 883 InsnType Rs = fieldFromInstruction(insn, 21, 5); 884 InsnType Rt = fieldFromInstruction(insn, 16, 5); 885 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 886 887 if (Rt == 0) 888 return MCDisassembler::Fail; 889 else if (Rs == 0) 890 MI.setOpcode(Mips::BGTZC); 891 else if (Rs == Rt) 892 MI.setOpcode(Mips::BLTZC); 893 else { 894 MI.setOpcode(Mips::BLTC); 895 HasRs = true; 896 } 897 898 if (HasRs) 899 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 900 Rs))); 901 902 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 903 Rt))); 904 905 MI.addOperand(MCOperand::createImm(Imm)); 906 907 return MCDisassembler::Success; 908 } 909 910 template <typename InsnType> 911 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 912 uint64_t Address, 913 const MCDisassembler *Decoder) { 914 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 915 // (otherwise we would have matched the BGTZ instruction from the earlier 916 // ISA's instead). 917 // 918 // We have: 919 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 920 // BGTZ if rt == 0 921 // BGTZALC if rs == 0 && rt != 0 922 // BLTZALC if rs != 0 && rs == rt 923 // BLTUC if rs != 0 && rs != rt 924 925 InsnType Rs = fieldFromInstruction(insn, 21, 5); 926 InsnType Rt = fieldFromInstruction(insn, 16, 5); 927 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 928 bool HasRs = false; 929 bool HasRt = false; 930 931 if (Rt == 0) { 932 MI.setOpcode(Mips::BGTZ); 933 HasRs = true; 934 } else if (Rs == 0) { 935 MI.setOpcode(Mips::BGTZALC); 936 HasRt = true; 937 } else if (Rs == Rt) { 938 MI.setOpcode(Mips::BLTZALC); 939 HasRs = true; 940 } else { 941 MI.setOpcode(Mips::BLTUC); 942 HasRs = true; 943 HasRt = true; 944 } 945 946 if (HasRs) 947 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 948 Rs))); 949 950 if (HasRt) 951 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 952 Rt))); 953 954 MI.addOperand(MCOperand::createImm(Imm)); 955 956 return MCDisassembler::Success; 957 } 958 959 template <typename InsnType> 960 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 961 uint64_t Address, 962 const MCDisassembler *Decoder) { 963 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 964 // (otherwise we would have matched the BLEZL instruction from the earlier 965 // ISA's instead). 966 // 967 // We have: 968 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 969 // Invalid if rs == 0 970 // BLEZALC if rs == 0 && rt != 0 971 // BGEZALC if rs == rt && rt != 0 972 // BGEUC if rs != rt && rs != 0 && rt != 0 973 974 InsnType Rs = fieldFromInstruction(insn, 21, 5); 975 InsnType Rt = fieldFromInstruction(insn, 16, 5); 976 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 977 bool HasRs = false; 978 979 if (Rt == 0) 980 return MCDisassembler::Fail; 981 else if (Rs == 0) 982 MI.setOpcode(Mips::BLEZALC); 983 else if (Rs == Rt) 984 MI.setOpcode(Mips::BGEZALC); 985 else { 986 HasRs = true; 987 MI.setOpcode(Mips::BGEUC); 988 } 989 990 if (HasRs) 991 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 992 Rs))); 993 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 994 Rt))); 995 996 MI.addOperand(MCOperand::createImm(Imm)); 997 998 return MCDisassembler::Success; 999 } 1000 1001 // Override the generated disassembler to produce DEXT all the time. This is 1002 // for feature / behaviour parity with binutils. 1003 template <typename InsnType> 1004 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, 1005 const MCDisassembler *Decoder) { 1006 unsigned Msbd = fieldFromInstruction(Insn, 11, 5); 1007 unsigned Lsb = fieldFromInstruction(Insn, 6, 5); 1008 unsigned Size = 0; 1009 unsigned Pos = 0; 1010 1011 switch (MI.getOpcode()) { 1012 case Mips::DEXT: 1013 Pos = Lsb; 1014 Size = Msbd + 1; 1015 break; 1016 case Mips::DEXTM: 1017 Pos = Lsb; 1018 Size = Msbd + 1 + 32; 1019 break; 1020 case Mips::DEXTU: 1021 Pos = Lsb + 32; 1022 Size = Msbd + 1; 1023 break; 1024 default: 1025 llvm_unreachable("Unknown DEXT instruction!"); 1026 } 1027 1028 MI.setOpcode(Mips::DEXT); 1029 1030 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1031 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1032 1033 MI.addOperand( 1034 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); 1035 MI.addOperand( 1036 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); 1037 MI.addOperand(MCOperand::createImm(Pos)); 1038 MI.addOperand(MCOperand::createImm(Size)); 1039 1040 return MCDisassembler::Success; 1041 } 1042 1043 // Override the generated disassembler to produce DINS all the time. This is 1044 // for feature / behaviour parity with binutils. 1045 template <typename InsnType> 1046 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, 1047 const MCDisassembler *Decoder) { 1048 unsigned Msbd = fieldFromInstruction(Insn, 11, 5); 1049 unsigned Lsb = fieldFromInstruction(Insn, 6, 5); 1050 unsigned Size = 0; 1051 unsigned Pos = 0; 1052 1053 switch (MI.getOpcode()) { 1054 case Mips::DINS: 1055 Pos = Lsb; 1056 Size = Msbd + 1 - Pos; 1057 break; 1058 case Mips::DINSM: 1059 Pos = Lsb; 1060 Size = Msbd + 33 - Pos; 1061 break; 1062 case Mips::DINSU: 1063 Pos = Lsb + 32; 1064 // mbsd = pos + size - 33 1065 // mbsd - pos + 33 = size 1066 Size = Msbd + 33 - Pos; 1067 break; 1068 default: 1069 llvm_unreachable("Unknown DINS instruction!"); 1070 } 1071 1072 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1073 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1074 1075 MI.setOpcode(Mips::DINS); 1076 MI.addOperand( 1077 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); 1078 MI.addOperand( 1079 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); 1080 MI.addOperand(MCOperand::createImm(Pos)); 1081 MI.addOperand(MCOperand::createImm(Size)); 1082 1083 return MCDisassembler::Success; 1084 } 1085 1086 // Auto-generated decoder wouldn't add the third operand for CRC32*. 1087 template <typename InsnType> 1088 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, 1089 const MCDisassembler *Decoder) { 1090 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1091 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1092 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1093 Rt))); 1094 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1095 Rs))); 1096 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1097 Rt))); 1098 return MCDisassembler::Success; 1099 } 1100 1101 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 1102 /// according to the given endianness. 1103 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 1104 uint64_t &Size, uint32_t &Insn, 1105 bool IsBigEndian) { 1106 // We want to read exactly 2 Bytes of data. 1107 if (Bytes.size() < 2) { 1108 Size = 0; 1109 return MCDisassembler::Fail; 1110 } 1111 1112 if (IsBigEndian) { 1113 Insn = (Bytes[0] << 8) | Bytes[1]; 1114 } else { 1115 Insn = (Bytes[1] << 8) | Bytes[0]; 1116 } 1117 1118 return MCDisassembler::Success; 1119 } 1120 1121 /// Read four bytes from the ArrayRef and return 32 bit word sorted 1122 /// according to the given endianness. 1123 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 1124 uint64_t &Size, uint32_t &Insn, 1125 bool IsBigEndian, bool IsMicroMips) { 1126 // We want to read exactly 4 Bytes of data. 1127 if (Bytes.size() < 4) { 1128 Size = 0; 1129 return MCDisassembler::Fail; 1130 } 1131 1132 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 1133 // always precede the low 16 bits in the instruction stream (that is, they 1134 // are placed at lower addresses in the instruction stream). 1135 // 1136 // microMIPS byte ordering: 1137 // Big-endian: 0 | 1 | 2 | 3 1138 // Little-endian: 1 | 0 | 3 | 2 1139 1140 if (IsBigEndian) { 1141 // Encoded as a big-endian 32-bit word in the stream. 1142 Insn = 1143 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 1144 } else { 1145 if (IsMicroMips) { 1146 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 1147 (Bytes[1] << 24); 1148 } else { 1149 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 1150 (Bytes[3] << 24); 1151 } 1152 } 1153 1154 return MCDisassembler::Success; 1155 } 1156 1157 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 1158 ArrayRef<uint8_t> Bytes, 1159 uint64_t Address, 1160 raw_ostream &CStream) const { 1161 uint32_t Insn; 1162 DecodeStatus Result; 1163 Size = 0; 1164 1165 if (IsMicroMips) { 1166 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 1167 if (Result == MCDisassembler::Fail) 1168 return MCDisassembler::Fail; 1169 1170 if (hasMips32r6()) { 1171 LLVM_DEBUG( 1172 dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); 1173 // Calling the auto-generated decoder function for microMIPS32R6 1174 // 16-bit instructions. 1175 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, 1176 Address, this, STI); 1177 if (Result != MCDisassembler::Fail) { 1178 Size = 2; 1179 return Result; 1180 } 1181 } 1182 1183 LLVM_DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 1184 // Calling the auto-generated decoder function for microMIPS 16-bit 1185 // instructions. 1186 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 1187 this, STI); 1188 if (Result != MCDisassembler::Fail) { 1189 Size = 2; 1190 return Result; 1191 } 1192 1193 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 1194 if (Result == MCDisassembler::Fail) 1195 return MCDisassembler::Fail; 1196 1197 if (hasMips32r6()) { 1198 LLVM_DEBUG( 1199 dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); 1200 // Calling the auto-generated decoder function. 1201 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, 1202 Address, this, STI); 1203 if (Result != MCDisassembler::Fail) { 1204 Size = 4; 1205 return Result; 1206 } 1207 } 1208 1209 LLVM_DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 1210 // Calling the auto-generated decoder function. 1211 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 1212 this, STI); 1213 if (Result != MCDisassembler::Fail) { 1214 Size = 4; 1215 return Result; 1216 } 1217 1218 if (isFP64()) { 1219 LLVM_DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n"); 1220 Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn, 1221 Address, this, STI); 1222 if (Result != MCDisassembler::Fail) { 1223 Size = 4; 1224 return Result; 1225 } 1226 } 1227 1228 // This is an invalid instruction. Claim that the Size is 2 bytes. Since 1229 // microMIPS instructions have a minimum alignment of 2, the next 2 bytes 1230 // could form a valid instruction. The two bytes we rejected as an 1231 // instruction could have actually beeen an inline constant pool that is 1232 // unconditionally branched over. 1233 Size = 2; 1234 return MCDisassembler::Fail; 1235 } 1236 1237 // Attempt to read the instruction so that we can attempt to decode it. If 1238 // the buffer is not 4 bytes long, let the higher level logic figure out 1239 // what to do with a size of zero and MCDisassembler::Fail. 1240 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 1241 if (Result == MCDisassembler::Fail) 1242 return MCDisassembler::Fail; 1243 1244 // The only instruction size for standard encoded MIPS. 1245 Size = 4; 1246 1247 if (hasCOP3()) { 1248 LLVM_DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 1249 Result = 1250 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 1251 if (Result != MCDisassembler::Fail) 1252 return Result; 1253 } 1254 1255 if (hasMips32r6() && isGP64()) { 1256 LLVM_DEBUG( 1257 dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 1258 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 1259 Address, this, STI); 1260 if (Result != MCDisassembler::Fail) 1261 return Result; 1262 } 1263 1264 if (hasMips32r6() && isPTR64()) { 1265 LLVM_DEBUG( 1266 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1267 Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn, 1268 Address, this, STI); 1269 if (Result != MCDisassembler::Fail) 1270 return Result; 1271 } 1272 1273 if (hasMips32r6()) { 1274 LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 1275 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 1276 Address, this, STI); 1277 if (Result != MCDisassembler::Fail) 1278 return Result; 1279 } 1280 1281 if (hasMips2() && isPTR64()) { 1282 LLVM_DEBUG( 1283 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1284 Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn, 1285 Address, this, STI); 1286 if (Result != MCDisassembler::Fail) 1287 return Result; 1288 } 1289 1290 if (hasCnMips()) { 1291 LLVM_DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); 1292 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, 1293 Address, this, STI); 1294 if (Result != MCDisassembler::Fail) 1295 return Result; 1296 } 1297 1298 if (hasCnMipsP()) { 1299 LLVM_DEBUG(dbgs() << "Trying CnMipsP table (32-bit opcodes):\n"); 1300 Result = decodeInstruction(DecoderTableCnMipsP32, Instr, Insn, 1301 Address, this, STI); 1302 if (Result != MCDisassembler::Fail) 1303 return Result; 1304 } 1305 1306 if (isGP64()) { 1307 LLVM_DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); 1308 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, 1309 Address, this, STI); 1310 if (Result != MCDisassembler::Fail) 1311 return Result; 1312 } 1313 1314 if (isFP64()) { 1315 LLVM_DEBUG( 1316 dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n"); 1317 Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn, 1318 Address, this, STI); 1319 if (Result != MCDisassembler::Fail) 1320 return Result; 1321 } 1322 1323 LLVM_DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 1324 // Calling the auto-generated decoder function. 1325 Result = 1326 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 1327 if (Result != MCDisassembler::Fail) 1328 return Result; 1329 1330 return MCDisassembler::Fail; 1331 } 1332 1333 static DecodeStatus 1334 DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1335 const MCDisassembler *Decoder) { 1336 return MCDisassembler::Fail; 1337 } 1338 1339 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 1340 uint64_t Address, 1341 const MCDisassembler *Decoder) { 1342 if (RegNo > 31) 1343 return MCDisassembler::Fail; 1344 1345 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 1346 Inst.addOperand(MCOperand::createReg(Reg)); 1347 return MCDisassembler::Success; 1348 } 1349 1350 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo, 1351 uint64_t Address, 1352 const MCDisassembler *Decoder) { 1353 if (RegNo > 7) 1354 return MCDisassembler::Fail; 1355 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 1356 Inst.addOperand(MCOperand::createReg(Reg)); 1357 return MCDisassembler::Success; 1358 } 1359 1360 static DecodeStatus 1361 DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1362 const MCDisassembler *Decoder) { 1363 if (RegNo > 7) 1364 return MCDisassembler::Fail; 1365 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 1366 Inst.addOperand(MCOperand::createReg(Reg)); 1367 return MCDisassembler::Success; 1368 } 1369 1370 static DecodeStatus 1371 DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1372 const MCDisassembler *Decoder) { 1373 if (RegNo > 7) 1374 return MCDisassembler::Fail; 1375 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); 1376 Inst.addOperand(MCOperand::createReg(Reg)); 1377 return MCDisassembler::Success; 1378 } 1379 1380 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 1381 uint64_t Address, 1382 const MCDisassembler *Decoder) { 1383 if (RegNo > 31) 1384 return MCDisassembler::Fail; 1385 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 1386 Inst.addOperand(MCOperand::createReg(Reg)); 1387 return MCDisassembler::Success; 1388 } 1389 1390 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned RegNo, 1391 uint64_t Address, 1392 const MCDisassembler *Decoder) { 1393 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) 1394 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1395 1396 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1397 } 1398 1399 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1400 uint64_t Address, 1401 const MCDisassembler *Decoder) { 1402 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1403 } 1404 1405 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, 1406 uint64_t Address, 1407 const MCDisassembler *Decoder) { 1408 if (RegNo > 31) 1409 return MCDisassembler::Fail; 1410 1411 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1412 Inst.addOperand(MCOperand::createReg(Reg)); 1413 return MCDisassembler::Success; 1414 } 1415 1416 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, 1417 uint64_t Address, 1418 const MCDisassembler *Decoder) { 1419 if (RegNo > 31) 1420 return MCDisassembler::Fail; 1421 1422 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1423 Inst.addOperand(MCOperand::createReg(Reg)); 1424 return MCDisassembler::Success; 1425 } 1426 1427 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, 1428 uint64_t Address, 1429 const MCDisassembler *Decoder) { 1430 if (RegNo > 31) 1431 return MCDisassembler::Fail; 1432 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1433 Inst.addOperand(MCOperand::createReg(Reg)); 1434 return MCDisassembler::Success; 1435 } 1436 1437 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo, 1438 uint64_t Address, 1439 const MCDisassembler *Decoder) { 1440 if (RegNo > 7) 1441 return MCDisassembler::Fail; 1442 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1443 Inst.addOperand(MCOperand::createReg(Reg)); 1444 return MCDisassembler::Success; 1445 } 1446 1447 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1448 uint64_t Address, 1449 const MCDisassembler *Decoder) { 1450 if (RegNo > 31) 1451 return MCDisassembler::Fail; 1452 1453 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1454 Inst.addOperand(MCOperand::createReg(Reg)); 1455 return MCDisassembler::Success; 1456 } 1457 1458 static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, 1459 const MCDisassembler *Decoder) { 1460 int Offset = SignExtend32<16>(Insn & 0xffff); 1461 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1462 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1463 1464 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1465 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1466 1467 if (Inst.getOpcode() == Mips::SC || 1468 Inst.getOpcode() == Mips::SCD) 1469 Inst.addOperand(MCOperand::createReg(Reg)); 1470 1471 Inst.addOperand(MCOperand::createReg(Reg)); 1472 Inst.addOperand(MCOperand::createReg(Base)); 1473 Inst.addOperand(MCOperand::createImm(Offset)); 1474 1475 return MCDisassembler::Success; 1476 } 1477 1478 static DecodeStatus DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address, 1479 const MCDisassembler *Decoder) { 1480 int Offset = SignExtend32<9>(Insn >> 7); 1481 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1482 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1483 1484 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1485 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1486 1487 if (Inst.getOpcode() == Mips::SCE) 1488 Inst.addOperand(MCOperand::createReg(Reg)); 1489 1490 Inst.addOperand(MCOperand::createReg(Reg)); 1491 Inst.addOperand(MCOperand::createReg(Base)); 1492 Inst.addOperand(MCOperand::createImm(Offset)); 1493 1494 return MCDisassembler::Success; 1495 } 1496 1497 static DecodeStatus DecodeLoadByte15(MCInst &Inst, unsigned Insn, 1498 uint64_t Address, 1499 const MCDisassembler *Decoder) { 1500 int Offset = SignExtend32<16>(Insn & 0xffff); 1501 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1502 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1503 1504 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1505 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1506 1507 Inst.addOperand(MCOperand::createReg(Reg)); 1508 Inst.addOperand(MCOperand::createReg(Base)); 1509 Inst.addOperand(MCOperand::createImm(Offset)); 1510 1511 return MCDisassembler::Success; 1512 } 1513 1514 static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, 1515 const MCDisassembler *Decoder) { 1516 int Offset = SignExtend32<16>(Insn & 0xffff); 1517 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1518 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1519 1520 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1521 1522 Inst.addOperand(MCOperand::createReg(Base)); 1523 Inst.addOperand(MCOperand::createImm(Offset)); 1524 Inst.addOperand(MCOperand::createImm(Hint)); 1525 1526 return MCDisassembler::Success; 1527 } 1528 1529 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn, 1530 uint64_t Address, 1531 const MCDisassembler *Decoder) { 1532 int Offset = SignExtend32<12>(Insn & 0xfff); 1533 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1534 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1535 1536 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1537 1538 Inst.addOperand(MCOperand::createReg(Base)); 1539 Inst.addOperand(MCOperand::createImm(Offset)); 1540 Inst.addOperand(MCOperand::createImm(Hint)); 1541 1542 return MCDisassembler::Success; 1543 } 1544 1545 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, unsigned Insn, 1546 uint64_t Address, 1547 const MCDisassembler *Decoder) { 1548 int Offset = SignExtend32<9>(Insn & 0x1ff); 1549 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1550 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1551 1552 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1553 1554 Inst.addOperand(MCOperand::createReg(Base)); 1555 Inst.addOperand(MCOperand::createImm(Offset)); 1556 Inst.addOperand(MCOperand::createImm(Hint)); 1557 1558 return MCDisassembler::Success; 1559 } 1560 1561 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn, 1562 uint64_t Address, 1563 const MCDisassembler *Decoder) { 1564 int Offset = SignExtend32<9>(Insn >> 7); 1565 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1566 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1567 1568 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1569 1570 Inst.addOperand(MCOperand::createReg(Base)); 1571 Inst.addOperand(MCOperand::createImm(Offset)); 1572 Inst.addOperand(MCOperand::createImm(Hint)); 1573 1574 return MCDisassembler::Success; 1575 } 1576 1577 static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address, 1578 const MCDisassembler *Decoder) { 1579 int Offset = SignExtend32<16>(Insn & 0xffff); 1580 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1581 1582 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1583 1584 Inst.addOperand(MCOperand::createReg(Base)); 1585 Inst.addOperand(MCOperand::createImm(Offset)); 1586 1587 return MCDisassembler::Success; 1588 } 1589 1590 static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn, 1591 uint64_t Address, 1592 const MCDisassembler *Decoder) { 1593 int Offset = SignExtend32<16>(Insn & 0xffff); 1594 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1595 1596 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1597 1598 Inst.addOperand(MCOperand::createReg(Base)); 1599 Inst.addOperand(MCOperand::createImm(Offset)); 1600 1601 return MCDisassembler::Success; 1602 } 1603 1604 static DecodeStatus DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address, 1605 const MCDisassembler *Decoder) { 1606 int Immediate = SignExtend32<16>(Insn & 0xffff); 1607 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1608 1609 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1610 1611 Inst.addOperand(MCOperand::createReg(Base)); 1612 Inst.addOperand(MCOperand::createImm(Immediate)); 1613 1614 return MCDisassembler::Success; 1615 } 1616 1617 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1618 uint64_t Address, 1619 const MCDisassembler *Decoder) { 1620 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1621 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1622 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1623 1624 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1625 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1626 1627 Inst.addOperand(MCOperand::createReg(Reg)); 1628 Inst.addOperand(MCOperand::createReg(Base)); 1629 1630 // The immediate field of an LD/ST instruction is scaled which means it must 1631 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1632 // data format. 1633 // .b - 1 byte 1634 // .h - 2 bytes 1635 // .w - 4 bytes 1636 // .d - 8 bytes 1637 switch(Inst.getOpcode()) 1638 { 1639 default: 1640 assert(false && "Unexpected instruction"); 1641 return MCDisassembler::Fail; 1642 break; 1643 case Mips::LD_B: 1644 case Mips::ST_B: 1645 Inst.addOperand(MCOperand::createImm(Offset)); 1646 break; 1647 case Mips::LD_H: 1648 case Mips::ST_H: 1649 Inst.addOperand(MCOperand::createImm(Offset * 2)); 1650 break; 1651 case Mips::LD_W: 1652 case Mips::ST_W: 1653 Inst.addOperand(MCOperand::createImm(Offset * 4)); 1654 break; 1655 case Mips::LD_D: 1656 case Mips::ST_D: 1657 Inst.addOperand(MCOperand::createImm(Offset * 8)); 1658 break; 1659 } 1660 1661 return MCDisassembler::Success; 1662 } 1663 1664 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, unsigned Insn, 1665 uint64_t Address, 1666 const MCDisassembler *Decoder) { 1667 unsigned Offset = Insn & 0xf; 1668 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1669 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1670 1671 switch (Inst.getOpcode()) { 1672 case Mips::LBU16_MM: 1673 case Mips::LHU16_MM: 1674 case Mips::LW16_MM: 1675 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1676 == MCDisassembler::Fail) 1677 return MCDisassembler::Fail; 1678 break; 1679 case Mips::SB16_MM: 1680 case Mips::SB16_MMR6: 1681 case Mips::SH16_MM: 1682 case Mips::SH16_MMR6: 1683 case Mips::SW16_MM: 1684 case Mips::SW16_MMR6: 1685 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1686 == MCDisassembler::Fail) 1687 return MCDisassembler::Fail; 1688 break; 1689 } 1690 1691 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1692 == MCDisassembler::Fail) 1693 return MCDisassembler::Fail; 1694 1695 switch (Inst.getOpcode()) { 1696 case Mips::LBU16_MM: 1697 if (Offset == 0xf) 1698 Inst.addOperand(MCOperand::createImm(-1)); 1699 else 1700 Inst.addOperand(MCOperand::createImm(Offset)); 1701 break; 1702 case Mips::SB16_MM: 1703 case Mips::SB16_MMR6: 1704 Inst.addOperand(MCOperand::createImm(Offset)); 1705 break; 1706 case Mips::LHU16_MM: 1707 case Mips::SH16_MM: 1708 case Mips::SH16_MMR6: 1709 Inst.addOperand(MCOperand::createImm(Offset << 1)); 1710 break; 1711 case Mips::LW16_MM: 1712 case Mips::SW16_MM: 1713 case Mips::SW16_MMR6: 1714 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1715 break; 1716 } 1717 1718 return MCDisassembler::Success; 1719 } 1720 1721 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn, 1722 uint64_t Address, 1723 const MCDisassembler *Decoder) { 1724 unsigned Offset = Insn & 0x1F; 1725 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1726 1727 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1728 1729 Inst.addOperand(MCOperand::createReg(Reg)); 1730 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1731 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1732 1733 return MCDisassembler::Success; 1734 } 1735 1736 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn, 1737 uint64_t Address, 1738 const MCDisassembler *Decoder) { 1739 unsigned Offset = Insn & 0x7F; 1740 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1741 1742 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1743 1744 Inst.addOperand(MCOperand::createReg(Reg)); 1745 Inst.addOperand(MCOperand::createReg(Mips::GP)); 1746 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1747 1748 return MCDisassembler::Success; 1749 } 1750 1751 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn, 1752 uint64_t Address, 1753 const MCDisassembler *Decoder) { 1754 int Offset; 1755 switch (Inst.getOpcode()) { 1756 case Mips::LWM16_MMR6: 1757 case Mips::SWM16_MMR6: 1758 Offset = fieldFromInstruction(Insn, 4, 4); 1759 break; 1760 default: 1761 Offset = SignExtend32<4>(Insn & 0xf); 1762 break; 1763 } 1764 1765 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) 1766 == MCDisassembler::Fail) 1767 return MCDisassembler::Fail; 1768 1769 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1770 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1771 1772 return MCDisassembler::Success; 1773 } 1774 1775 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, unsigned Insn, 1776 uint64_t Address, 1777 const MCDisassembler *Decoder) { 1778 int Offset = SignExtend32<9>(Insn & 0x1ff); 1779 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1780 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1781 1782 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1783 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1784 1785 if (Inst.getOpcode() == Mips::SCE_MM || Inst.getOpcode() == Mips::SC_MMR6) 1786 Inst.addOperand(MCOperand::createReg(Reg)); 1787 1788 Inst.addOperand(MCOperand::createReg(Reg)); 1789 Inst.addOperand(MCOperand::createReg(Base)); 1790 Inst.addOperand(MCOperand::createImm(Offset)); 1791 1792 return MCDisassembler::Success; 1793 } 1794 1795 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn, 1796 uint64_t Address, 1797 const MCDisassembler *Decoder) { 1798 int Offset = SignExtend32<12>(Insn & 0x0fff); 1799 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1800 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1801 1802 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1803 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1804 1805 switch (Inst.getOpcode()) { 1806 case Mips::SWM32_MM: 1807 case Mips::LWM32_MM: 1808 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1809 == MCDisassembler::Fail) 1810 return MCDisassembler::Fail; 1811 Inst.addOperand(MCOperand::createReg(Base)); 1812 Inst.addOperand(MCOperand::createImm(Offset)); 1813 break; 1814 case Mips::SC_MM: 1815 Inst.addOperand(MCOperand::createReg(Reg)); 1816 LLVM_FALLTHROUGH; 1817 default: 1818 Inst.addOperand(MCOperand::createReg(Reg)); 1819 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) 1820 Inst.addOperand(MCOperand::createReg(Reg+1)); 1821 1822 Inst.addOperand(MCOperand::createReg(Base)); 1823 Inst.addOperand(MCOperand::createImm(Offset)); 1824 } 1825 1826 return MCDisassembler::Success; 1827 } 1828 1829 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, unsigned Insn, 1830 uint64_t Address, 1831 const MCDisassembler *Decoder) { 1832 int Offset = SignExtend32<16>(Insn & 0xffff); 1833 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1834 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1835 1836 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1837 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1838 1839 Inst.addOperand(MCOperand::createReg(Reg)); 1840 Inst.addOperand(MCOperand::createReg(Base)); 1841 Inst.addOperand(MCOperand::createImm(Offset)); 1842 1843 return MCDisassembler::Success; 1844 } 1845 1846 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, 1847 const MCDisassembler *Decoder) { 1848 int Offset = SignExtend32<16>(Insn & 0xffff); 1849 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1850 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1851 1852 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1853 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1854 1855 Inst.addOperand(MCOperand::createReg(Reg)); 1856 Inst.addOperand(MCOperand::createReg(Base)); 1857 Inst.addOperand(MCOperand::createImm(Offset)); 1858 1859 return MCDisassembler::Success; 1860 } 1861 1862 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 1863 uint64_t Address, 1864 const MCDisassembler *Decoder) { 1865 // This function is the same as DecodeFMem but with the Reg and Base fields 1866 // swapped according to microMIPS spec. 1867 int Offset = SignExtend32<16>(Insn & 0xffff); 1868 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1869 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1870 1871 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1872 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1873 1874 Inst.addOperand(MCOperand::createReg(Reg)); 1875 Inst.addOperand(MCOperand::createReg(Base)); 1876 Inst.addOperand(MCOperand::createImm(Offset)); 1877 1878 return MCDisassembler::Success; 1879 } 1880 1881 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, 1882 const MCDisassembler *Decoder) { 1883 int Offset = SignExtend32<16>(Insn & 0xffff); 1884 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1885 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1886 1887 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1888 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1889 1890 Inst.addOperand(MCOperand::createReg(Reg)); 1891 Inst.addOperand(MCOperand::createReg(Base)); 1892 Inst.addOperand(MCOperand::createImm(Offset)); 1893 1894 return MCDisassembler::Success; 1895 } 1896 1897 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, 1898 const MCDisassembler *Decoder) { 1899 int Offset = SignExtend32<16>(Insn & 0xffff); 1900 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1901 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1902 1903 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 1904 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1905 1906 Inst.addOperand(MCOperand::createReg(Reg)); 1907 Inst.addOperand(MCOperand::createReg(Base)); 1908 Inst.addOperand(MCOperand::createImm(Offset)); 1909 1910 return MCDisassembler::Success; 1911 } 1912 1913 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 1914 uint64_t Address, 1915 const MCDisassembler *Decoder) { 1916 int Offset = SignExtend32<11>(Insn & 0x07ff); 1917 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1918 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1919 1920 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1921 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1922 1923 Inst.addOperand(MCOperand::createReg(Reg)); 1924 Inst.addOperand(MCOperand::createReg(Base)); 1925 Inst.addOperand(MCOperand::createImm(Offset)); 1926 1927 return MCDisassembler::Success; 1928 } 1929 1930 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 1931 uint64_t Address, 1932 const MCDisassembler *Decoder) { 1933 int Offset = SignExtend32<11>(Insn & 0x07ff); 1934 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1935 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1936 1937 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1938 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1939 1940 Inst.addOperand(MCOperand::createReg(Reg)); 1941 Inst.addOperand(MCOperand::createReg(Base)); 1942 Inst.addOperand(MCOperand::createImm(Offset)); 1943 1944 return MCDisassembler::Success; 1945 } 1946 1947 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, 1948 uint64_t Address, 1949 const MCDisassembler *Decoder) { 1950 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 1951 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 1952 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1953 1954 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 1955 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1956 1957 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 1958 Inst.addOperand(MCOperand::createReg(Rt)); 1959 } 1960 1961 Inst.addOperand(MCOperand::createReg(Rt)); 1962 Inst.addOperand(MCOperand::createReg(Base)); 1963 Inst.addOperand(MCOperand::createImm(Offset)); 1964 1965 return MCDisassembler::Success; 1966 } 1967 1968 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned RegNo, 1969 uint64_t Address, 1970 const MCDisassembler *Decoder) { 1971 // Currently only hardware register 29 is supported. 1972 if (RegNo != 29) 1973 return MCDisassembler::Fail; 1974 Inst.addOperand(MCOperand::createReg(Mips::HWR29)); 1975 return MCDisassembler::Success; 1976 } 1977 1978 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, 1979 uint64_t Address, 1980 const MCDisassembler *Decoder) { 1981 if (RegNo > 30 || RegNo %2) 1982 return MCDisassembler::Fail; 1983 1984 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 1985 Inst.addOperand(MCOperand::createReg(Reg)); 1986 return MCDisassembler::Success; 1987 } 1988 1989 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo, 1990 uint64_t Address, 1991 const MCDisassembler *Decoder) { 1992 if (RegNo >= 4) 1993 return MCDisassembler::Fail; 1994 1995 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 1996 Inst.addOperand(MCOperand::createReg(Reg)); 1997 return MCDisassembler::Success; 1998 } 1999 2000 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo, 2001 uint64_t Address, 2002 const MCDisassembler *Decoder) { 2003 if (RegNo >= 4) 2004 return MCDisassembler::Fail; 2005 2006 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 2007 Inst.addOperand(MCOperand::createReg(Reg)); 2008 return MCDisassembler::Success; 2009 } 2010 2011 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo, 2012 uint64_t Address, 2013 const MCDisassembler *Decoder) { 2014 if (RegNo >= 4) 2015 return MCDisassembler::Fail; 2016 2017 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 2018 Inst.addOperand(MCOperand::createReg(Reg)); 2019 return MCDisassembler::Success; 2020 } 2021 2022 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo, 2023 uint64_t Address, 2024 const MCDisassembler *Decoder) { 2025 if (RegNo > 31) 2026 return MCDisassembler::Fail; 2027 2028 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 2029 Inst.addOperand(MCOperand::createReg(Reg)); 2030 return MCDisassembler::Success; 2031 } 2032 2033 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo, 2034 uint64_t Address, 2035 const MCDisassembler *Decoder) { 2036 if (RegNo > 31) 2037 return MCDisassembler::Fail; 2038 2039 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 2040 Inst.addOperand(MCOperand::createReg(Reg)); 2041 return MCDisassembler::Success; 2042 } 2043 2044 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo, 2045 uint64_t Address, 2046 const MCDisassembler *Decoder) { 2047 if (RegNo > 31) 2048 return MCDisassembler::Fail; 2049 2050 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 2051 Inst.addOperand(MCOperand::createReg(Reg)); 2052 return MCDisassembler::Success; 2053 } 2054 2055 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo, 2056 uint64_t Address, 2057 const MCDisassembler *Decoder) { 2058 if (RegNo > 31) 2059 return MCDisassembler::Fail; 2060 2061 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 2062 Inst.addOperand(MCOperand::createReg(Reg)); 2063 return MCDisassembler::Success; 2064 } 2065 2066 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo, 2067 uint64_t Address, 2068 const MCDisassembler *Decoder) { 2069 if (RegNo > 7) 2070 return MCDisassembler::Fail; 2071 2072 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 2073 Inst.addOperand(MCOperand::createReg(Reg)); 2074 return MCDisassembler::Success; 2075 } 2076 2077 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo, 2078 uint64_t Address, 2079 const MCDisassembler *Decoder) { 2080 if (RegNo > 31) 2081 return MCDisassembler::Fail; 2082 2083 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); 2084 Inst.addOperand(MCOperand::createReg(Reg)); 2085 return MCDisassembler::Success; 2086 } 2087 2088 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo, 2089 uint64_t Address, 2090 const MCDisassembler *Decoder) { 2091 if (RegNo > 31) 2092 return MCDisassembler::Fail; 2093 2094 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 2095 Inst.addOperand(MCOperand::createReg(Reg)); 2096 return MCDisassembler::Success; 2097 } 2098 2099 static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset, 2100 uint64_t Address, 2101 const MCDisassembler *Decoder) { 2102 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 2103 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2104 return MCDisassembler::Success; 2105 } 2106 2107 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset, 2108 uint64_t Address, 2109 const MCDisassembler *Decoder) { 2110 int32_t BranchOffset = (SignExtend32<16>(Offset) * 2); 2111 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2112 return MCDisassembler::Success; 2113 } 2114 2115 static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn, 2116 uint64_t Address, 2117 const MCDisassembler *Decoder) { 2118 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 2119 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2120 return MCDisassembler::Success; 2121 } 2122 2123 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset, 2124 uint64_t Address, 2125 const MCDisassembler *Decoder) { 2126 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2127 2128 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2129 return MCDisassembler::Success; 2130 } 2131 2132 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset, 2133 uint64_t Address, 2134 const MCDisassembler *Decoder) { 2135 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2136 2137 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2138 return MCDisassembler::Success; 2139 } 2140 2141 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset, 2142 uint64_t Address, 2143 const MCDisassembler *Decoder) { 2144 int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4; 2145 2146 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2147 return MCDisassembler::Success; 2148 } 2149 2150 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset, 2151 uint64_t Address, 2152 const MCDisassembler *Decoder) { 2153 int32_t BranchOffset = SignExtend32<8>(Offset << 1); 2154 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2155 return MCDisassembler::Success; 2156 } 2157 2158 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset, 2159 uint64_t Address, 2160 const MCDisassembler *Decoder) { 2161 int32_t BranchOffset = SignExtend32<11>(Offset << 1); 2162 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2163 return MCDisassembler::Success; 2164 } 2165 2166 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset, 2167 uint64_t Address, 2168 const MCDisassembler *Decoder) { 2169 int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4; 2170 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2171 return MCDisassembler::Success; 2172 } 2173 2174 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset, 2175 uint64_t Address, 2176 const MCDisassembler *Decoder) { 2177 int32_t BranchOffset = SignExtend32<27>(Offset << 1); 2178 2179 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2180 return MCDisassembler::Success; 2181 } 2182 2183 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn, 2184 uint64_t Address, 2185 const MCDisassembler *Decoder) { 2186 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 2187 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2188 return MCDisassembler::Success; 2189 } 2190 2191 static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, unsigned Insn, 2192 uint64_t Address, 2193 const MCDisassembler *Decoder) { 2194 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 2195 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2196 return MCDisassembler::Success; 2197 } 2198 2199 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value, 2200 uint64_t Address, 2201 const MCDisassembler *Decoder) { 2202 if (Value == 0) 2203 Inst.addOperand(MCOperand::createImm(1)); 2204 else if (Value == 0x7) 2205 Inst.addOperand(MCOperand::createImm(-1)); 2206 else 2207 Inst.addOperand(MCOperand::createImm(Value << 2)); 2208 return MCDisassembler::Success; 2209 } 2210 2211 static DecodeStatus DecodeLi16Imm(MCInst &Inst, unsigned Value, 2212 uint64_t Address, 2213 const MCDisassembler *Decoder) { 2214 if (Value == 0x7F) 2215 Inst.addOperand(MCOperand::createImm(-1)); 2216 else 2217 Inst.addOperand(MCOperand::createImm(Value)); 2218 return MCDisassembler::Success; 2219 } 2220 2221 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value, 2222 uint64_t Address, 2223 const MCDisassembler *Decoder) { 2224 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value)); 2225 return MCDisassembler::Success; 2226 } 2227 2228 template <unsigned Bits, int Offset, int Scale> 2229 static DecodeStatus 2230 DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, 2231 const MCDisassembler *Decoder) { 2232 Value &= ((1 << Bits) - 1); 2233 Value *= Scale; 2234 Inst.addOperand(MCOperand::createImm(Value + Offset)); 2235 return MCDisassembler::Success; 2236 } 2237 2238 template <unsigned Bits, int Offset, int ScaleBy> 2239 static DecodeStatus 2240 DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, 2241 const MCDisassembler *Decoder) { 2242 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy; 2243 Inst.addOperand(MCOperand::createImm(Imm + Offset)); 2244 return MCDisassembler::Success; 2245 } 2246 2247 static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, 2248 const MCDisassembler *Decoder) { 2249 // First we need to grab the pos(lsb) from MCInst. 2250 // This function only handles the 32 bit variants of ins, as dins 2251 // variants are handled differently. 2252 int Pos = Inst.getOperand(2).getImm(); 2253 int Size = (int) Insn - Pos + 1; 2254 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 2255 return MCDisassembler::Success; 2256 } 2257 2258 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 2259 uint64_t Address, 2260 const MCDisassembler *Decoder) { 2261 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); 2262 return MCDisassembler::Success; 2263 } 2264 2265 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 2266 uint64_t Address, 2267 const MCDisassembler *Decoder) { 2268 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); 2269 return MCDisassembler::Success; 2270 } 2271 2272 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address, 2273 const MCDisassembler *Decoder) { 2274 int32_t DecodedValue; 2275 switch (Insn) { 2276 case 0: DecodedValue = 256; break; 2277 case 1: DecodedValue = 257; break; 2278 case 510: DecodedValue = -258; break; 2279 case 511: DecodedValue = -257; break; 2280 default: DecodedValue = SignExtend32<9>(Insn); break; 2281 } 2282 Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); 2283 return MCDisassembler::Success; 2284 } 2285 2286 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 2287 uint64_t Address, 2288 const MCDisassembler *Decoder) { 2289 // Insn must be >= 0, since it is unsigned that condition is always true. 2290 assert(Insn < 16); 2291 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 2292 255, 32768, 65535}; 2293 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); 2294 return MCDisassembler::Success; 2295 } 2296 2297 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 2298 uint64_t Address, 2299 const MCDisassembler *Decoder) { 2300 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 2301 Mips::S6, Mips::S7, Mips::FP}; 2302 unsigned RegNum; 2303 2304 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 2305 2306 // Empty register lists are not allowed. 2307 if (RegLst == 0) 2308 return MCDisassembler::Fail; 2309 2310 RegNum = RegLst & 0xf; 2311 2312 // RegLst values 10-15, and 26-31 are reserved. 2313 if (RegNum > 9) 2314 return MCDisassembler::Fail; 2315 2316 for (unsigned i = 0; i < RegNum; i++) 2317 Inst.addOperand(MCOperand::createReg(Regs[i])); 2318 2319 if (RegLst & 0x10) 2320 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2321 2322 return MCDisassembler::Success; 2323 } 2324 2325 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 2326 uint64_t Address, 2327 const MCDisassembler *Decoder) { 2328 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 2329 unsigned RegLst; 2330 switch(Inst.getOpcode()) { 2331 default: 2332 RegLst = fieldFromInstruction(Insn, 4, 2); 2333 break; 2334 case Mips::LWM16_MMR6: 2335 case Mips::SWM16_MMR6: 2336 RegLst = fieldFromInstruction(Insn, 8, 2); 2337 break; 2338 } 2339 unsigned RegNum = RegLst & 0x3; 2340 2341 for (unsigned i = 0; i <= RegNum; i++) 2342 Inst.addOperand(MCOperand::createReg(Regs[i])); 2343 2344 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2345 2346 return MCDisassembler::Success; 2347 } 2348 2349 static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn, 2350 uint64_t Address, 2351 const MCDisassembler *Decoder) { 2352 unsigned RegPair = fieldFromInstruction(Insn, 7, 3); 2353 if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) == 2354 MCDisassembler::Fail) 2355 return MCDisassembler::Fail; 2356 2357 unsigned RegRs; 2358 if (static_cast<const MipsDisassembler*>(Decoder)->hasMips32r6()) 2359 RegRs = fieldFromInstruction(Insn, 0, 2) | 2360 (fieldFromInstruction(Insn, 3, 1) << 2); 2361 else 2362 RegRs = fieldFromInstruction(Insn, 1, 3); 2363 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) == 2364 MCDisassembler::Fail) 2365 return MCDisassembler::Fail; 2366 2367 unsigned RegRt = fieldFromInstruction(Insn, 4, 3); 2368 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) == 2369 MCDisassembler::Fail) 2370 return MCDisassembler::Fail; 2371 2372 return MCDisassembler::Success; 2373 } 2374 2375 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, 2376 uint64_t Address, 2377 const MCDisassembler *Decoder) { 2378 switch (RegPair) { 2379 default: 2380 return MCDisassembler::Fail; 2381 case 0: 2382 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2383 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2384 break; 2385 case 1: 2386 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2387 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2388 break; 2389 case 2: 2390 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2391 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2392 break; 2393 case 3: 2394 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2395 Inst.addOperand(MCOperand::createReg(Mips::S5)); 2396 break; 2397 case 4: 2398 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2399 Inst.addOperand(MCOperand::createReg(Mips::S6)); 2400 break; 2401 case 5: 2402 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2403 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2404 break; 2405 case 6: 2406 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2407 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2408 break; 2409 case 7: 2410 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2411 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2412 break; 2413 } 2414 2415 return MCDisassembler::Success; 2416 } 2417 2418 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 2419 uint64_t Address, 2420 const MCDisassembler *Decoder) { 2421 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); 2422 return MCDisassembler::Success; 2423 } 2424 2425 template <typename InsnType> 2426 static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, 2427 uint64_t Address, 2428 const MCDisassembler *Decoder) { 2429 // We have: 2430 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii 2431 // Invalid if rt == 0 2432 // BGTZALC_MMR6 if rs == 0 && rt != 0 2433 // BLTZALC_MMR6 if rs != 0 && rs == rt 2434 // BLTUC_MMR6 if rs != 0 && rs != rt 2435 2436 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2437 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2438 InsnType Imm = 0; 2439 bool HasRs = false; 2440 bool HasRt = false; 2441 2442 if (Rt == 0) 2443 return MCDisassembler::Fail; 2444 else if (Rs == 0) { 2445 MI.setOpcode(Mips::BGTZALC_MMR6); 2446 HasRt = true; 2447 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2448 } 2449 else if (Rs == Rt) { 2450 MI.setOpcode(Mips::BLTZALC_MMR6); 2451 HasRs = true; 2452 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2453 } 2454 else { 2455 MI.setOpcode(Mips::BLTUC_MMR6); 2456 HasRs = true; 2457 HasRt = true; 2458 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2459 } 2460 2461 if (HasRs) 2462 MI.addOperand( 2463 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2464 2465 if (HasRt) 2466 MI.addOperand( 2467 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2468 2469 MI.addOperand(MCOperand::createImm(Imm)); 2470 2471 return MCDisassembler::Success; 2472 } 2473 2474 template <typename InsnType> 2475 static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, 2476 uint64_t Address, 2477 const MCDisassembler *Decoder) { 2478 // We have: 2479 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii 2480 // Invalid if rt == 0 2481 // BLEZALC_MMR6 if rs == 0 && rt != 0 2482 // BGEZALC_MMR6 if rs == rt && rt != 0 2483 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0 2484 2485 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2486 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2487 InsnType Imm = 0; 2488 bool HasRs = false; 2489 2490 if (Rt == 0) 2491 return MCDisassembler::Fail; 2492 else if (Rs == 0) { 2493 MI.setOpcode(Mips::BLEZALC_MMR6); 2494 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2495 } 2496 else if (Rs == Rt) { 2497 MI.setOpcode(Mips::BGEZALC_MMR6); 2498 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2499 } 2500 else { 2501 HasRs = true; 2502 MI.setOpcode(Mips::BGEUC_MMR6); 2503 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2504 } 2505 2506 if (HasRs) 2507 MI.addOperand( 2508 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2509 MI.addOperand( 2510 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2511 2512 MI.addOperand(MCOperand::createImm(Imm)); 2513 2514 return MCDisassembler::Success; 2515 } 2516