10b57cec5SDimitry Andric //===- MipsMCCodeEmitter.h - Convert Mips Code to Machine Code --*- C++ -*-===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // 90b57cec5SDimitry Andric // This file defines the MipsMCCodeEmitter class. 100b57cec5SDimitry Andric // 110b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 120b57cec5SDimitry Andric 130b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCCODEEMITTER_H 140b57cec5SDimitry Andric #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCCODEEMITTER_H 150b57cec5SDimitry Andric 160b57cec5SDimitry Andric #include "llvm/MC/MCCodeEmitter.h" 170b57cec5SDimitry Andric #include <cstdint> 180b57cec5SDimitry Andric 190b57cec5SDimitry Andric namespace llvm { 200b57cec5SDimitry Andric 210b57cec5SDimitry Andric class MCContext; 220b57cec5SDimitry Andric class MCExpr; 230b57cec5SDimitry Andric class MCFixup; 240b57cec5SDimitry Andric class MCInst; 250b57cec5SDimitry Andric class MCInstrInfo; 260b57cec5SDimitry Andric class MCOperand; 270b57cec5SDimitry Andric class MCSubtargetInfo; 280b57cec5SDimitry Andric class raw_ostream; 290b57cec5SDimitry Andric 300b57cec5SDimitry Andric class MipsMCCodeEmitter : public MCCodeEmitter { 310b57cec5SDimitry Andric const MCInstrInfo &MCII; 320b57cec5SDimitry Andric MCContext &Ctx; 330b57cec5SDimitry Andric bool IsLittleEndian; 340b57cec5SDimitry Andric 350b57cec5SDimitry Andric bool isMicroMips(const MCSubtargetInfo &STI) const; 360b57cec5SDimitry Andric bool isMips32r6(const MCSubtargetInfo &STI) const; 370b57cec5SDimitry Andric 380b57cec5SDimitry Andric public: MipsMCCodeEmitter(const MCInstrInfo & mcii,MCContext & Ctx_,bool IsLittle)390b57cec5SDimitry Andric MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_, bool IsLittle) 400b57cec5SDimitry Andric : MCII(mcii), Ctx(Ctx_), IsLittleEndian(IsLittle) {} 410b57cec5SDimitry Andric MipsMCCodeEmitter(const MipsMCCodeEmitter &) = delete; 420b57cec5SDimitry Andric MipsMCCodeEmitter &operator=(const MipsMCCodeEmitter &) = delete; 430b57cec5SDimitry Andric ~MipsMCCodeEmitter() override = default; 440b57cec5SDimitry Andric 450b57cec5SDimitry Andric void EmitByte(unsigned char C, raw_ostream &OS) const; 460b57cec5SDimitry Andric 475f757f3fSDimitry Andric void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB, 480b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 490b57cec5SDimitry Andric const MCSubtargetInfo &STI) const override; 500b57cec5SDimitry Andric 510b57cec5SDimitry Andric // getBinaryCodeForInstr - TableGen'erated function for getting the 520b57cec5SDimitry Andric // binary encoding for an instruction. 530b57cec5SDimitry Andric uint64_t getBinaryCodeForInstr(const MCInst &MI, 540b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 550b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 560b57cec5SDimitry Andric 570b57cec5SDimitry Andric // getJumpTargetOpValue - Return binary encoding of the jump 580b57cec5SDimitry Andric // target operand. If the machine operand requires relocation, 590b57cec5SDimitry Andric // record the relocation and return zero. 600b57cec5SDimitry Andric unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo, 610b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 620b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 630b57cec5SDimitry Andric 640b57cec5SDimitry Andric // getBranchJumpOpValueMM - Return binary encoding of the microMIPS jump 650b57cec5SDimitry Andric // target operand. If the machine operand requires relocation, 660b57cec5SDimitry Andric // record the relocation and return zero. 670b57cec5SDimitry Andric unsigned getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo, 680b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 690b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 700b57cec5SDimitry Andric 710b57cec5SDimitry Andric // getUImm5Lsl2Encoding - Return binary encoding of the microMIPS jump 720b57cec5SDimitry Andric // target operand. 730b57cec5SDimitry Andric unsigned getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo, 740b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 750b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 760b57cec5SDimitry Andric 770b57cec5SDimitry Andric unsigned getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo, 780b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 790b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 800b57cec5SDimitry Andric 810b57cec5SDimitry Andric unsigned getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo, 820b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 830b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 840b57cec5SDimitry Andric 850b57cec5SDimitry Andric // getSImm9AddiuspValue - Return binary encoding of the microMIPS addiusp 860b57cec5SDimitry Andric // instruction immediate operand. 870b57cec5SDimitry Andric unsigned getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo, 880b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 890b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 900b57cec5SDimitry Andric 910b57cec5SDimitry Andric // getBranchTargetOpValue - Return binary encoding of the branch 920b57cec5SDimitry Andric // target operand. If the machine operand requires relocation, 930b57cec5SDimitry Andric // record the relocation and return zero. 940b57cec5SDimitry Andric unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, 950b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 960b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 970b57cec5SDimitry Andric 980b57cec5SDimitry Andric // getBranchTargetOpValue1SImm16 - Return binary encoding of the branch 990b57cec5SDimitry Andric // target operand. If the machine operand requires relocation, 1000b57cec5SDimitry Andric // record the relocation and return zero. 1010b57cec5SDimitry Andric unsigned getBranchTargetOpValue1SImm16(const MCInst &MI, unsigned OpNo, 1020b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 1030b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 1040b57cec5SDimitry Andric 1050b57cec5SDimitry Andric // getBranchTargetOpValueMMR6 - Return binary encoding of the branch 1060b57cec5SDimitry Andric // target operand. If the machine operand requires relocation, 1070b57cec5SDimitry Andric // record the relocation and return zero. 1080b57cec5SDimitry Andric unsigned getBranchTargetOpValueMMR6(const MCInst &MI, unsigned OpNo, 1090b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 1100b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 1110b57cec5SDimitry Andric 1120b57cec5SDimitry Andric // getBranchTargetOpValueLsl2MMR6 - Return binary encoding of the branch 1130b57cec5SDimitry Andric // target operand. If the machine operand requires relocation, 1140b57cec5SDimitry Andric // record the relocation and return zero. 1150b57cec5SDimitry Andric unsigned getBranchTargetOpValueLsl2MMR6(const MCInst &MI, unsigned OpNo, 1160b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 1170b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 1180b57cec5SDimitry Andric 1190b57cec5SDimitry Andric // getBranchTarget7OpValue - Return binary encoding of the microMIPS branch 1200b57cec5SDimitry Andric // target operand. If the machine operand requires relocation, 1210b57cec5SDimitry Andric // record the relocation and return zero. 1220b57cec5SDimitry Andric unsigned getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo, 1230b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 1240b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 1250b57cec5SDimitry Andric 1260b57cec5SDimitry Andric // getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS 1270b57cec5SDimitry Andric // 10-bit branch target operand. If the machine operand requires relocation, 1280b57cec5SDimitry Andric // record the relocation and return zero. 1290b57cec5SDimitry Andric unsigned getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo, 1300b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 1310b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 1320b57cec5SDimitry Andric 1330b57cec5SDimitry Andric // getBranchTargetOpValue - Return binary encoding of the microMIPS branch 1340b57cec5SDimitry Andric // target operand. If the machine operand requires relocation, 1350b57cec5SDimitry Andric // record the relocation and return zero. 1360b57cec5SDimitry Andric unsigned getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo, 1370b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 1380b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 1390b57cec5SDimitry Andric 1400b57cec5SDimitry Andric // getBranchTarget21OpValue - Return binary encoding of the branch 1410b57cec5SDimitry Andric // offset operand. If the machine operand requires relocation, 1420b57cec5SDimitry Andric // record the relocation and return zero. 1430b57cec5SDimitry Andric unsigned getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo, 1440b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 1450b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 1460b57cec5SDimitry Andric 1470b57cec5SDimitry Andric // getBranchTarget21OpValueMM - Return binary encoding of the branch 1480b57cec5SDimitry Andric // offset operand for microMIPS. If the machine operand requires 1490b57cec5SDimitry Andric // relocation,record the relocation and return zero. 1500b57cec5SDimitry Andric unsigned getBranchTarget21OpValueMM(const MCInst &MI, unsigned OpNo, 1510b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 1520b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 1530b57cec5SDimitry Andric 1540b57cec5SDimitry Andric // getBranchTarget26OpValue - Return binary encoding of the branch 1550b57cec5SDimitry Andric // offset operand. If the machine operand requires relocation, 1560b57cec5SDimitry Andric // record the relocation and return zero. 1570b57cec5SDimitry Andric unsigned getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo, 1580b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 1590b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 1600b57cec5SDimitry Andric 1610b57cec5SDimitry Andric // getBranchTarget26OpValueMM - Return binary encoding of the branch 1620b57cec5SDimitry Andric // offset operand. If the machine operand requires relocation, 1630b57cec5SDimitry Andric // record the relocation and return zero. 1640b57cec5SDimitry Andric unsigned getBranchTarget26OpValueMM(const MCInst &MI, unsigned OpNo, 1650b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 1660b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 1670b57cec5SDimitry Andric 1680b57cec5SDimitry Andric // getJumpOffset16OpValue - Return binary encoding of the jump 1690b57cec5SDimitry Andric // offset operand. If the machine operand requires relocation, 1700b57cec5SDimitry Andric // record the relocation and return zero. 1710b57cec5SDimitry Andric unsigned getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo, 1720b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 1730b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 1740b57cec5SDimitry Andric 1750b57cec5SDimitry Andric // getMachineOpValue - Return binary encoding of operand. If the machin 1760b57cec5SDimitry Andric // operand requires relocation, record the relocation and return zero. 1770b57cec5SDimitry Andric unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, 1780b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 1790b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 1800b57cec5SDimitry Andric 1810b57cec5SDimitry Andric unsigned getMSAMemEncoding(const MCInst &MI, unsigned OpNo, 1820b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 1830b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 1840b57cec5SDimitry Andric 1850b57cec5SDimitry Andric template <unsigned ShiftAmount = 0> 1860b57cec5SDimitry Andric unsigned getMemEncoding(const MCInst &MI, unsigned OpNo, 1870b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 1880b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 1890b57cec5SDimitry Andric unsigned getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo, 1900b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 1910b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 1920b57cec5SDimitry Andric unsigned getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo, 1930b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 1940b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 1950b57cec5SDimitry Andric unsigned getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo, 1960b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 1970b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 1980b57cec5SDimitry Andric unsigned getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo, 1990b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 2000b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 2010b57cec5SDimitry Andric unsigned getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo, 2020b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 2030b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 2040b57cec5SDimitry Andric unsigned getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo, 2050b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 2060b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 2070b57cec5SDimitry Andric unsigned getMemEncodingMMImm11(const MCInst &MI, unsigned OpNo, 2080b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 2090b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 2100b57cec5SDimitry Andric unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo, 2110b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 2120b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 2130b57cec5SDimitry Andric unsigned getMemEncodingMMImm16(const MCInst &MI, unsigned OpNo, 2140b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 2150b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 2160b57cec5SDimitry Andric unsigned getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo, 2170b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 2180b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 2190b57cec5SDimitry Andric unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo, 2200b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 2210b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 2220b57cec5SDimitry Andric 2230b57cec5SDimitry Andric /// Subtract Offset then encode as a N-bit unsigned integer. 2240b57cec5SDimitry Andric template <unsigned Bits, int Offset> 2250b57cec5SDimitry Andric unsigned getUImmWithOffsetEncoding(const MCInst &MI, unsigned OpNo, 2260b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 2270b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 2280b57cec5SDimitry Andric 2290b57cec5SDimitry Andric unsigned getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo, 2300b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 2310b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 2320b57cec5SDimitry Andric 2330b57cec5SDimitry Andric unsigned getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo, 2340b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 2350b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 2360b57cec5SDimitry Andric 2370b57cec5SDimitry Andric unsigned getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo, 2380b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 2390b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 2400b57cec5SDimitry Andric unsigned getUImm4AndValue(const MCInst &MI, unsigned OpNo, 2410b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 2420b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 2430b57cec5SDimitry Andric 2440b57cec5SDimitry Andric unsigned getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo, 2450b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 2460b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 2470b57cec5SDimitry Andric unsigned getMovePRegSingleOpValue(const MCInst &MI, unsigned OpNo, 2480b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 2490b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 2500b57cec5SDimitry Andric 2510b57cec5SDimitry Andric unsigned getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo, 2520b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 2530b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 2540b57cec5SDimitry Andric 2550b57cec5SDimitry Andric unsigned getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups, 2560b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 2570b57cec5SDimitry Andric 2580b57cec5SDimitry Andric unsigned getRegisterListOpValue(const MCInst &MI, unsigned OpNo, 2590b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 2600b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 2610b57cec5SDimitry Andric 2620b57cec5SDimitry Andric unsigned getRegisterListOpValue16(const MCInst &MI, unsigned OpNo, 2630b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 2640b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 2650b57cec5SDimitry Andric 2660b57cec5SDimitry Andric private: 2670b57cec5SDimitry Andric void LowerCompactBranch(MCInst& Inst) const; 2680b57cec5SDimitry Andric }; 2690b57cec5SDimitry Andric 2700b57cec5SDimitry Andric } // end namespace llvm 2710b57cec5SDimitry Andric 2720b57cec5SDimitry Andric #endif // LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCCODEEMITTER_H 273