1//===-- MicroMipsInstrFormats.td - microMIPS Inst Formats -*- tablegen -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This files describes the formats of the microMIPS instruction set.
10//
11//===----------------------------------------------------------------------===//
12
13//===----------------------------------------------------------------------===//
14// MicroMIPS Base Classes
15//===----------------------------------------------------------------------===//
16
17//
18// Base class for MicroMips instructions.
19// This class does not depend on the instruction size.
20//
21class MicroMipsInstBase<dag outs, dag ins, string asmstr, list<dag> pattern,
22                        InstrItinClass itin, Format f> : Instruction,
23                        PredicateControl {
24  let Namespace = "Mips";
25  let DecoderNamespace = "MicroMips";
26
27  let OutOperandList = outs;
28  let InOperandList  = ins;
29
30  let AsmString   = asmstr;
31  let Pattern     = pattern;
32  let Itinerary   = itin;
33
34  let EncodingPredicates = [InMicroMips];
35
36  Format Form = f;
37}
38
39//
40// Base class for MicroMIPS 16-bit instructions.
41//
42class MicroMipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
43               InstrItinClass itin, Format f> :
44  MicroMipsInstBase<outs, ins, asmstr, pattern, itin, f>
45{
46  let Size = 2;
47  field bits<16> Inst;
48  field bits<16> SoftFail = 0;
49  bits<6> Opcode = 0x0;
50}
51
52//===----------------------------------------------------------------------===//
53// MicroMIPS 16-bit Instruction Formats
54//===----------------------------------------------------------------------===//
55
56class ARITH_FM_MM16<bit funct> {
57  bits<3> rd;
58  bits<3> rt;
59  bits<3> rs;
60
61  bits<16> Inst;
62
63  let Inst{15-10} = 0x01;
64  let Inst{9-7}   = rd;
65  let Inst{6-4}   = rt;
66  let Inst{3-1}   = rs;
67  let Inst{0}     = funct;
68}
69
70class ANDI_FM_MM16<bits<6> funct> {
71  bits<3> rd;
72  bits<3> rs;
73  bits<4> imm;
74
75  bits<16> Inst;
76
77  let Inst{15-10} = funct;
78  let Inst{9-7}   = rd;
79  let Inst{6-4}   = rs;
80  let Inst{3-0}   = imm;
81}
82
83class LOGIC_FM_MM16<bits<4> funct> {
84  bits<3> rt;
85  bits<3> rs;
86
87  bits<16> Inst;
88
89  let Inst{15-10} = 0x11;
90  let Inst{9-6}   = funct;
91  let Inst{5-3}   = rt;
92  let Inst{2-0}   = rs;
93}
94
95class SHIFT_FM_MM16<bits<1> funct> {
96  bits<3> rd;
97  bits<3> rt;
98  bits<3> shamt;
99
100  bits<16> Inst;
101
102  let Inst{15-10} = 0x09;
103  let Inst{9-7}   = rd;
104  let Inst{6-4}   = rt;
105  let Inst{3-1}   = shamt;
106  let Inst{0}     = funct;
107}
108
109class ADDIUR2_FM_MM16 {
110  bits<3> rd;
111  bits<3> rs;
112  bits<3> imm;
113
114  bits<16> Inst;
115
116  let Inst{15-10} = 0x1b;
117  let Inst{9-7}   = rd;
118  let Inst{6-4}   = rs;
119  let Inst{3-1}   = imm;
120  let Inst{0}     = 0;
121}
122
123class LOAD_STORE_FM_MM16<bits<6> op> {
124  bits<3> rt;
125  bits<7> addr;
126
127  bits<16> Inst;
128
129  let Inst{15-10} = op;
130  let Inst{9-7}   = rt;
131  let Inst{6-4}   = addr{6-4};
132  let Inst{3-0}   = addr{3-0};
133}
134
135class LOAD_STORE_SP_FM_MM16<bits<6> op> {
136  bits<5> rt;
137  bits<5> offset;
138
139  bits<16> Inst;
140
141  let Inst{15-10} = op;
142  let Inst{9-5}   = rt;
143  let Inst{4-0}   = offset;
144}
145
146class LOAD_GP_FM_MM16<bits<6> op> {
147  bits<3> rt;
148  bits<7> offset;
149
150  bits<16> Inst;
151
152  let Inst{15-10} = op;
153  let Inst{9-7} = rt;
154  let Inst{6-0} = offset;
155}
156
157class ADDIUS5_FM_MM16 {
158  bits<5> rd;
159  bits<4> imm;
160
161  bits<16> Inst;
162
163  let Inst{15-10} = 0x13;
164  let Inst{9-5}   = rd;
165  let Inst{4-1}   = imm;
166  let Inst{0}     = 0;
167}
168
169class ADDIUSP_FM_MM16 {
170  bits<9> imm;
171
172  bits<16> Inst;
173
174  let Inst{15-10} = 0x13;
175  let Inst{9-1}   = imm;
176  let Inst{0}     = 1;
177}
178
179class MOVE_FM_MM16<bits<6> funct> {
180  bits<5> rs;
181  bits<5> rd;
182
183  bits<16> Inst;
184
185  let Inst{15-10} = funct;
186  let Inst{9-5}   = rd;
187  let Inst{4-0}   = rs;
188}
189
190class LI_FM_MM16 {
191  bits<3> rd;
192  bits<7> imm;
193
194  bits<16> Inst;
195
196  let Inst{15-10} = 0x3b;
197  let Inst{9-7}   = rd;
198  let Inst{6-0}   = imm;
199}
200
201class JALR_FM_MM16<bits<5> op> {
202  bits<5> rs;
203
204  bits<16> Inst;
205
206  let Inst{15-10} = 0x11;
207  let Inst{9-5}   = op;
208  let Inst{4-0}   = rs;
209}
210
211class MFHILO_FM_MM16<bits<5> funct> {
212  bits<5> rd;
213
214  bits<16> Inst;
215
216  let Inst{15-10} = 0x11;
217  let Inst{9-5}   = funct;
218  let Inst{4-0}   = rd;
219}
220
221class JRADDIUSP_FM_MM16<bits<5> op> {
222  bits<5> rs;
223  bits<5> imm;
224
225  bits<16> Inst;
226
227  let Inst{15-10} = 0x11;
228  let Inst{9-5}   = op;
229  let Inst{4-0}   = imm;
230}
231
232class ADDIUR1SP_FM_MM16 {
233  bits<3> rd;
234  bits<6> imm;
235
236  bits<16> Inst;
237
238  let Inst{15-10} = 0x1b;
239  let Inst{9-7}   = rd;
240  let Inst{6-1}   = imm;
241  let Inst{0}     = 1;
242}
243
244class BRKSDBBP16_FM_MM<bits<6> op> {
245  bits<4> code_;
246  bits<16> Inst;
247
248  let Inst{15-10} = 0x11;
249  let Inst{9-4}   = op;
250  let Inst{3-0}   = code_;
251}
252
253class BEQNEZ_FM_MM16<bits<6> op> {
254  bits<3> rs;
255  bits<7> offset;
256
257  bits<16> Inst;
258
259  let Inst{15-10} = op;
260  let Inst{9-7}   = rs;
261  let Inst{6-0}   = offset;
262}
263
264class B16_FM {
265  bits<10> offset;
266
267  bits<16> Inst;
268
269  let Inst{15-10} = 0x33;
270  let Inst{9-0}   = offset;
271}
272
273class MOVEP_FM_MM16 {
274  bits<3> rt;
275  bits<3> rs;
276
277  bits<16> Inst;
278
279  let Inst{15-10} = 0x21;
280  // bits 7-9 are populated by MipsMCCodeEmitter::encodeInstruction, with a
281  // special encoding of both rd1 and rd2.
282  let Inst{9-7}   = ?;
283  let Inst{6-4}   = rt;
284  let Inst{3-1}   = rs;
285  let Inst{0}     = 0;
286}
287
288//===----------------------------------------------------------------------===//
289// MicroMIPS 32-bit Instruction Formats
290//===----------------------------------------------------------------------===//
291
292class MMArch {
293  string Arch = "micromips";
294}
295
296class ADD_FM_MM<bits<6> op, bits<10> funct> : MMArch {
297  bits<5> rt;
298  bits<5> rs;
299  bits<5> rd;
300
301  bits<32> Inst;
302
303  let Inst{31-26} = op;
304  let Inst{25-21} = rt;
305  let Inst{20-16} = rs;
306  let Inst{15-11} = rd;
307  let Inst{10}    = 0;
308  let Inst{9-0}   = funct;
309}
310
311class ADDI_FM_MM<bits<6> op> : MMArch {
312  bits<5>  rs;
313  bits<5>  rt;
314  bits<16> imm16;
315
316  bits<32> Inst;
317
318  let Inst{31-26} = op;
319  let Inst{25-21} = rt;
320  let Inst{20-16} = rs;
321  let Inst{15-0}  = imm16;
322}
323
324class SLTI_FM_MM<bits<6> op> : MMArch {
325  bits<5> rt;
326  bits<5> rs;
327  bits<16> imm16;
328
329  bits<32> Inst;
330
331  let Inst{31-26} = op;
332  let Inst{25-21} = rt;
333  let Inst{20-16} = rs;
334  let Inst{15-0}  = imm16;
335}
336
337class LUI_FM_MM : MMArch {
338  bits<5> rt;
339  bits<16> imm16;
340
341  bits<32> Inst;
342
343  let Inst{31-26} = 0x10;
344  let Inst{25-21} = 0xd;
345  let Inst{20-16} = rt;
346  let Inst{15-0}  = imm16;
347}
348
349class MULT_FM_MM<bits<10> funct> : MMArch {
350  bits<5>  rs;
351  bits<5>  rt;
352
353  bits<32> Inst;
354
355  let Inst{31-26} = 0x00;
356  let Inst{25-21} = rt;
357  let Inst{20-16} = rs;
358  let Inst{15-6}  = funct;
359  let Inst{5-0}   = 0x3c;
360}
361
362class SRA_FM_MM<bits<10> funct, bit rotate> : MMArch {
363  bits<5> rd;
364  bits<5> rt;
365  bits<5> shamt;
366
367  bits<32> Inst;
368
369  let Inst{31-26} = 0;
370  let Inst{25-21} = rd;
371  let Inst{20-16} = rt;
372  let Inst{15-11} = shamt;
373  let Inst{10}    = rotate;
374  let Inst{9-0}   = funct;
375}
376
377class SRLV_FM_MM<bits<10> funct, bit rotate> : MMArch {
378  bits<5> rd;
379  bits<5> rt;
380  bits<5> rs;
381
382  bits<32> Inst;
383
384  let Inst{31-26} = 0;
385  let Inst{25-21} = rt;
386  let Inst{20-16} = rs;
387  let Inst{15-11} = rd;
388  let Inst{10}    = rotate;
389  let Inst{9-0}   = funct;
390}
391
392class LW_FM_MM<bits<6> op> : MMArch {
393  bits<5> rt;
394  bits<21> addr;
395  bits<5> base = addr{20-16};
396  bits<16> offset = addr{15-0};
397
398  bits<32> Inst;
399
400  let Inst{31-26} = op;
401  let Inst{25-21} = rt;
402  let Inst{20-16} = base;
403  let Inst{15-0}  = offset;
404}
405
406class POOL32C_LHUE_FM_MM<bits<6> op, bits<4> fmt, bits<3> funct> : MMArch {
407  bits<5> rt;
408  bits<21> addr;
409  bits<5> base = addr{20-16};
410  bits<9> offset = addr{8-0};
411
412  bits<32> Inst;
413
414  let Inst{31-26} = op;
415  let Inst{25-21} = rt;
416  let Inst{20-16} = base;
417  let Inst{15-12} = fmt;
418  let Inst{11-9} = funct;
419  let Inst{8-0}  = offset;
420}
421
422class LWL_FM_MM<bits<4> funct> : MMArch {
423  bits<5> rt;
424  bits<21> addr;
425
426  bits<32> Inst;
427
428  let Inst{31-26} = 0x18;
429  let Inst{25-21} = rt;
430  let Inst{20-16} = addr{20-16};
431  let Inst{15-12} = funct;
432  let Inst{11-0}  = addr{11-0};
433}
434
435class POOL32C_STEVA_LDEVA_FM_MM<bits<4> type, bits<3> funct> : MMArch {
436  bits<5> rt;
437  bits<21> addr;
438  bits<5> base = addr{20-16};
439  bits<9> offset = addr{8-0};
440
441  bits<32> Inst;
442
443  let Inst{31-26} = 0x18;
444  let Inst{25-21} = rt;
445  let Inst{20-16} = base;
446  let Inst{15-12} = type;
447  let Inst{11-9} = funct;
448  let Inst{8-0}  = offset;
449}
450
451class CMov_F_I_FM_MM<bits<7> func> : MMArch {
452  bits<5> rd;
453  bits<5> rs;
454  bits<3> fcc;
455
456  bits<32> Inst;
457
458  let Inst{31-26} = 0x15;
459  let Inst{25-21} = rd;
460  let Inst{20-16} = rs;
461  let Inst{15-13} = fcc;
462  let Inst{12-6}  = func;
463  let Inst{5-0}   = 0x3b;
464}
465
466class MTLO_FM_MM<bits<10> funct> : MMArch {
467  bits<5> rs;
468
469  bits<32> Inst;
470
471  let Inst{31-26} = 0x00;
472  let Inst{25-21} = 0x00;
473  let Inst{20-16} = rs;
474  let Inst{15-6}  = funct;
475  let Inst{5-0}   = 0x3c;
476}
477
478class MFLO_FM_MM<bits<10> funct> : MMArch {
479  bits<5> rd;
480
481  bits<32> Inst;
482
483  let Inst{31-26} = 0x00;
484  let Inst{25-21} = 0x00;
485  let Inst{20-16} = rd;
486  let Inst{15-6}  = funct;
487  let Inst{5-0}   = 0x3c;
488}
489
490class CLO_FM_MM<bits<10> funct> : MMArch {
491  bits<5> rd;
492  bits<5> rs;
493
494  bits<32> Inst;
495
496  let Inst{31-26} = 0x00;
497  let Inst{25-21} = rd;
498  let Inst{20-16} = rs;
499  let Inst{15-6}  = funct;
500  let Inst{5-0}   = 0x3c;
501}
502
503class SEB_FM_MM<bits<10> funct> : MMArch {
504  bits<5> rd;
505  bits<5> rt;
506
507  bits<32> Inst;
508
509  let Inst{31-26} = 0x00;
510  let Inst{25-21} = rd;
511  let Inst{20-16} = rt;
512  let Inst{15-6}  = funct;
513  let Inst{5-0}   = 0x3c;
514}
515
516class EXT_FM_MM<bits<6> funct> : MMArch {
517  bits<5> rt;
518  bits<5> rs;
519  bits<5> pos;
520  bits<5> size;
521
522  bits<32> Inst;
523
524  let Inst{31-26} = 0x00;
525  let Inst{25-21} = rt;
526  let Inst{20-16} = rs;
527  let Inst{15-11} = size;
528  let Inst{10-6}  = pos;
529  let Inst{5-0}   = funct;
530}
531
532class J_FM_MM<bits<6> op> : MMArch {
533  bits<26> target;
534
535  bits<32> Inst;
536
537  let Inst{31-26} = op;
538  let Inst{25-0}  = target;
539}
540
541class JR_FM_MM<bits<8> funct> : MMArch {
542  bits<5> rs;
543
544  bits<32> Inst;
545
546  let Inst{31-21} = 0x00;
547  let Inst{20-16} = rs;
548  let Inst{15-14} = 0x0;
549  let Inst{13-6}  = funct;
550  let Inst{5-0}   = 0x3c;
551}
552
553class JALR_FM_MM<bits<10> funct> {
554  bits<5> rs;
555  bits<5> rd;
556
557  bits<32> Inst;
558
559  let Inst{31-26} = 0x00;
560  let Inst{25-21} = rd;
561  let Inst{20-16} = rs;
562  let Inst{15-6}  = funct;
563  let Inst{5-0}   = 0x3c;
564}
565
566class BEQ_FM_MM<bits<6> op> : MMArch {
567  bits<5>  rs;
568  bits<5>  rt;
569  bits<16> offset;
570
571  bits<32> Inst;
572
573  let Inst{31-26} = op;
574  let Inst{25-21} = rt;
575  let Inst{20-16} = rs;
576  let Inst{15-0}  = offset;
577}
578
579class BGEZ_FM_MM<bits<5> funct> : MMArch {
580  bits<5>  rs;
581  bits<16> offset;
582
583  bits<32> Inst;
584
585  let Inst{31-26} = 0x10;
586  let Inst{25-21} = funct;
587  let Inst{20-16} = rs;
588  let Inst{15-0}  = offset;
589}
590
591class BGEZAL_FM_MM<bits<5> funct> : MMArch {
592  bits<5>  rs;
593  bits<16> offset;
594
595  bits<32> Inst;
596
597  let Inst{31-26} = 0x10;
598  let Inst{25-21} = funct;
599  let Inst{20-16} = rs;
600  let Inst{15-0}  = offset;
601}
602
603class SYNC_FM_MM : MMArch {
604  bits<5> stype;
605
606  bits<32> Inst;
607
608  let Inst{31-26} = 0x00;
609  let Inst{25-21} = 0x0;
610  let Inst{20-16} = stype;
611  let Inst{15-6}  = 0x1ad;
612  let Inst{5-0}   = 0x3c;
613}
614
615class SYNCI_FM_MM : MMArch {
616  bits<21> addr;
617  bits<5> rs = addr{20-16};
618  bits<16> offset = addr{15-0};
619  bits<32> Inst;
620
621  let Inst{31-26} = 0b010000;
622  let Inst{25-21} = 0b10000;
623  let Inst{20-16} = rs;
624  let Inst{15-0}  = offset;
625}
626
627class BRK_FM_MM : MMArch {
628  bits<10> code_1;
629  bits<10> code_2;
630  bits<32> Inst;
631  let Inst{31-26} = 0x0;
632  let Inst{25-16} = code_1;
633  let Inst{15-6}  = code_2;
634  let Inst{5-0}   = 0x07;
635}
636
637class SYS_FM_MM : MMArch {
638  bits<10> code_;
639  bits<32> Inst;
640  let Inst{31-26} = 0x0;
641  let Inst{25-16} = code_;
642  let Inst{15-6}  = 0x22d;
643  let Inst{5-0}   = 0x3c;
644}
645
646class WAIT_FM_MM : MMArch {
647  bits<10> code_;
648  bits<32> Inst;
649
650  let Inst{31-26} = 0x00;
651  let Inst{25-16} = code_;
652  let Inst{15-6}  = 0x24d;
653  let Inst{5-0}   = 0x3c;
654}
655
656class ER_FM_MM<bits<10> funct> : MMArch {
657  bits<32> Inst;
658
659  let Inst{31-26} = 0x00;
660  let Inst{25-16} = 0x00;
661  let Inst{15-6}  = funct;
662  let Inst{5-0}   = 0x3c;
663}
664
665class EI_FM_MM<bits<10> funct> : MMArch {
666  bits<32> Inst;
667  bits<5> rt;
668
669  let Inst{31-26} = 0x00;
670  let Inst{25-21} = 0x00;
671  let Inst{20-16} = rt;
672  let Inst{15-6}  = funct;
673  let Inst{5-0}   = 0x3c;
674}
675
676class TEQ_FM_MM<bits<6> funct> : MMArch {
677  bits<5> rs;
678  bits<5> rt;
679  bits<4> code_;
680
681  bits<32> Inst;
682
683  let Inst{31-26} = 0x00;
684  let Inst{25-21} = rt;
685  let Inst{20-16} = rs;
686  let Inst{15-12} = code_;
687  let Inst{11-6}  = funct;
688  let Inst{5-0}   = 0x3c;
689}
690
691class TEQI_FM_MM<bits<5> funct> : MMArch {
692  bits<5> rs;
693  bits<16> imm16;
694
695  bits<32> Inst;
696
697  let Inst{31-26} = 0x10;
698  let Inst{25-21} = funct;
699  let Inst{20-16} = rs;
700  let Inst{15-0}  = imm16;
701}
702
703class LL_FM_MM<bits<4> funct> : MMArch {
704  bits<5> rt;
705  bits<21> addr;
706
707  bits<32> Inst;
708
709  let Inst{31-26} = 0x18;
710  let Inst{25-21} = rt;
711  let Inst{20-16} = addr{20-16};
712  let Inst{15-12} = funct;
713  let Inst{11-0}  = addr{11-0};
714}
715
716class LLE_FM_MM<bits<4> funct> : MMArch {
717  bits<5> rt;
718  bits<21> addr;
719  bits<5> base = addr{20-16};
720  bits<9> offset = addr{8-0};
721
722  bits<32> Inst;
723
724  let Inst{31-26} = 0x18;
725  let Inst{25-21} = rt;
726  let Inst{20-16} = base;
727  let Inst{15-12} = funct;
728  let Inst{11-9} = 0x6;
729  let Inst{8-0} = offset;
730}
731
732class ADDS_FM_MM<bits<2> fmt, bits<8> funct> : MMArch {
733  bits<5> ft;
734  bits<5> fs;
735  bits<5> fd;
736
737  bits<32> Inst;
738
739  let Inst{31-26} = 0x15;
740  let Inst{25-21} = ft;
741  let Inst{20-16} = fs;
742  let Inst{15-11} = fd;
743  let Inst{10}    = 0;
744  let Inst{9-8}   = fmt;
745  let Inst{7-0}   = funct;
746
747}
748
749class LWXC1_FM_MM<bits<9> funct> : MMArch {
750  bits<5> fd;
751  bits<5> base;
752  bits<5> index;
753
754  bits<32> Inst;
755
756  let Inst{31-26} = 0x15;
757  let Inst{25-21} = index;
758  let Inst{20-16} = base;
759  let Inst{15-11} = fd;
760  let Inst{10-9}  = 0x0;
761  let Inst{8-0}   = funct;
762}
763
764class SWXC1_FM_MM<bits<9> funct> : MMArch {
765  bits<5> fs;
766  bits<5> base;
767  bits<5> index;
768
769  bits<32> Inst;
770
771  let Inst{31-26} = 0x15;
772  let Inst{25-21} = index;
773  let Inst{20-16} = base;
774  let Inst{15-11} = fs;
775  let Inst{10-9}  = 0x0;
776  let Inst{8-0}   = funct;
777}
778
779class CEQS_FM_MM<bits<2> fmt> : MMArch {
780  bits<5> fs;
781  bits<5> ft;
782  bits<3> fcc;
783  bits<4> cond;
784
785  bits<32> Inst;
786
787  let Inst{31-26} = 0x15;
788  let Inst{25-21} = ft;
789  let Inst{20-16} = fs;
790  let Inst{15-13} = fcc;
791  let Inst{12}    = 0;
792  let Inst{11-10} = fmt;
793  let Inst{9-6}   = cond;
794  let Inst{5-0}   = 0x3c;
795}
796
797class C_COND_FM_MM<bits <2> fmt, bits<4> c> : CEQS_FM_MM<fmt> {
798  let cond = c;
799}
800
801class BC1F_FM_MM<bits<5> tf> : MMArch {
802  bits<3> fcc;
803  bits<16> offset;
804
805  bits<32> Inst;
806
807  let Inst{31-26} = 0x10;
808  let Inst{25-21} = tf;
809  let Inst{20-18} = fcc; // cc
810  let Inst{17-16} = 0x0;
811  let Inst{15-0}  = offset;
812}
813
814class ROUND_W_FM_MM<bits<1> fmt, bits<8> funct> : MMArch {
815  bits<5> fd;
816  bits<5> fs;
817
818  bits<32> Inst;
819
820  let Inst{31-26} = 0x15;
821  let Inst{25-21} = fd;
822  let Inst{20-16} = fs;
823  let Inst{15}    = 0;
824  let Inst{14}    = fmt;
825  let Inst{13-6}  = funct;
826  let Inst{5-0}   = 0x3b;
827}
828
829class ABS_FM_MM<bits<2> fmt, bits<7> funct> : MMArch {
830  bits<5> fd;
831  bits<5> fs;
832
833  bits<32> Inst;
834
835  let Inst{31-26} = 0x15;
836  let Inst{25-21} = fd;
837  let Inst{20-16} = fs;
838  let Inst{15}    = 0;
839  let Inst{14-13} = fmt;
840  let Inst{12-6}  = funct;
841  let Inst{5-0}   = 0x3b;
842}
843
844class CMov_F_F_FM_MM<bits<9> func, bits<2> fmt> : MMArch {
845  bits<5> fd;
846  bits<5> fs;
847  bits<3> fcc;
848  bits<32> Inst;
849
850  let Inst{31-26} = 0x15;
851  let Inst{25-21} = fd;
852  let Inst{20-16} = fs;
853  let Inst{15-13} = fcc; //cc
854  let Inst{12-11} = 0x0;
855  let Inst{10-9}  = fmt;
856  let Inst{8-0}   = func;
857}
858
859class CMov_I_F_FM_MM<bits<8> funct, bits<2> fmt> : MMArch {
860  bits<5> fd;
861  bits<5> fs;
862  bits<5> rt;
863
864  bits<32> Inst;
865
866  let Inst{31-26} = 0x15;
867  let Inst{25-21} = rt;
868  let Inst{20-16} = fs;
869  let Inst{15-11} = fd;
870  let Inst{9-8}   = fmt;
871  let Inst{7-0}   = funct;
872}
873
874class MFC1_FM_MM<bits<8> funct> : MMArch {
875  bits<5> rt;
876  bits<5> fs;
877
878  bits<32> Inst;
879
880  let Inst{31-26} = 0x15;
881  let Inst{25-21} = rt;
882  let Inst{20-16} = fs;
883  let Inst{15-14} = 0x0;
884  let Inst{13-6}  = funct;
885  let Inst{5-0}   = 0x3b;
886}
887
888class MADDS_FM_MM<bits<6> funct>: MMArch {
889  bits<5> ft;
890  bits<5> fs;
891  bits<5> fd;
892  bits<5> fr;
893
894  bits<32> Inst;
895
896  let Inst{31-26} = 0x15;
897  let Inst{25-21} = ft;
898  let Inst{20-16} = fs;
899  let Inst{15-11} = fd;
900  let Inst{10-6}  = fr;
901  let Inst{5-0}   = funct;
902}
903
904class COMPACT_BRANCH_FM_MM<bits<5> funct> {
905  bits<5>  rs;
906  bits<16> offset;
907
908  bits<32> Inst;
909
910  let Inst{31-26} = 0x10;
911  let Inst{25-21} = funct;
912  let Inst{20-16} = rs;
913  let Inst{15-0}  = offset;
914}
915
916class COP0_TLB_FM_MM<bits<10> op> : MMArch {
917  bits<32> Inst;
918
919  let Inst{31-26} = 0x0;
920  let Inst{25-16} = 0x0;
921  let Inst{15-6}  = op;
922  let Inst{5-0}   = 0x3c;
923}
924
925class SDBBP_FM_MM : MMArch {
926  bits<10> code_;
927
928  bits<32> Inst;
929
930  let Inst{31-26} = 0x0;
931  let Inst{25-16} = code_;
932  let Inst{15-6}  = 0x36d;
933  let Inst{5-0}   = 0x3c;
934}
935
936class SIGRIE_FM_MM : MMArch {
937  bits<16> code_;
938
939  bits<32> Inst;
940
941  let Inst{31-26} = 0x0;
942  let Inst{25-22} = 0x0;
943  let Inst{21-6} = code_;
944  let Inst{5-0} = 0b111111;
945}
946
947class RDHWR_FM_MM : MMArch {
948  bits<5> rt;
949  bits<5> rd;
950
951  bits<32> Inst;
952
953  let Inst{31-26} = 0x0;
954  let Inst{25-21} = rt;
955  let Inst{20-16} = rd;
956  let Inst{15-6}  = 0x1ac;
957  let Inst{5-0}   = 0x3c;
958}
959
960class LWXS_FM_MM<bits<10> funct> {
961  bits<5> rd;
962  bits<5> base;
963  bits<5> index;
964
965  bits<32> Inst;
966
967  let Inst{31-26} = 0x0;
968  let Inst{25-21} = index;
969  let Inst{20-16} = base;
970  let Inst{15-11} = rd;
971  let Inst{10}    = 0;
972  let Inst{9-0}   = funct;
973}
974
975class LWM_FM_MM<bits<4> funct> : MMArch {
976  bits<5> rt;
977  bits<21> addr;
978
979  bits<32> Inst;
980
981  let Inst{31-26} = 0x8;
982  let Inst{25-21} = rt;
983  let Inst{20-16} = addr{20-16};
984  let Inst{15-12} = funct;
985  let Inst{11-0}  = addr{11-0};
986}
987
988class LWM_FM_MM16<bits<4> funct> : MMArch {
989  bits<2> rt;
990  bits<4> addr;
991
992  bits<16> Inst;
993
994  let Inst{15-10} = 0x11;
995  let Inst{9-6}   = funct;
996  let Inst{5-4}   = rt;
997  let Inst{3-0}   = addr;
998}
999
1000class CACHE_PREF_FM_MM<bits<6> op, bits<4> funct> : MMArch {
1001  bits<21> addr;
1002  bits<5> hint;
1003  bits<5> base = addr{20-16};
1004  bits<12> offset = addr{11-0};
1005
1006  bits<32> Inst;
1007
1008  let Inst{31-26} = op;
1009  let Inst{25-21} = hint;
1010  let Inst{20-16} = base;
1011  let Inst{15-12} = funct;
1012  let Inst{11-0}  = offset;
1013}
1014
1015class CACHE_PREFE_FM_MM<bits<6> op, bits<3> funct> : MMArch {
1016  bits<21> addr;
1017  bits<5> hint;
1018  bits<5> base = addr{20-16};
1019  bits<9> offset = addr{8-0};
1020
1021  bits<32> Inst;
1022
1023  let Inst{31-26} = op;
1024  let Inst{25-21} = hint;
1025  let Inst{20-16} = base;
1026  let Inst{15-12} = 0xA;
1027  let Inst{11-9} = funct;
1028  let Inst{8-0}  = offset;
1029}
1030
1031class POOL32F_PREFX_FM_MM<bits<6> op, bits<9> funct> : MMArch {
1032  bits<5> index;
1033  bits<5> base;
1034  bits<5> hint;
1035
1036  bits<32> Inst;
1037
1038  let Inst{31-26} = op;
1039  let Inst{25-21} = index;
1040  let Inst{20-16} = base;
1041  let Inst{15-11} = hint;
1042  let Inst{10-9}  = 0x0;
1043  let Inst{8-0}   = funct;
1044}
1045
1046class BARRIER_FM_MM<bits<5> op> : MMArch {
1047  bits<32> Inst;
1048
1049  let Inst{31-26} = 0x0;
1050  let Inst{25-21} = 0x0;
1051  let Inst{20-16} = 0x0;
1052  let Inst{15-11} = op;
1053  let Inst{10-6}  = 0x0;
1054  let Inst{5-0}   = 0x0;
1055}
1056
1057class ADDIUPC_FM_MM {
1058  bits<3> rs;
1059  bits<23> imm;
1060
1061  bits<32> Inst;
1062
1063  let Inst{31-26} = 0x1e;
1064  let Inst{25-23} = rs;
1065  let Inst{22-0} = imm;
1066}
1067
1068class POOL32A_CFTC2_FM_MM<bits<10> funct> : MMArch {
1069  bits<5> rt;
1070  bits<5> impl;
1071
1072  bits<32> Inst;
1073
1074  let Inst{31-26} = 0b000000;
1075  let Inst{25-21} = rt;
1076  let Inst{20-16} = impl;
1077  let Inst{15-6}  = funct;
1078  let Inst{5-0}   = 0b111100;
1079}
1080
1081class POOL32A_TLBINV_FM_MM<bits<10> funct> : MMArch {
1082  bits<32> Inst;
1083
1084  let Inst{31-26} = 0x0;
1085  let Inst{25-16} = 0x0;
1086  let Inst{15-6}  = funct;
1087  let Inst{5-0}   = 0b111100;
1088}
1089
1090class POOL32A_MFTC0_FM_MM<bits<5> funct, bits<6> opcode> : MMArch {
1091  bits<5> rt;
1092  bits<5> rs;
1093  bits<3> sel;
1094
1095  bits<32> Inst;
1096
1097  let Inst{31-26} = 0b000000;
1098  let Inst{25-21} = rt;
1099  let Inst{20-16} = rs;
1100  let Inst{15-14} = 0;
1101  let Inst{13-11} = sel;
1102  let Inst{10-6}  = funct;
1103  let Inst{5-0}   = opcode;
1104}
1105
1106class POOL32A_HYPCALL_FM_MM : MMArch {
1107  bits<32> Inst;
1108
1109  bits<10> code_;
1110
1111  let Inst{31-26} = 0x0;
1112  let Inst{25-16} = code_;
1113  let Inst{15-6}  = 0b1100001101;
1114  let Inst{5-0}   = 0b111100;
1115}
1116