1//===--- MicroMipsInstrFormats.td - microMIPS Inst Defs -*- tablegen -*----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This files describes the definitions of the microMIPSr3 instructions.
10//
11//===----------------------------------------------------------------------===//
12
13def addrimm11 : ComplexPattern<iPTR, 2, "selectIntAddr11MM", [frameindex]>;
14def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddr12MM", [frameindex]>;
15def addrimm16 : ComplexPattern<iPTR, 2, "selectIntAddr16MM", [frameindex]>;
16def addrimm4lsl2 : ComplexPattern<iPTR, 2, "selectIntAddrLSL2MM", [frameindex]>;
17
18def simm9_addiusp : Operand<i32> {
19  let EncoderMethod = "getSImm9AddiuspValue";
20  let DecoderMethod = "DecodeSimm9SP";
21}
22
23def uimm3_shift : Operand<i32> {
24  let EncoderMethod = "getUImm3Mod8Encoding";
25  let DecoderMethod = "DecodePOOL16BEncodedField";
26}
27
28def simm3_lsa2 : Operand<i32> {
29  let EncoderMethod = "getSImm3Lsa2Value";
30  let DecoderMethod = "DecodeAddiur2Simm7";
31}
32
33def uimm4_andi : Operand<i32> {
34  let EncoderMethod = "getUImm4AndValue";
35  let DecoderMethod = "DecodeANDI16Imm";
36}
37
38def immSExtAddiur2 : ImmLeaf<i32, [{return Imm == 1 || Imm == -1 ||
39                                           ((Imm % 4 == 0) &&
40                                            Imm < 28 && Imm > 0);}]>;
41
42def immSExtAddius5 : ImmLeaf<i32, [{return Imm >= -8 && Imm <= 7;}]>;
43
44def immZExtAndi16 : ImmLeaf<i32,
45  [{return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
46            Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
47            Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );}]>;
48
49def immZExt2Shift : ImmLeaf<i32, [{return Imm >= 1 && Imm <= 8;}]>;
50
51def immLi16 : ImmLeaf<i32, [{return Imm >= -1 && Imm <= 126;}]>;
52
53def MicroMipsMemGPRMM16AsmOperand : AsmOperandClass {
54  let Name = "MicroMipsMem";
55  let RenderMethod = "addMicroMipsMemOperands";
56  let ParserMethod = "parseMemOperand";
57  let PredicateMethod = "isMemWithGRPMM16Base";
58}
59
60// Define the classes of pointers used by microMIPS.
61// The numbers must match those in MipsRegisterInfo::MipsPtrClass.
62def ptr_gpr16mm_rc : PointerLikeRegClass<1>;
63def ptr_sp_rc : PointerLikeRegClass<2>;
64def ptr_gp_rc : PointerLikeRegClass<3>;
65
66class mem_mm_4_generic : Operand<i32> {
67  let PrintMethod = "printMemOperand";
68  let MIOperandInfo = (ops ptr_gpr16mm_rc, simm4);
69  let OperandType = "OPERAND_MEMORY";
70  let ParserMatchClass = MicroMipsMemGPRMM16AsmOperand;
71}
72
73def mem_mm_4 : mem_mm_4_generic {
74  let EncoderMethod = "getMemEncodingMMImm4";
75}
76
77def mem_mm_4_lsl1 : mem_mm_4_generic {
78  let EncoderMethod = "getMemEncodingMMImm4Lsl1";
79}
80
81def mem_mm_4_lsl2 : mem_mm_4_generic {
82  let EncoderMethod = "getMemEncodingMMImm4Lsl2";
83}
84
85def MicroMipsMemSPAsmOperand : AsmOperandClass {
86  let Name = "MicroMipsMemSP";
87  let RenderMethod = "addMemOperands";
88  let ParserMethod = "parseMemOperand";
89  let PredicateMethod = "isMemWithUimmWordAlignedOffsetSP<7>";
90}
91
92def MicroMipsMemGPAsmOperand : AsmOperandClass {
93  let Name = "MicroMipsMemGP";
94  let RenderMethod = "addMemOperands";
95  let ParserMethod = "parseMemOperand";
96  let PredicateMethod = "isMemWithSimmWordAlignedOffsetGP<9>";
97}
98
99def mem_mm_sp_imm5_lsl2 : Operand<i32> {
100  let PrintMethod = "printMemOperand";
101  let MIOperandInfo = (ops ptr_sp_rc:$base, simm5:$offset);
102  let OperandType = "OPERAND_MEMORY";
103  let ParserMatchClass = MicroMipsMemSPAsmOperand;
104  let EncoderMethod = "getMemEncodingMMSPImm5Lsl2";
105}
106
107def mem_mm_gp_simm7_lsl2 : Operand<i32> {
108  let PrintMethod = "printMemOperand";
109  let MIOperandInfo = (ops ptr_gp_rc:$base, simm7_lsl2:$offset);
110  let OperandType = "OPERAND_MEMORY";
111  let ParserMatchClass = MicroMipsMemGPAsmOperand;
112  let EncoderMethod = "getMemEncodingMMGPImm7Lsl2";
113}
114
115def mem_mm_9 : Operand<i32> {
116  let PrintMethod = "printMemOperand";
117  let MIOperandInfo = (ops ptr_rc, simm9);
118  let EncoderMethod = "getMemEncodingMMImm9";
119  let ParserMatchClass = MipsMemSimmAsmOperand<9>;
120  let OperandType = "OPERAND_MEMORY";
121}
122
123def mem_mm_11 : Operand<i32> {
124  let PrintMethod = "printMemOperand";
125  let MIOperandInfo = (ops GPR32, simm11);
126  let EncoderMethod = "getMemEncodingMMImm11";
127  let ParserMatchClass = MipsMemSimmAsmOperand<11>;
128  let OperandType = "OPERAND_MEMORY";
129}
130
131def mem_mm_12 : Operand<i32> {
132  let PrintMethod = "printMemOperand";
133  let MIOperandInfo = (ops ptr_rc, simm12);
134  let EncoderMethod = "getMemEncodingMMImm12";
135  let ParserMatchClass = MipsMemAsmOperand;
136  let OperandType = "OPERAND_MEMORY";
137}
138
139def mem_mm_16 : Operand<i32> {
140  let PrintMethod = "printMemOperand";
141  let MIOperandInfo = (ops ptr_rc, simm16);
142  let EncoderMethod = "getMemEncodingMMImm16";
143  let DecoderMethod = "DecodeMemMMImm16";
144  let ParserMatchClass = MipsMemSimmAsmOperand<16>;
145  let OperandType = "OPERAND_MEMORY";
146}
147
148def MipsMemUimm4AsmOperand : AsmOperandClass {
149  let Name = "MemOffsetUimm4";
150  let SuperClasses = [MipsMemAsmOperand];
151  let RenderMethod = "addMemOperands";
152  let ParserMethod = "parseMemOperand";
153  let PredicateMethod = "isMemWithUimmOffsetSP<6>";
154}
155
156def mem_mm_4sp : Operand<i32> {
157  let PrintMethod = "printMemOperand";
158  let MIOperandInfo = (ops ptr_sp_rc, uimm8);
159  let EncoderMethod = "getMemEncodingMMImm4sp";
160  let ParserMatchClass = MipsMemUimm4AsmOperand;
161  let OperandType = "OPERAND_MEMORY";
162}
163
164def jmptarget_mm : Operand<OtherVT> {
165  let EncoderMethod = "getJumpTargetOpValueMM";
166}
167
168def calltarget_mm : Operand<iPTR> {
169  let EncoderMethod = "getJumpTargetOpValueMM";
170}
171
172def brtarget7_mm : Operand<OtherVT> {
173  let EncoderMethod = "getBranchTarget7OpValueMM";
174  let OperandType   = "OPERAND_PCREL";
175  let DecoderMethod = "DecodeBranchTarget7MM";
176  let ParserMatchClass = MipsJumpTargetAsmOperand;
177}
178
179def brtarget10_mm : Operand<OtherVT> {
180  let EncoderMethod = "getBranchTargetOpValueMMPC10";
181  let OperandType   = "OPERAND_PCREL";
182  let DecoderMethod = "DecodeBranchTarget10MM";
183  let ParserMatchClass = MipsJumpTargetAsmOperand;
184}
185
186def brtarget_mm : Operand<OtherVT> {
187  let EncoderMethod = "getBranchTargetOpValueMM";
188  let OperandType   = "OPERAND_PCREL";
189  let DecoderMethod = "DecodeBranchTargetMM";
190  let ParserMatchClass = MipsJumpTargetAsmOperand;
191}
192
193def simm23_lsl2 : Operand<i32> {
194  let EncoderMethod = "getSimm23Lsl2Encoding";
195  let DecoderMethod = "DecodeSimm23Lsl2";
196}
197
198class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
199                      RegisterOperand RO> :
200  InstSE<(outs), (ins RO:$rs, opnd:$offset),
201         !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZC, FrmI> {
202  let isBranch = 1;
203  let isTerminator = 1;
204  let hasDelaySlot = 0;
205  let Defs = [AT];
206}
207
208let canFoldAsLoad = 1 in
209class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
210                      Operand MemOpnd, InstrItinClass Itin> :
211  InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
212         !strconcat(opstr, "\t$rt, $addr"),
213         [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
214         Itin, FrmI> {
215  let DecoderMethod = "DecodeMemMMImm12";
216  string Constraints = "$src = $rt";
217  let BaseOpcode = opstr;
218  bit mayLoad = 1;
219  bit mayStore = 0;
220}
221
222class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
223                       Operand MemOpnd, InstrItinClass Itin>:
224  InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
225         !strconcat(opstr, "\t$rt, $addr"),
226         [(OpNode RO:$rt, addrimm12:$addr)], Itin, FrmI> {
227  let DecoderMethod = "DecodeMemMMImm12";
228  let BaseOpcode = opstr;
229  bit mayLoad = 0;
230  bit mayStore = 1;
231}
232
233class MovePMM16<string opstr, RegisterOperand RO1, RegisterOperand RO2,
234                RegisterOperand RO3> :
235MicroMipsInst16<(outs RO1:$rd1, RO2:$rd2), (ins RO3:$rs, RO3:$rt),
236                 !strconcat(opstr, "\t$rd1, $rd2, $rs, $rt"), [],
237                 NoItinerary, FrmR> {
238  let isReMaterializable = 1;
239  let isMoveReg = 1;
240  let DecoderMethod = "DecodeMovePOperands";
241}
242
243class StorePairMM<string opstr, ComplexPattern Addr = addr>
244    :  InstSE<(outs), (ins GPR32Opnd:$rt, GPR32Opnd:$rt2, mem_simm12:$addr),
245         !strconcat(opstr, "\t$rt, $addr"), [], II_SWP, FrmI, opstr> {
246  let DecoderMethod = "DecodeMemMMImm12";
247  let mayStore = 1;
248  let AsmMatchConverter = "ConvertXWPOperands";
249}
250
251class LoadPairMM<string opstr, ComplexPattern Addr = addr>
252    : InstSE<(outs GPR32Opnd:$rt, GPR32Opnd:$rt2), (ins mem_simm12:$addr),
253          !strconcat(opstr, "\t$rt, $addr"), [], II_LWP, FrmI, opstr> {
254  let DecoderMethod = "DecodeMemMMImm12";
255  let mayLoad = 1;
256  let AsmMatchConverter = "ConvertXWPOperands";
257}
258
259class LLBaseMM<string opstr, RegisterOperand RO> :
260  InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
261         !strconcat(opstr, "\t$rt, $addr"), [], II_LL, FrmI> {
262  let DecoderMethod = "DecodeMemMMImm12";
263  let mayLoad = 1;
264}
265
266class LLEBaseMM<string opstr, RegisterOperand RO> :
267  InstSE<(outs RO:$rt), (ins mem_simm9:$addr),
268         !strconcat(opstr, "\t$rt, $addr"), [], II_LLE, FrmI> {
269  let DecoderMethod = "DecodeMemMMImm9";
270  string BaseOpcode = opstr;
271  let mayLoad = 1;
272}
273
274class SCBaseMM<string opstr, RegisterOperand RO> :
275  InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
276         !strconcat(opstr, "\t$rt, $addr"), [], II_SC, FrmI> {
277  let DecoderMethod = "DecodeMemMMImm12";
278  let mayStore = 1;
279  let Constraints = "$rt = $dst";
280}
281
282class SCEBaseMM<string opstr, RegisterOperand RO> :
283  InstSE<(outs RO:$dst), (ins RO:$rt, mem_simm9:$addr),
284         !strconcat(opstr, "\t$rt, $addr"), [], II_SCE, FrmI> {
285  let DecoderMethod = "DecodeMemMMImm9";
286  string BaseOpcode = opstr;
287  let mayStore = 1;
288  let Constraints = "$rt = $dst";
289}
290
291class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
292             InstrItinClass Itin = NoItinerary, DAGOperand MO = mem_mm_12> :
293  InstSE<(outs RO:$rt), (ins MO:$addr),
294         !strconcat(opstr, "\t$rt, $addr"),
295         [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI, opstr> {
296  let DecoderMethod = "DecodeMemMMImm12";
297  let canFoldAsLoad = 1;
298  let mayLoad = 1;
299}
300
301class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0,
302                 InstrItinClass Itin = NoItinerary,
303                 SDPatternOperator OpNode = null_frag> :
304  MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),
305                  !strconcat(opstr, "\t$rd, $rs, $rt"),
306                  [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
307  let isCommutable = isComm;
308}
309
310class AndImmMM16<string opstr, RegisterOperand RO,
311                 InstrItinClass Itin = NoItinerary> :
312  MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, uimm4_andi:$imm),
313                  !strconcat(opstr, "\t$rd, $rs, $imm"), [], Itin, FrmI>;
314
315class LogicRMM16<string opstr, RegisterOperand RO,
316                 InstrItinClass Itin = NoItinerary,
317                 SDPatternOperator OpNode = null_frag> :
318  MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
319         !strconcat(opstr, "\t$rt, $rs"),
320         [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
321  let isCommutable = 1;
322  let Constraints = "$rt = $dst";
323}
324
325class NotMM16<string opstr, RegisterOperand RO> :
326  MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
327         !strconcat(opstr, "\t$rt, $rs"),
328         [(set RO:$rt, (not RO:$rs))], II_NOT, FrmR>;
329
330class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,
331                 InstrItinClass Itin = NoItinerary> :
332  MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
333                  !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;
334
335class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode,
336               InstrItinClass Itin, Operand MemOpnd> :
337  MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$addr),
338                  !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
339  let DecoderMethod = "DecodeMemMMImm4";
340  let canFoldAsLoad = 1;
341  let mayLoad = 1;
342}
343
344class StoreMM16<string opstr, DAGOperand RTOpnd, DAGOperand RO,
345                SDPatternOperator OpNode, InstrItinClass Itin,
346                Operand MemOpnd> :
347  MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
348                  !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
349  let DecoderMethod = "DecodeMemMMImm4";
350  let mayStore = 1;
351}
352
353class LoadSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
354                 Operand MemOpnd> :
355  MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
356                  !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
357  let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
358  let canFoldAsLoad = 1;
359  let mayLoad = 1;
360}
361
362class StoreSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
363                  Operand MemOpnd> :
364  MicroMipsInst16<(outs), (ins RO:$rt, MemOpnd:$offset),
365                  !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
366  let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
367  let mayStore = 1;
368}
369
370class LoadGPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
371                 Operand MemOpnd> :
372  MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
373                  !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
374  let DecoderMethod = "DecodeMemMMGPImm7Lsl2";
375  let canFoldAsLoad = 1;
376  let mayLoad = 1;
377}
378
379class AddImmUR2<string opstr, RegisterOperand RO> :
380  MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
381                  !strconcat(opstr, "\t$rd, $rs, $imm"),
382                  [], II_ADDIU, FrmR> {
383  let isCommutable = 1;
384}
385
386class AddImmUS5<string opstr, RegisterOperand RO> :
387  MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
388                  !strconcat(opstr, "\t$rd, $imm"), [], II_ADDIU, FrmR> {
389  let Constraints = "$rd = $dst";
390}
391
392class AddImmUR1SP<string opstr, RegisterOperand RO> :
393  MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm),
394                  !strconcat(opstr, "\t$rd, $imm"), [], II_ADDIU, FrmR>;
395
396class AddImmUSP<string opstr> :
397  MicroMipsInst16<(outs), (ins simm9_addiusp:$imm),
398                  !strconcat(opstr, "\t$imm"), [], II_ADDIU, FrmI>;
399
400class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
401      MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
402  [], II_MFHI_MFLO, FrmR> {
403  let Uses = [UseReg];
404  let hasSideEffects = 0;
405  let isMoveReg = 1;
406}
407
408class MoveMM16<string opstr, RegisterOperand RO>
409    :  MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
410                       !strconcat(opstr, "\t$rd, $rs"), [], II_MOVE, FrmR> {
411  let isReMaterializable = 1;
412  let isMoveReg = 1;
413}
414
415class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO> :
416  MicroMipsInst16<(outs RO:$rd), (ins Od:$imm),
417                  !strconcat(opstr, "\t$rd, $imm"), [], II_LI, FrmI> {
418  let isReMaterializable = 1;
419}
420
421// 16-bit Jump and Link (Call)
422class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
423  MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
424           [(MipsJmpLink RO:$rs)], II_JALR, FrmR> {
425  let isCall = 1;
426  let hasDelaySlot = 1;
427  let Defs = [RA];
428  let hasPostISelHook = 1;
429}
430
431// 16-bit Jump Reg
432class JumpRegMM16<string opstr, RegisterOperand RO> :
433  MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
434           [], II_JR, FrmR> {
435  let hasDelaySlot = 1;
436  let isBranch = 1;
437  let isIndirectBranch = 1;
438}
439
440// Base class for JRADDIUSP instruction.
441class JumpRAddiuStackMM16 :
442  MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jraddiusp\t$imm",
443                  [], II_JRADDIUSP, FrmR> {
444  let isTerminator = 1;
445  let isBarrier = 1;
446  let isBranch = 1;
447  let isIndirectBranch = 1;
448}
449
450// 16-bit Jump and Link (Call) - Short Delay Slot
451class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
452  MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
453           [], II_JALRS, FrmR> {
454  let isCall = 1;
455  let hasDelaySlot = 1;
456  let Defs = [RA];
457}
458
459// 16-bit Jump Register Compact - No delay slot
460class JumpRegCMM16<string opstr, RegisterOperand RO> :
461  MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
462                  [], II_JRC, FrmR> {
463  let isTerminator = 1;
464  let isBarrier = 1;
465  let isBranch = 1;
466  let isIndirectBranch = 1;
467}
468
469// Break16 and Sdbbp16
470class BrkSdbbp16MM<string opstr, InstrItinClass Itin> :
471  MicroMipsInst16<(outs), (ins uimm4:$code_),
472                  !strconcat(opstr, "\t$code_"),
473                  [], Itin, FrmOther>;
474
475class CBranchZeroMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
476  MicroMipsInst16<(outs), (ins RO:$rs, opnd:$offset),
477                  !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZ, FrmI> {
478  let isBranch = 1;
479  let isTerminator = 1;
480  let hasDelaySlot = 1;
481  let Defs = [AT];
482}
483
484// MicroMIPS Jump and Link (Call) - Short Delay Slot
485let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
486  class JumpLinkMM<string opstr, DAGOperand opnd> :
487    InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
488           [], II_JALS, FrmJ, opstr> {
489    let DecoderMethod = "DecodeJumpTargetMM";
490  }
491
492  class JumpLinkRegMM<string opstr, RegisterOperand RO>:
493    InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
494            [], II_JALRS, FrmR>;
495
496  class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd,
497                                  RegisterOperand RO> :
498    InstSE<(outs), (ins RO:$rs, opnd:$offset),
499           !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZALS, FrmI, opstr>;
500}
501
502class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO,
503                              SDPatternOperator OpNode = null_frag> :
504  InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index),
505         !strconcat(opstr, "\t$rd, ${index}(${base})"), [], II_LWXS, FrmFI>;
506
507class PrefetchIndexed<string opstr> :
508  InstSE<(outs), (ins PtrRC:$base, PtrRC:$index, uimm5:$hint),
509         !strconcat(opstr, "\t$hint, ${index}(${base})"),
510         [], II_PREF, FrmOther>;
511
512class AddImmUPC<string opstr, RegisterOperand RO> :
513  InstSE<(outs RO:$rs), (ins simm23_lsl2:$imm),
514         !strconcat(opstr, "\t$rs, $imm"), [], II_ADDIU, FrmR>;
515
516/// A list of registers used by load/store multiple instructions.
517def RegListAsmOperand : AsmOperandClass {
518  let Name = "RegList";
519  let ParserMethod = "parseRegisterList";
520}
521
522def reglist : Operand<i32> {
523  let EncoderMethod = "getRegisterListOpValue";
524  let ParserMatchClass = RegListAsmOperand;
525  let PrintMethod = "printRegisterList";
526  let DecoderMethod = "DecodeRegListOperand";
527}
528
529def RegList16AsmOperand : AsmOperandClass {
530  let Name = "RegList16";
531  let ParserMethod = "parseRegisterList";
532  let PredicateMethod = "isRegList16";
533  let RenderMethod = "addRegListOperands";
534}
535
536def reglist16 : Operand<i32> {
537  let EncoderMethod = "getRegisterListOpValue16";
538  let DecoderMethod = "DecodeRegListOperand16";
539  let PrintMethod = "printRegisterList";
540  let ParserMatchClass = RegList16AsmOperand;
541}
542
543class StoreMultMM<string opstr,
544            InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
545  InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),
546         !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
547  let DecoderMethod = "DecodeMemMMImm12";
548  let mayStore = 1;
549}
550
551class LoadMultMM<string opstr,
552            InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
553  InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr),
554          !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
555  let DecoderMethod = "DecodeMemMMImm12";
556  let mayLoad = 1;
557}
558
559class StoreMultMM16<string opstr,
560                    InstrItinClass Itin = NoItinerary,
561                    ComplexPattern Addr = addr> :
562  MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
563                  !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
564  let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
565  let mayStore = 1;
566}
567
568class LoadMultMM16<string opstr,
569                   InstrItinClass Itin = NoItinerary,
570                   ComplexPattern Addr = addr> :
571  MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
572                  !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
573  let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
574  let mayLoad = 1;
575}
576
577class UncondBranchMM16<string opstr> :
578  MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
579                  !strconcat(opstr, "\t$offset"),
580                  [], II_B, FrmI> {
581  let isBranch = 1;
582  let isTerminator = 1;
583  let isBarrier = 1;
584  let hasDelaySlot = 1;
585  let Predicates = [RelocPIC, InMicroMips];
586  let Defs = [AT];
587}
588
589class HypcallMM<string opstr> :
590  InstSE<(outs), (ins uimm10:$code_),
591          !strconcat(opstr, "\t$code_"), [], II_HYPCALL, FrmOther> {
592  let BaseOpcode = opstr;
593}
594
595class TLBINVMM<string opstr, InstrItinClass Itin> :
596  InstSE<(outs), (ins), opstr, [], Itin, FrmOther> {
597  let BaseOpcode = opstr;
598}
599
600class MfCop0MM<string opstr, RegisterOperand DstRC,
601               RegisterOperand SrcRC, InstrItinClass Itin> :
602  InstSE<(outs DstRC:$rt), (ins SrcRC:$rs, uimm3:$sel),
603          !strconcat(opstr, "\t$rt, $rs, $sel"), [], Itin, FrmR> {
604  let BaseOpcode = opstr;
605}
606
607class MtCop0MM<string opstr, RegisterOperand DstRC,
608               RegisterOperand SrcRC, InstrItinClass Itin> :
609  InstSE<(outs DstRC:$rs), (ins SrcRC:$rt, uimm3:$sel),
610          !strconcat(opstr, "\t$rt, $rs, $sel"), [], Itin, FrmR> {
611  let BaseOpcode = opstr;
612}
613
614let FastISelShouldIgnore = 1 in {
615  def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
616      ARITH_FM_MM16<0>, ISA_MICROMIPS32_NOT_MIPS32R6;
617  def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
618      LOGIC_FM_MM16<0x2>, ISA_MICROMIPS32_NOT_MIPS32R6;
619}
620
621def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>,
622                ISA_MICROMIPS32_NOT_MIPS32R6;
623def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>,
624               ISA_MICROMIPS32_NOT_MIPS32R6;
625let FastISelShouldIgnore = 1 in
626  def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>, LOGIC_FM_MM16<0x3>,
627                ISA_MICROMIPS32_NOT_MIPS32R6;
628def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
629    SHIFT_FM_MM16<0>, ISA_MICROMIPS32_NOT_MIPS32R6;
630def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
631    SHIFT_FM_MM16<1>, ISA_MICROMIPS32_NOT_MIPS32R6;
632
633let FastISelShouldIgnore = 1 in {
634  def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
635                  ARITH_FM_MM16<1>, ISA_MICROMIPS32_NOT_MIPS32R6;
636  def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
637                 LOGIC_FM_MM16<0x1>, ISA_MICROMIPS32_NOT_MIPS32R6;
638}
639def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU,
640                        mem_mm_4>, LOAD_STORE_FM_MM16<0x02>, ISA_MICROMIPS;
641def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU,
642                        mem_mm_4_lsl1>, LOAD_STORE_FM_MM16<0x0a>, ISA_MICROMIPS;
643def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, load, II_LW, mem_mm_4_lsl2>,
644                      LOAD_STORE_FM_MM16<0x1a>, ISA_MICROMIPS;
645def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei8,
646                        II_SB, mem_mm_4>, LOAD_STORE_FM_MM16<0x22>,
647                        ISA_MICROMIPS32_NOT_MIPS32R6;
648def SH16_MM : StoreMM16<"sh16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei16,
649                        II_SH, mem_mm_4_lsl1>,
650                        LOAD_STORE_FM_MM16<0x2a>, ISA_MICROMIPS32_NOT_MIPS32R6;
651def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, GPRMM16Opnd, store, II_SW,
652                        mem_mm_4_lsl2>, LOAD_STORE_FM_MM16<0x3a>,
653                        ISA_MICROMIPS32_NOT_MIPS32R6;
654def LWGP_MM : LoadGPMM16<"lw", GPRMM16Opnd, II_LW, mem_mm_gp_simm7_lsl2>,
655                         LOAD_GP_FM_MM16<0x19>, ISA_MICROMIPS;
656def LWSP_MM : LoadSPMM16<"lw", GPR32Opnd, II_LW, mem_mm_sp_imm5_lsl2>,
657              LOAD_STORE_SP_FM_MM16<0x12>, ISA_MICROMIPS;
658def SWSP_MM : StoreSPMM16<"swsp", GPR32Opnd, II_SW, mem_mm_sp_imm5_lsl2>,
659              LOAD_STORE_SP_FM_MM16<0x32>, ISA_MICROMIPS32_NOT_MIPS32R6;
660def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16,
661                   ISA_MICROMIPS;
662def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16,
663                 ISA_MICROMIPS;
664def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16,
665                 ISA_MICROMIPS;
666def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16, ISA_MICROMIPS;
667def MFHI16_MM : MoveFromHILOMM<"mfhi16", GPR32Opnd, AC0>,
668                MFHILO_FM_MM16<0x10>, ISA_MICROMIPS32_NOT_MIPS32R6;
669def MFLO16_MM : MoveFromHILOMM<"mflo16", GPR32Opnd, AC0>,
670                MFHILO_FM_MM16<0x12>, ISA_MICROMIPS32_NOT_MIPS32R6;
671def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>,
672                ISA_MICROMIPS32_NOT_MIPS32R6;
673def MOVEP_MM : MovePMM16<"movep", GPRMM16OpndMovePPairFirst,
674                         GPRMM16OpndMovePPairSecond, GPRMM16OpndMoveP>,
675               MOVEP_FM_MM16, ISA_MICROMIPS32_NOT_MIPS32R6;
676def LI16_MM : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>, LI_FM_MM16,
677              IsAsCheapAsAMove, ISA_MICROMIPS32_NOT_MIPS32R6;
678def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>,
679                ISA_MICROMIPS32_NOT_MIPS32R6;
680def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>,
681                 ISA_MICROMIPS32_NOT_MIPS32R6;
682def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>,
683               ISA_MICROMIPS32_NOT_MIPS32R6;
684def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>,
685                ISA_MICROMIPS32_NOT_MIPS32R6;
686def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>,
687              ISA_MICROMIPS32_NOT_MIPS32R6;
688def BEQZ16_MM : CBranchZeroMM<"beqz16", brtarget7_mm, GPRMM16Opnd>,
689                BEQNEZ_FM_MM16<0x23>, ISA_MICROMIPS32_NOT_MIPS32R6;
690def BNEZ16_MM : CBranchZeroMM<"bnez16", brtarget7_mm, GPRMM16Opnd>,
691                BEQNEZ_FM_MM16<0x2b>, ISA_MICROMIPS32_NOT_MIPS32R6;
692def B16_MM : UncondBranchMM16<"b16">, B16_FM, ISA_MICROMIPS32_NOT_MIPS32R6;
693def BREAK16_MM : BrkSdbbp16MM<"break16", II_BREAK>, BRKSDBBP16_FM_MM<0x28>,
694                 ISA_MICROMIPS32_NOT_MIPS32R6;
695def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, BRKSDBBP16_FM_MM<0x2C>,
696                 ISA_MICROMIPS32_NOT_MIPS32R6;
697
698class WaitMM<string opstr> :
699  InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
700         II_WAIT, FrmOther, opstr>;
701
702let DecoderNamespace = "MicroMips" in {
703  /// Load and Store Instructions - multiple
704  def SWM16_MM : StoreMultMM16<"swm16", II_SWM>, LWM_FM_MM16<0x5>,
705                 ISA_MICROMIPS32_NOT_MIPS32R6;
706  def LWM16_MM : LoadMultMM16<"lwm16", II_LWM>, LWM_FM_MM16<0x4>,
707                 ISA_MICROMIPS32_NOT_MIPS32R6;
708  def CFC2_MM : InstSE<(outs GPR32Opnd:$rt), (ins COP2Opnd:$impl),
709                       "cfc2\t$rt, $impl", [], II_CFC2, FrmFR, "cfc2">,
710                POOL32A_CFTC2_FM_MM<0b1100110100>, ISA_MICROMIPS;
711  def CTC2_MM : InstSE<(outs COP2Opnd:$impl), (ins GPR32Opnd:$rt),
712                       "ctc2\t$rt, $impl", [], II_CTC2, FrmFR, "ctc2">,
713                POOL32A_CFTC2_FM_MM<0b1101110100>, ISA_MICROMIPS;
714
715  /// Compact Branch Instructions
716  def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>,
717                 COMPACT_BRANCH_FM_MM<0x7>, ISA_MICROMIPS32_NOT_MIPS32R6;
718  def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,
719                 COMPACT_BRANCH_FM_MM<0x5>, ISA_MICROMIPS32_NOT_MIPS32R6;
720
721  /// Arithmetic Instructions (ALU Immediate)
722  def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU>,
723                 ADDI_FM_MM<0xc>, ISA_MICROMIPS32_NOT_MIPS32R6;
724  def ADDi_MM  : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd, II_ADDI>,
725                 ADDI_FM_MM<0x4>, ISA_MICROMIPS32_NOT_MIPS32R6;
726  def SLTi_MM  : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
727                 SLTI_FM_MM<0x24>, ISA_MICROMIPS;
728  def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
729                 SLTI_FM_MM<0x2c>, ISA_MICROMIPS;
730  def ANDi_MM  : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI>,
731                 ADDI_FM_MM<0x34>, ISA_MICROMIPS32_NOT_MIPS32R6;
732  def ORi_MM   : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
733                                    or>, ADDI_FM_MM<0x14>,
734                 ISA_MICROMIPS32_NOT_MIPS32R6;
735  def XORi_MM  : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI,
736                                    immZExt16, xor>, ADDI_FM_MM<0x1c>,
737                 ISA_MICROMIPS32_NOT_MIPS32R6;
738  def LUi_MM   : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM_MM,
739                 ISA_MICROMIPS32_NOT_MIPS32R6;
740
741  def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
742                     LW_FM_MM<0xc>, ISA_MICROMIPS;
743
744  /// Arithmetic Instructions (3-Operand, R-Type)
745  def ADDu_MM  : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
746                 ADD_FM_MM<0, 0x150>, ISA_MICROMIPS32_NOT_MIPS32R6;
747  def SUBu_MM  : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
748                 ADD_FM_MM<0, 0x1d0>, ISA_MICROMIPS32_NOT_MIPS32R6;
749  let Defs = [HI0, LO0] in
750    def MUL_MM   : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
751                   ADD_FM_MM<0, 0x210>, ISA_MICROMIPS32_NOT_MIPS32R6;
752  def ADD_MM   : MMRel, ArithLogicR<"add", GPR32Opnd, 1, II_ADD>,
753                 ADD_FM_MM<0, 0x110>, ISA_MICROMIPS32_NOT_MIPS32R6;
754  def SUB_MM   : MMRel, ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>,
755                 ADD_FM_MM<0, 0x190>, ISA_MICROMIPS32_NOT_MIPS32R6;
756  def SLT_MM   : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>,
757                 ISA_MICROMIPS;
758  def SLTu_MM  : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
759                 ADD_FM_MM<0, 0x390>, ISA_MICROMIPS;
760  def AND_MM   : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
761                 ADD_FM_MM<0, 0x250>, ISA_MICROMIPS32_NOT_MIPS32R6;
762  def OR_MM    : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
763                 ADD_FM_MM<0, 0x290>, ISA_MICROMIPS32_NOT_MIPS32R6;
764  def XOR_MM   : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
765                 ADD_FM_MM<0, 0x310>, ISA_MICROMIPS32_NOT_MIPS32R6;
766  def NOR_MM   : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>,
767                 ISA_MICROMIPS32_NOT_MIPS32R6;
768  def MULT_MM  : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
769                 MULT_FM_MM<0x22c>, ISA_MICROMIPS32_NOT_MIPS32R6;
770  def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
771                 MULT_FM_MM<0x26c>, ISA_MICROMIPS32_NOT_MIPS32R6;
772  def SDIV_MM  : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
773                 MULT_FM_MM<0x2ac>, ISA_MICROMIPS32_NOT_MIPS32R6;
774  def UDIV_MM  : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
775                 MULT_FM_MM<0x2ec>, ISA_MICROMIPS32_NOT_MIPS32R6;
776
777  /// Arithmetic Instructions with PC and Immediate
778  def ADDIUPC_MM : AddImmUPC<"addiupc", GPRMM16Opnd>, ADDIUPC_FM_MM,
779                   ISA_MICROMIPS32_NOT_MIPS32R6;
780
781  /// Shift Instructions
782  def SLL_MM   : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
783                 SRA_FM_MM<0, 0>, ISA_MICROMIPS;
784  def SRL_MM   : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
785                 SRA_FM_MM<0x40, 0>, ISA_MICROMIPS;
786  def SRA_MM   : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
787                 SRA_FM_MM<0x80, 0>, ISA_MICROMIPS;
788  def SLLV_MM  : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
789                 SRLV_FM_MM<0x10, 0>, ISA_MICROMIPS;
790  def SRLV_MM  : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
791                 SRLV_FM_MM<0x50, 0>, ISA_MICROMIPS;
792  def SRAV_MM  : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
793                 SRLV_FM_MM<0x90, 0>, ISA_MICROMIPS;
794  def ROTR_MM  : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
795                 SRA_FM_MM<0xc0, 0>, ISA_MICROMIPS {
796    list<dag> Pattern = [(set GPR32Opnd:$rd,
797                          (rotr GPR32Opnd:$rt, immZExt5:$shamt))];
798  }
799  def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
800                 SRLV_FM_MM<0xd0, 0>, ISA_MICROMIPS {
801    list<dag> Pattern = [(set GPR32Opnd:$rd,
802                          (rotr GPR32Opnd:$rt, GPR32Opnd:$rs))];
803  }
804
805  /// Load and Store Instructions - aligned
806  let DecoderMethod = "DecodeMemMMImm16" in {
807    def LB_MM  : LoadMemory<"lb", GPR32Opnd, mem_mm_16, sextloadi8, II_LB>,
808                 MMRel, LW_FM_MM<0x7>, ISA_MICROMIPS;
809    def LBu_MM : LoadMemory<"lbu", GPR32Opnd, mem_mm_16, zextloadi8, II_LBU>,
810                 MMRel, LW_FM_MM<0x5>, ISA_MICROMIPS;
811    def LH_MM  : LoadMemory<"lh", GPR32Opnd, mem_simmptr, sextloadi16, II_LH,
812                            addrDefault>, MMRel, LW_FM_MM<0xf>, ISA_MICROMIPS;
813    def LHu_MM : LoadMemory<"lhu", GPR32Opnd, mem_simmptr, zextloadi16, II_LHU>,
814                 MMRel, LW_FM_MM<0xd>, ISA_MICROMIPS;
815    def LW_MM  : Load<"lw", GPR32Opnd, null_frag, II_LW>, MMRel, LW_FM_MM<0x3f>,
816                 ISA_MICROMIPS;
817    def SB_MM  : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel,
818                 LW_FM_MM<0x6>, ISA_MICROMIPS;
819    def SH_MM  : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel,
820                 LW_FM_MM<0xe>, ISA_MICROMIPS;
821    def SW_MM  : Store<"sw", GPR32Opnd, null_frag, II_SW>, MMRel,
822                 LW_FM_MM<0x3e>, ISA_MICROMIPS;
823  }
824
825  let DecoderMethod = "DecodeMemMMImm9" in {
826    def LBE_MM  : MMRel, Load<"lbe", GPR32Opnd, null_frag, II_LBE>,
827                  POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>, ISA_MICROMIPS, ASE_EVA;
828    def LBuE_MM : MMRel, Load<"lbue", GPR32Opnd, null_frag, II_LBUE>,
829                  POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>, ISA_MICROMIPS, ASE_EVA;
830    def LHE_MM  : MMRel, LoadMemory<"lhe", GPR32Opnd, mem_simm9, null_frag,
831                                    II_LHE>,
832                  POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>, ISA_MICROMIPS, ASE_EVA;
833    def LHuE_MM : MMRel, LoadMemory<"lhue", GPR32Opnd, mem_simm9, null_frag,
834                                    II_LHUE>,
835                  POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>, ISA_MICROMIPS, ASE_EVA;
836    def LWE_MM  : MMRel, LoadMemory<"lwe", GPR32Opnd, mem_simm9, null_frag,
837                                    II_LWE>,
838                  POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>, ISA_MICROMIPS, ASE_EVA;
839    def SBE_MM  : MMRel, StoreMemory<"sbe", GPR32Opnd, mem_simm9, null_frag,
840                                     II_SBE>,
841                  POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>, ISA_MICROMIPS, ASE_EVA;
842    def SHE_MM  : MMRel, StoreMemory<"she", GPR32Opnd, mem_simm9, null_frag,
843                                     II_SHE>,
844                  POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>, ISA_MICROMIPS, ASE_EVA;
845    def SWE_MM  : MMRel, StoreMemory<"swe", GPR32Opnd, mem_simm9, null_frag,
846                                     II_SWE>,
847                  POOL32C_LHUE_FM_MM<0x18, 0xa, 0x7>, ISA_MICROMIPS, ASE_EVA;
848    def LWLE_MM : MMRel, LoadLeftRightMM<"lwle", MipsLWL, GPR32Opnd, mem_mm_9,
849                                         II_LWLE>,
850                  POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x2>,
851                  ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA;
852    def LWRE_MM : MMRel, LoadLeftRightMM<"lwre", MipsLWR, GPR32Opnd, mem_mm_9,
853                                         II_LWRE>,
854                  POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x3>,
855                  ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA;
856    def SWLE_MM : MMRel, StoreLeftRightMM<"swle", MipsSWL, GPR32Opnd, mem_mm_9,
857                                          II_SWLE>,
858                  POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x0>,
859                  ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA;
860    def SWRE_MM : MMRel, StoreLeftRightMM<"swre", MipsSWR, GPR32Opnd, mem_mm_9,
861                                          II_SWRE>,
862                  POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x1>,
863                  ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA;
864  }
865
866  def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>,
867                ISA_MICROMIPS;
868
869  /// Load and Store Instructions - unaligned
870  def LWL_MM : MMRel, LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12,
871                                      II_LWL>, LWL_FM_MM<0x0>,
872               ISA_MICROMIPS32_NOT_MIPS32R6;
873  def LWR_MM : MMRel, LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12,
874                                      II_LWR>, LWL_FM_MM<0x1>,
875               ISA_MICROMIPS32_NOT_MIPS32R6;
876  def SWL_MM : MMRel, StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12,
877                                       II_SWL>, LWL_FM_MM<0x8>,
878               ISA_MICROMIPS32_NOT_MIPS32R6;
879  def SWR_MM : MMRel, StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12,
880                                       II_SWR>, LWL_FM_MM<0x9>,
881               ISA_MICROMIPS32_NOT_MIPS32R6;
882
883  /// Load and Store Instructions - multiple
884  def SWM32_MM  : StoreMultMM<"swm32", II_SWM>, LWM_FM_MM<0xd>, ISA_MICROMIPS;
885  def LWM32_MM  : LoadMultMM<"lwm32", II_LWM>, LWM_FM_MM<0x5>, ISA_MICROMIPS;
886
887  /// Load and Store Pair Instructions
888  def SWP_MM  : StorePairMM<"swp">, LWM_FM_MM<0x9>, ISA_MICROMIPS;
889  def LWP_MM  : LoadPairMM<"lwp">, LWM_FM_MM<0x1>, ISA_MICROMIPS;
890
891  /// Load and Store multiple pseudo Instructions
892  class LoadWordMultMM<string instr_asm > :
893    MipsAsmPseudoInst<(outs reglist:$rt), (ins mem_mm_12:$addr),
894                      !strconcat(instr_asm, "\t$rt, $addr")> ;
895
896  class StoreWordMultMM<string instr_asm > :
897    MipsAsmPseudoInst<(outs), (ins reglist:$rt, mem_mm_12:$addr),
898                      !strconcat(instr_asm, "\t$rt, $addr")> ;
899
900
901  def SWM_MM  : StoreWordMultMM<"swm">, ISA_MICROMIPS;
902  def LWM_MM  : LoadWordMultMM<"lwm">, ISA_MICROMIPS;
903
904  /// Move Conditional
905  def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
906                                     II_MOVZ>, ADD_FM_MM<0, 0x58>,
907                  ISA_MICROMIPS32_NOT_MIPS32R6;
908  def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
909                                     II_MOVN>, ADD_FM_MM<0, 0x18>,
910                  ISA_MICROMIPS32_NOT_MIPS32R6;
911  def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT, MipsCMovFP_T>,
912                  CMov_F_I_FM_MM<0x25>, ISA_MICROMIPS32_NOT_MIPS32R6;
913  def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF, MipsCMovFP_F>,
914                  CMov_F_I_FM_MM<0x5>, ISA_MICROMIPS32_NOT_MIPS32R6;
915  /// Move to/from HI/LO
916  def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
917                MTLO_FM_MM<0x0b5>, ISA_MICROMIPS32_NOT_MIPS32R6;
918  def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
919                MTLO_FM_MM<0x0f5>, ISA_MICROMIPS32_NOT_MIPS32R6;
920  def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
921                MFLO_FM_MM<0x035>, ISA_MICROMIPS32_NOT_MIPS32R6;
922  def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
923                MFLO_FM_MM<0x075>, ISA_MICROMIPS32_NOT_MIPS32R6;
924
925  /// Multiply Add/Sub Instructions
926  def MADD_MM  : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>,
927                 ISA_MICROMIPS32_NOT_MIPS32R6;
928  def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>,
929                 ISA_MICROMIPS32_NOT_MIPS32R6;
930  def MSUB_MM  : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>,
931                 ISA_MICROMIPS32_NOT_MIPS32R6;
932  def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>,
933                 ISA_MICROMIPS32_NOT_MIPS32R6;
934
935  /// Count Leading
936  def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM_MM<0x16c>,
937               ISA_MICROMIPS;
938  def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd, II_CLO>, CLO_FM_MM<0x12c>,
939               ISA_MICROMIPS;
940
941  /// Sign Ext In Register Instructions.
942  def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
943               SEB_FM_MM<0x0ac>, ISA_MICROMIPS;
944  def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
945               SEB_FM_MM<0x0ec>, ISA_MICROMIPS;
946
947  /// Word Swap Bytes Within Halfwords
948  def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>,
949                SEB_FM_MM<0x1ec>, ISA_MICROMIPS;
950  // TODO: Add '0 < pos+size <= 32' constraint check to ext instruction
951  def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, immZExt5,
952                              immZExt5Plus1, MipsExt>, EXT_FM_MM<0x2c>,
953               ISA_MICROMIPS32_NOT_MIPS32R6;
954  def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, uimm5_inssize_plus1,
955                              immZExt5, immZExt5Plus1>,
956               EXT_FM_MM<0x0c>, ISA_MICROMIPS32_NOT_MIPS32R6;
957
958  /// Jump Instructions
959  let DecoderMethod = "DecodeJumpTargetMM" in {
960    def J_MM          : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
961                        J_FM_MM<0x35>, AdditionalRequires<[RelocNotPIC]>,
962                        IsBranch, ISA_MICROMIPS32_NOT_MIPS32R6;
963    def JAL_MM      : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>,
964                      ISA_MICROMIPS32_NOT_MIPS32R6;
965  }
966
967  let DecoderMethod = "DecodeJumpTargetXMM" in
968    def JALX_MM     : MMRel, JumpLink<"jalx", calltarget>, J_FM_MM<0x3c>,
969                      ISA_MICROMIPS32_NOT_MIPS32R6;
970
971  def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>,
972              ISA_MICROMIPS32_NOT_MIPS32R6;
973  def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>,
974                ISA_MICROMIPS32_NOT_MIPS32R6;
975
976  /// Jump Instructions - Short Delay Slot
977  def JALS_MM   : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>,
978                  ISA_MICROMIPS32_NOT_MIPS32R6;
979  def JALRS_MM  : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>,
980                  ISA_MICROMIPS32_NOT_MIPS32R6;
981
982  /// Branch Instructions
983  def BEQ_MM  : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
984                BEQ_FM_MM<0x25>, ISA_MICROMIPS32_NOT_MIPS32R6;
985  def BNE_MM  : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
986                BEQ_FM_MM<0x2d>, ISA_MICROMIPS32_NOT_MIPS32R6;
987  def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
988                BGEZ_FM_MM<0x2>, ISA_MICROMIPS32_NOT_MIPS32R6;
989  def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
990                BGEZ_FM_MM<0x6>, ISA_MICROMIPS32_NOT_MIPS32R6;
991  def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
992                BGEZ_FM_MM<0x4>, ISA_MICROMIPS32_NOT_MIPS32R6;
993  def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
994                BGEZ_FM_MM<0x0>, ISA_MICROMIPS32_NOT_MIPS32R6;
995  def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
996                  BGEZAL_FM_MM<0x03>, ISA_MICROMIPS32_NOT_MIPS32R6;
997  def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
998                  BGEZAL_FM_MM<0x01>, ISA_MICROMIPS32_NOT_MIPS32R6;
999  def BAL_BR_MM : BAL_BR_Pseudo<BGEZAL_MM, brtarget_mm>,
1000                  ISA_MICROMIPS32_NOT_MIPS32R6;
1001
1002  /// Branch Instructions - Short Delay Slot
1003  def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm,
1004                                             GPR32Opnd>, BGEZAL_FM_MM<0x13>,
1005                   ISA_MICROMIPS32_NOT_MIPS32R6;
1006  def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm,
1007                                             GPR32Opnd>, BGEZAL_FM_MM<0x11>,
1008                   ISA_MICROMIPS32_NOT_MIPS32R6;
1009  def B_MM    : UncondBranch<BEQ_MM, brtarget_mm>, IsBranch,
1010                ISA_MICROMIPS32_NOT_MIPS32R6;
1011
1012  /// Control Instructions
1013  def SYNC_MM    : MMRel, SYNC_FT<"sync">, SYNC_FM_MM, ISA_MICROMIPS;
1014  let DecoderMethod = "DecodeSyncI_MM" in
1015    def SYNCI_MM   : MMRel, SYNCI_FT<"synci", mem_mm_16>, SYNCI_FM_MM,
1016                     ISA_MICROMIPS32_NOT_MIPS32R6;
1017  def BREAK_MM   : MMRel, BRK_FT<"break">, BRK_FM_MM, ISA_MICROMIPS;
1018  def SYSCALL_MM : MMRel, SYS_FT<"syscall", uimm10, II_SYSCALL>, SYS_FM_MM,
1019                   ISA_MICROMIPS;
1020  def WAIT_MM    : MMRel, WaitMM<"wait">, WAIT_FM_MM, ISA_MICROMIPS;
1021  def ERET_MM    : MMRel, ER_FT<"eret", II_ERET>, ER_FM_MM<0x3cd>,
1022                   ISA_MICROMIPS;
1023  def DERET_MM   : MMRel, ER_FT<"deret", II_DERET>, ER_FM_MM<0x38d>,
1024                   ISA_MICROMIPS;
1025  def EI_MM      : MMRel, DEI_FT<"ei", GPR32Opnd, II_EI>, EI_FM_MM<0x15d>,
1026                   ISA_MICROMIPS;
1027  def DI_MM      : MMRel, DEI_FT<"di", GPR32Opnd, II_DI>, EI_FM_MM<0x11d>,
1028                   ISA_MICROMIPS;
1029  def TRAP_MM    : TrapBase<BREAK_MM>, ISA_MICROMIPS;
1030
1031  /// Trap Instructions
1032  def TEQ_MM  : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm4, II_TEQ>, TEQ_FM_MM<0x0>,
1033                ISA_MICROMIPS;
1034  def TGE_MM  : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm4, II_TGE>, TEQ_FM_MM<0x08>,
1035                ISA_MICROMIPS;
1036  def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm4, II_TGEU>,
1037                TEQ_FM_MM<0x10>, ISA_MICROMIPS;
1038  def TLT_MM  : MMRel, TEQ_FT<"tlt", GPR32Opnd, uimm4, II_TLT>, TEQ_FM_MM<0x20>,
1039                ISA_MICROMIPS;
1040  def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm4, II_TLTU>,
1041                TEQ_FM_MM<0x28>, ISA_MICROMIPS;
1042  def TNE_MM  : MMRel, TEQ_FT<"tne", GPR32Opnd, uimm4, II_TNE>, TEQ_FM_MM<0x30>,
1043                ISA_MICROMIPS;
1044
1045  def TEQI_MM  : MMRel, TEQI_FT<"teqi", GPR32Opnd, II_TEQI>, TEQI_FM_MM<0x0e>,
1046                 ISA_MICROMIPS32_NOT_MIPS32R6;
1047  def TGEI_MM  : MMRel, TEQI_FT<"tgei", GPR32Opnd, II_TGEI>, TEQI_FM_MM<0x09>,
1048                 ISA_MICROMIPS32_NOT_MIPS32R6;
1049  def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd, II_TGEIU>,
1050                 TEQI_FM_MM<0x0b>, ISA_MICROMIPS32_NOT_MIPS32R6;
1051  def TLTI_MM  : MMRel, TEQI_FT<"tlti", GPR32Opnd, II_TLTI>, TEQI_FM_MM<0x08>,
1052                 ISA_MICROMIPS32_NOT_MIPS32R6;
1053  def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd, II_TTLTIU>,
1054                 TEQI_FM_MM<0x0a>, ISA_MICROMIPS32_NOT_MIPS32R6;
1055  def TNEI_MM  : MMRel, TEQI_FT<"tnei", GPR32Opnd, II_TNEI>, TEQI_FM_MM<0x0c>,
1056                 ISA_MICROMIPS32_NOT_MIPS32R6;
1057
1058  /// Load-linked, Store-conditional
1059  def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>,
1060              ISA_MICROMIPS32_NOT_MIPS32R6;
1061  def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>,
1062              ISA_MICROMIPS32_NOT_MIPS32R6;
1063
1064  def LLE_MM : MMRel, LLEBaseMM<"lle", GPR32Opnd>, LLE_FM_MM<0x6>,
1065               ISA_MICROMIPS, ASE_EVA;
1066  def SCE_MM : MMRel, SCEBaseMM<"sce", GPR32Opnd>, LLE_FM_MM<0xA>,
1067               ISA_MICROMIPS, ASE_EVA;
1068
1069  let DecoderMethod = "DecodeCacheOpMM" in {
1070    def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12, II_CACHE>,
1071                   CACHE_PREF_FM_MM<0x08, 0x6>, ISA_MICROMIPS32_NOT_MIPS32R6;
1072    def PREF_MM  : MMRel, CacheOp<"pref", mem_mm_12, II_PREF>,
1073                   CACHE_PREF_FM_MM<0x18, 0x2>, ISA_MICROMIPS32_NOT_MIPS32R6;
1074  }
1075
1076  let DecoderMethod = "DecodePrefeOpMM" in {
1077    def PREFE_MM  : MMRel, CacheOp<"prefe", mem_mm_9, II_PREFE>,
1078                    CACHE_PREFE_FM_MM<0x18, 0x2>, ISA_MICROMIPS, ASE_EVA;
1079    def CACHEE_MM : MMRel, CacheOp<"cachee", mem_mm_9, II_CACHEE>,
1080                    CACHE_PREFE_FM_MM<0x18, 0x3>, ISA_MICROMIPS, ASE_EVA;
1081  }
1082  def SSNOP_MM : MMRel, Barrier<"ssnop", II_SSNOP>, BARRIER_FM_MM<0x1>,
1083                 ISA_MICROMIPS;
1084  def EHB_MM   : MMRel, Barrier<"ehb", II_EHB>, BARRIER_FM_MM<0x3>,
1085                 ISA_MICROMIPS;
1086  def PAUSE_MM : MMRel, Barrier<"pause", II_PAUSE>, BARRIER_FM_MM<0x5>,
1087                 ISA_MICROMIPS;
1088
1089  def TLBP_MM : MMRel, TLB<"tlbp", II_TLBP>, COP0_TLB_FM_MM<0x0d>,
1090                ISA_MICROMIPS;
1091  def TLBR_MM : MMRel, TLB<"tlbr", II_TLBR>, COP0_TLB_FM_MM<0x4d>,
1092                ISA_MICROMIPS;
1093  def TLBWI_MM : MMRel, TLB<"tlbwi", II_TLBWI>, COP0_TLB_FM_MM<0x8d>,
1094                 ISA_MICROMIPS;
1095  def TLBWR_MM : MMRel, TLB<"tlbwr", II_TLBWR>, COP0_TLB_FM_MM<0xcd>,
1096                 ISA_MICROMIPS;
1097
1098  def SDBBP_MM : MMRel, SYS_FT<"sdbbp", uimm10, II_SDBBP>, SDBBP_FM_MM,
1099                 ISA_MICROMIPS;
1100
1101  def PREFX_MM : PrefetchIndexed<"prefx">, POOL32F_PREFX_FM_MM<0x15, 0x1A0>,
1102                 ISA_MICROMIPS32_NOT_MIPS32R6;
1103}
1104
1105let AdditionalPredicates = [NotDSP] in {
1106  def PseudoMULT_MM : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>,
1107                      ISA_MICROMIPS32_NOT_MIPS32R6;
1108  def PseudoMULTu_MM : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>,
1109                       ISA_MICROMIPS32_NOT_MIPS32R6;
1110  def PseudoMFHI_MM : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>,
1111                      ISA_MICROMIPS32_NOT_MIPS32R6;
1112  def PseudoMFLO_MM : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>,
1113                      ISA_MICROMIPS32_NOT_MIPS32R6;
1114  def PseudoMTLOHI_MM : PseudoMTLOHI<ACC64, GPR32>,
1115                        ISA_MICROMIPS32_NOT_MIPS32R6;
1116  def PseudoMADD_MM : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
1117                      ISA_MICROMIPS32_NOT_MIPS32R6;
1118  def PseudoMADDU_MM : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>,
1119                       ISA_MICROMIPS32_NOT_MIPS32R6;
1120  def PseudoMSUB_MM : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,
1121                      ISA_MICROMIPS32_NOT_MIPS32R6;
1122  def PseudoMSUBU_MM : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,
1123                       ISA_MICROMIPS32_NOT_MIPS32R6;
1124}
1125
1126def TAILCALL_MM : TailCall<J_MM, jmptarget_mm>,
1127                  ISA_MICROMIPS32_NOT_MIPS32R6;
1128
1129def TAILCALLREG_MM  : TailCallReg<JRC16_MM, GPR32Opnd>,
1130                      ISA_MICROMIPS32_NOT_MIPS32R6;
1131
1132def PseudoIndirectBranch_MM : PseudoIndirectBranchBase<JR_MM, GPR32Opnd>,
1133                              ISA_MICROMIPS32_NOT_MIPS32R6;
1134
1135let DecoderNamespace = "MicroMips" in {
1136  def RDHWR_MM : MMRel, R6MMR6Rel, ReadHardware<GPR32Opnd, HWRegsOpnd>,
1137                 RDHWR_FM_MM, ISA_MICROMIPS32_NOT_MIPS32R6;
1138  def LWU_MM : MMRel, LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU,
1139                             mem_simm12>, LL_FM_MM<0xe>,
1140               ISA_MICROMIPS32_NOT_MIPS32R6;
1141
1142  def MFGC0_MM    : MMRel, MfCop0MM<"mfgc0", GPR32Opnd, COP0Opnd, II_MFGC0>,
1143                    POOL32A_MFTC0_FM_MM<0b10011, 0b111100>,
1144                    ISA_MICROMIPS32R5, ASE_VIRT;
1145  def MFHGC0_MM   : MMRel, MfCop0MM<"mfhgc0", GPR32Opnd, COP0Opnd, II_MFHGC0>,
1146                    POOL32A_MFTC0_FM_MM<0b10011, 0b110100>,
1147                    ISA_MICROMIPS32R5, ASE_VIRT;
1148  def MTGC0_MM    : MMRel, MtCop0MM<"mtgc0", COP0Opnd, GPR32Opnd, II_MTGC0>,
1149                    POOL32A_MFTC0_FM_MM<0b11011, 0b111100>,
1150                    ISA_MICROMIPS32R5, ASE_VIRT;
1151  def MTHGC0_MM   : MMRel, MtCop0MM<"mthgc0", COP0Opnd, GPR32Opnd, II_MTHGC0>,
1152                    POOL32A_MFTC0_FM_MM<0b11011, 0b110100>,
1153                    ISA_MICROMIPS32R5, ASE_VIRT;
1154  def HYPCALL_MM  : MMRel, HypcallMM<"hypcall">, POOL32A_HYPCALL_FM_MM,
1155                    ISA_MICROMIPS32R5, ASE_VIRT;
1156  def TLBGINV_MM  : MMRel, TLBINVMM<"tlbginv", II_TLBGINV>,
1157                    POOL32A_TLBINV_FM_MM<0x105>, ISA_MICROMIPS32R5, ASE_VIRT;
1158  def TLBGINVF_MM : MMRel, TLBINVMM<"tlbginvf", II_TLBGINVF>,
1159                    POOL32A_TLBINV_FM_MM<0x145>, ISA_MICROMIPS32R5, ASE_VIRT;
1160  def TLBGP_MM    : MMRel, TLBINVMM<"tlbgp", II_TLBGP>,
1161                    POOL32A_TLBINV_FM_MM<0x5>, ISA_MICROMIPS32R5, ASE_VIRT;
1162  def TLBGR_MM    : MMRel, TLBINVMM<"tlbgr", II_TLBGR>,
1163                    POOL32A_TLBINV_FM_MM<0x45>, ISA_MICROMIPS32R5, ASE_VIRT;
1164  def TLBGWI_MM   : MMRel, TLBINVMM<"tlbgwi", II_TLBGWI>,
1165                    POOL32A_TLBINV_FM_MM<0x85>, ISA_MICROMIPS32R5, ASE_VIRT;
1166  def TLBGWR_MM   : MMRel, TLBINVMM<"tlbgwr", II_TLBGWR>,
1167                    POOL32A_TLBINV_FM_MM<0xc5>, ISA_MICROMIPS32R5, ASE_VIRT;
1168}
1169
1170//===----------------------------------------------------------------------===//
1171// MicroMips arbitrary patterns that map to one or more instructions
1172//===----------------------------------------------------------------------===//
1173
1174defm : MipsHiLoRelocs<LUi_MM, ADDiu_MM, ZERO, GPR32Opnd>, ISA_MICROMIPS;
1175
1176def : MipsPat<(MipsGotHi tglobaladdr:$in), (LUi_MM tglobaladdr:$in)>,
1177      ISA_MICROMIPS;
1178def : MipsPat<(MipsGotHi texternalsym:$in), (LUi_MM texternalsym:$in)>,
1179      ISA_MICROMIPS;
1180
1181def : MipsPat<(MipsTlsHi tglobaltlsaddr:$in), (LUi_MM tglobaltlsaddr:$in)>,
1182      ISA_MICROMIPS;
1183
1184// gp_rel relocs
1185def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1186              (ADDiu_MM GPR32:$gp, tglobaladdr:$in)>, ISA_MICROMIPS;
1187def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1188              (ADDiu_MM GPR32:$gp, tconstpool:$in)>, ISA_MICROMIPS;
1189
1190def : WrapperPat<tglobaladdr, ADDiu_MM, GPR32>, ISA_MICROMIPS;
1191def : WrapperPat<tconstpool, ADDiu_MM, GPR32>, ISA_MICROMIPS;
1192def : WrapperPat<texternalsym, ADDiu_MM, GPR32>, ISA_MICROMIPS;
1193def : WrapperPat<tblockaddress, ADDiu_MM, GPR32>, ISA_MICROMIPS;
1194def : WrapperPat<tjumptable, ADDiu_MM, GPR32>, ISA_MICROMIPS;
1195def : WrapperPat<tglobaltlsaddr, ADDiu_MM, GPR32>, ISA_MICROMIPS;
1196
1197def : MipsPat<(atomic_load_8 addr:$a), (LB_MM addr:$a)>, ISA_MICROMIPS;
1198def : MipsPat<(atomic_load_16 addr:$a), (LH_MM addr:$a)>, ISA_MICROMIPS;
1199def : MipsPat<(atomic_load_32 addr:$a), (LW_MM addr:$a)>, ISA_MICROMIPS;
1200
1201def : MipsPat<(i32 immLi16:$imm),
1202              (LI16_MM immLi16:$imm)>, ISA_MICROMIPS;
1203
1204defm : MaterializeImms<i32, ZERO, ADDiu_MM, LUi_MM, ORi_MM>, ISA_MICROMIPS;
1205
1206def : MipsPat<(not GPRMM16:$in),
1207              (NOT16_MM GPRMM16:$in)>, ISA_MICROMIPS;
1208def : MipsPat<(not GPR32:$in),
1209              (NOR_MM GPR32Opnd:$in, ZERO)>, ISA_MICROMIPS;
1210
1211def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm),
1212              (ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>, ISA_MICROMIPS;
1213def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm),
1214              (ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>, ISA_MICROMIPS;
1215def : MipsPat<(add GPR32:$src, immSExt16:$imm),
1216              (ADDiu_MM GPR32:$src, immSExt16:$imm)>, ISA_MICROMIPS;
1217
1218def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
1219              (ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>, ISA_MICROMIPS;
1220def : MipsPat<(and GPR32:$src, immZExt16:$imm),
1221              (ANDi_MM GPR32:$src, immZExt16:$imm)>, ISA_MICROMIPS;
1222
1223def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm),
1224              (SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>, ISA_MICROMIPS;
1225def : MipsPat<(shl GPR32:$src, immZExt5:$imm),
1226              (SLL_MM GPR32:$src, immZExt5:$imm)>, ISA_MICROMIPS;
1227def : MipsPat<(shl GPR32:$lhs, GPR32:$rhs),
1228              (SLLV_MM GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS;
1229
1230def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm),
1231              (SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>, ISA_MICROMIPS;
1232def : MipsPat<(srl GPR32:$src, immZExt5:$imm),
1233              (SRL_MM GPR32:$src, immZExt5:$imm)>, ISA_MICROMIPS;
1234def : MipsPat<(srl GPR32:$lhs, GPR32:$rhs),
1235              (SRLV_MM GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS;
1236
1237def : MipsPat<(sra GPR32:$src, immZExt5:$imm),
1238              (SRA_MM GPR32:$src, immZExt5:$imm)>, ISA_MICROMIPS;
1239def : MipsPat<(sra GPR32:$lhs, GPR32:$rhs),
1240              (SRAV_MM GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS;
1241
1242def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
1243              (SW16_MM GPRMM16:$src, addrimm4lsl2:$addr)>, ISA_MICROMIPS;
1244def : MipsPat<(store GPR32:$src, addr:$addr),
1245              (SW_MM GPR32:$src, addr:$addr)>, ISA_MICROMIPS;
1246
1247def : MipsPat<(load addrimm4lsl2:$addr),
1248              (LW16_MM addrimm4lsl2:$addr)>, ISA_MICROMIPS;
1249def : MipsPat<(load addr:$addr),
1250              (LW_MM addr:$addr)>, ISA_MICROMIPS;
1251def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1252              (SUBu_MM GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS;
1253
1254def : MipsPat<(i32 (extloadi1  addr:$src)), (LBu_MM addr:$src)>,
1255      ISA_MICROMIPS;
1256
1257def : MipsPat<(i32 (extloadi8  addr:$src)), (LBu_MM addr:$src)>,
1258      ISA_MICROMIPS;
1259
1260def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_MM addr:$src)>,
1261      ISA_MICROMIPS;
1262
1263let AddedComplexity = 40 in
1264  def : MipsPat<(i32 (sextloadi16 addrRegImm:$a)),
1265                (LH_MM addrRegImm:$a)>, ISA_MICROMIPS;
1266
1267
1268def : MipsPat<(bswap GPR32:$rt), (ROTR_MM (WSBH_MM GPR32:$rt), 16)>,
1269      ISA_MICROMIPS;
1270
1271def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1272              (JAL_MM texternalsym:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;
1273def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1274              (TAILCALL_MM tglobaladdr:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;
1275def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1276              (TAILCALL_MM texternalsym:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;
1277
1278defm : BrcondPats<GPR32, BEQ_MM, BEQ_MM, BNE_MM, SLT_MM, SLTu_MM, SLTi_MM,
1279                  SLTiu_MM, ZERO>, ISA_MICROMIPS32_NOT_MIPS32R6;
1280
1281def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1282              (BLEZ_MM i32:$lhs, bb:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;
1283def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1284              (BGEZ_MM i32:$lhs, bb:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;
1285
1286defm : SeteqPats<GPR32, SLTiu_MM, XOR_MM, SLTu_MM, ZERO>, ISA_MICROMIPS;
1287defm : SetlePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>, ISA_MICROMIPS;
1288defm : SetgtPats<GPR32, SLT_MM, SLTu_MM>, ISA_MICROMIPS;
1289defm : SetgePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>, ISA_MICROMIPS;
1290defm : SetgeImmPats<GPR32, XORi_MM, SLTi_MM, SLTiu_MM>, ISA_MICROMIPS;
1291
1292// Select patterns
1293
1294// Instantiation of conditional move patterns.
1295defm : MovzPats0<GPR32, GPR32, MOVZ_I_MM, SLT_MM, SLTu_MM, SLTi_MM, SLTiu_MM>,
1296       ISA_MICROMIPS32_NOT_MIPS32R6;
1297defm : MovzPats1<GPR32, GPR32, MOVZ_I_MM, XOR_MM>,
1298       ISA_MICROMIPS32_NOT_MIPS32R6;
1299defm : MovzPats2<GPR32, GPR32, MOVZ_I_MM, XORi_MM>,
1300       ISA_MICROMIPS32_NOT_MIPS32R6;
1301
1302
1303defm : MovnPats<GPR32, GPR32, MOVN_I_MM, XOR_MM>, INSN_MIPS4_32_NOT_32R6_64R6;
1304
1305// Instantiation of conditional move patterns.
1306defm : MovzPats0<GPR32, GPR32, MOVZ_I_MM, SLT_MM, SLTu_MM, SLTi_MM, SLTiu_MM>,
1307       ISA_MICROMIPS32_NOT_MIPS32R6;
1308defm : MovzPats1<GPR32, GPR32, MOVZ_I_MM, XOR_MM>,
1309       ISA_MICROMIPS32_NOT_MIPS32R6;
1310defm : MovzPats2<GPR32, GPR32, MOVZ_I_MM, XORi_MM>,
1311       ISA_MICROMIPS32_NOT_MIPS32R6;
1312
1313defm : MovnPats<GPR32, GPR32, MOVN_I_MM, XOR_MM>, ISA_MICROMIPS32_NOT_MIPS32R6;
1314
1315//===----------------------------------------------------------------------===//
1316// MicroMips instruction aliases
1317//===----------------------------------------------------------------------===//
1318
1319class UncondBranchMMPseudo<string opstr> :
1320  MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
1321                    !strconcat(opstr, "\t$offset")>;
1322
1323def B_MM_Pseudo : UncondBranchMMPseudo<"b">, ISA_MICROMIPS;
1324
1325let EncodingPredicates = [InMicroMips] in {
1326  def SDIV_MM_Pseudo : MultDivPseudo<SDIV_MM, ACC64, GPR32Opnd, MipsDivRem,
1327                                     II_DIV, 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1328  def UDIV_MM_Pseudo : MultDivPseudo<UDIV_MM, ACC64, GPR32Opnd, MipsDivRemU,
1329                                     II_DIVU, 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1330
1331  def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>, ISA_MICROMIPS;
1332  def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>, ISA_MICROMIPS;
1333  def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>, ISA_MICROMIPS;
1334  def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MICROMIPS;
1335  def : MipsInstAlias<"di", (DI_MM ZERO), 1>, ISA_MICROMIPS;
1336  def : MipsInstAlias<"neg $rt, $rs",
1337                      (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>,
1338        ISA_MICROMIPS32_NOT_MIPS32R6;
1339  def : MipsInstAlias<"neg $rt",
1340                      (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>,
1341        ISA_MICROMIPS32_NOT_MIPS32R6;
1342  def : MipsInstAlias<"negu $rt, $rs",
1343                      (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>,
1344        ISA_MICROMIPS32_NOT_MIPS32R6;
1345  def : MipsInstAlias<"negu $rt",
1346                      (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>,
1347        ISA_MICROMIPS32_NOT_MIPS32R6;
1348  def : MipsInstAlias<"teq $rs, $rt",
1349                      (TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1350  def : MipsInstAlias<"tge $rs, $rt",
1351                      (TGE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1352  def : MipsInstAlias<"tgeu $rs, $rt",
1353                      (TGEU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1354  def : MipsInstAlias<"tlt $rs, $rt",
1355                      (TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1356  def : MipsInstAlias<"tltu $rs, $rt",
1357                      (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1358  def : MipsInstAlias<"tne $rs, $rt",
1359                      (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1360  def : MipsInstAlias<
1361          "sgt $rd, $rs, $rt",
1362          (SLT_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1363  def : MipsInstAlias<
1364          "sgt $rs, $rt",
1365          (SLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1366  def : MipsInstAlias<
1367          "sgtu $rd, $rs, $rt",
1368          (SLTu_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1369  def : MipsInstAlias<
1370          "sgtu $rs, $rt",
1371          (SLTu_MM GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1372  def : MipsInstAlias<"sll $rd, $rt, $rs",
1373                      (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1374  def : MipsInstAlias<"sra $rd, $rt, $rs",
1375                      (SRAV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1376  def : MipsInstAlias<"srl $rd, $rt, $rs",
1377                      (SRLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1378  def : MipsInstAlias<"sll $rd, $rt",
1379                      (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
1380  def : MipsInstAlias<"sra $rd, $rt",
1381                      (SRAV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
1382  def : MipsInstAlias<"srl $rd, $rt",
1383                      (SRLV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
1384  def : MipsInstAlias<"sll $rd, $shamt",
1385                      (SLL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
1386  def : MipsInstAlias<"sra $rd, $shamt",
1387                      (SRA_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
1388  def : MipsInstAlias<"srl $rd, $shamt",
1389                      (SRL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
1390  def : MipsInstAlias<"rotr $rt, $imm",
1391                      (ROTR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, uimm5:$imm), 0>;
1392  def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>, ISA_MICROMIPS;
1393
1394  def : MipsInstAlias<"sync", (SYNC_MM 0), 1>, ISA_MICROMIPS;
1395
1396  defm : OneOrTwoOperandMacroImmediateAlias<"add", ADDi_MM>, ISA_MICROMIPS;
1397
1398  defm : OneOrTwoOperandMacroImmediateAlias<"addu", ADDiu_MM>, ISA_MICROMIPS;
1399
1400  defm : OneOrTwoOperandMacroImmediateAlias<"and", ANDi_MM>, ISA_MICROMIPS;
1401
1402  defm : OneOrTwoOperandMacroImmediateAlias<"or", ORi_MM>, ISA_MICROMIPS;
1403
1404  defm : OneOrTwoOperandMacroImmediateAlias<"xor", XORi_MM>, ISA_MICROMIPS;
1405
1406  defm : OneOrTwoOperandMacroImmediateAlias<"slt", SLTi_MM>, ISA_MICROMIPS;
1407
1408  defm : OneOrTwoOperandMacroImmediateAlias<"sltu", SLTiu_MM>, ISA_MICROMIPS;
1409
1410  def : MipsInstAlias<"not $rt, $rs",
1411                      (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>,
1412        ISA_MICROMIPS32_NOT_MIPS32R6;
1413  def : MipsInstAlias<"not $rt",
1414                      (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>,
1415        ISA_MICROMIPS32_NOT_MIPS32R6;
1416  def : MipsInstAlias<"bnez $rs,$offset",
1417                      (BNE_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>,
1418        ISA_MICROMIPS;
1419  def : MipsInstAlias<"beqz $rs,$offset",
1420                      (BEQ_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>,
1421        ISA_MICROMIPS;
1422  def : MipsInstAlias<"seh $rd", (SEH_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
1423                     ISA_MICROMIPS;
1424  def : MipsInstAlias<"seb $rd", (SEB_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
1425                     ISA_MICROMIPS;
1426  def : MipsInstAlias<"break", (BREAK_MM 0, 0), 1>, ISA_MICROMIPS;
1427  def : MipsInstAlias<"break $imm", (BREAK_MM uimm10:$imm, 0), 1>,
1428        ISA_MICROMIPS;
1429  def : MipsInstAlias<"bal $offset", (BGEZAL_MM ZERO, brtarget_mm:$offset), 1>,
1430        ISA_MICROMIPS32_NOT_MIPS32R6;
1431
1432  def : MipsInstAlias<"j $rs", (JR_MM GPR32Opnd:$rs), 0>,
1433        ISA_MICROMIPS32_NOT_MIPS32R6;
1434}
1435def : MipsInstAlias<"rdhwr $rt, $rs",
1436                    (RDHWR_MM GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>,
1437      ISA_MICROMIPS32_NOT_MIPS32R6;
1438
1439def : MipsInstAlias<"hypcall", (HYPCALL_MM 0), 1>,
1440                    ISA_MICROMIPS32R5, ASE_VIRT;
1441def : MipsInstAlias<"mfgc0 $rt, $rs",
1442                    (MFGC0_MM GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,
1443                    ISA_MICROMIPS32R5, ASE_VIRT;
1444def : MipsInstAlias<"mfhgc0 $rt, $rs",
1445                    (MFHGC0_MM GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,
1446                    ISA_MICROMIPS32R5, ASE_VIRT;
1447def : MipsInstAlias<"mtgc0 $rt, $rs",
1448                    (MTGC0_MM COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
1449                    ISA_MICROMIPS32R5, ASE_VIRT;
1450def : MipsInstAlias<"mthgc0 $rt, $rs",
1451                    (MTHGC0_MM COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
1452                    ISA_MICROMIPS32R5, ASE_VIRT;
1453def : MipsInstAlias<"sw $rt, $offset",
1454                    (SWSP_MM GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset), 1>,
1455                    ISA_MICROMIPS;
1456