1//===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes Mips DSP ASE instructions.
10//
11//===----------------------------------------------------------------------===//
12
13// ImmLeaf
14def immZExt1 : ImmLeaf<i32, [{return isUInt<1>(Imm);}]>;
15def timmZExt1 : ImmLeaf<i32, [{return isUInt<1>(Imm);}], NOOP_SDNodeXForm, timm>;
16def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>;
17def timmZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}], NOOP_SDNodeXForm, timm>;
18def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>;
19def timmZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}], NOOP_SDNodeXForm, timm>;
20def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;
21def timmZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}], NOOP_SDNodeXForm, timm>;
22def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;
23def timmZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}], NOOP_SDNodeXForm, timm>;
24def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;
25def timmZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}], NOOP_SDNodeXForm, timm>;
26def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;
27def timmSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}], NOOP_SDNodeXForm, timm>;
28def immSExt10 : ImmLeaf<i32, [{return isInt<10>(Imm);}]>;
29
30// Mips-specific dsp nodes
31def SDT_MipsExtr : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
32                                        SDTCisVT<2, untyped>]>;
33def SDT_MipsShilo : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
34                                         SDTCisSameAs<0, 2>, SDTCisVT<1, i32>]>;
35def SDT_MipsDPA : SDTypeProfile<1, 3, [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
36                                       SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
37def SDT_MipsSHIFT_DSP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
38                                             SDTCisVT<2, i32>]>;
39
40class MipsDSPBase<string Opc, SDTypeProfile Prof> :
41  SDNode<!strconcat("MipsISD::", Opc), Prof>;
42
43class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> :
44  SDNode<!strconcat("MipsISD::", Opc), Prof, [SDNPHasChain, SDNPSideEffect]>;
45
46def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>;
47def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>;
48def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>;
49def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>;
50def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>;
51def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>;
52
53def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>;
54def MipsMTHLIP : MipsDSPSideEffectBase<"MTHLIP", SDT_MipsShilo>;
55
56def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>;
57def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>;
58def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>;
59def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>;
60def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>;
61
62def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>;
63def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>;
64def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>;
65def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>;
66def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>;
67def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>;
68def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>;
69def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>;
70
71def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>;
72def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>;
73def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>;
74def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>;
75def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>;
76def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>;
77def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>;
78def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>;
79def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>;
80
81def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>;
82def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>;
83def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>;
84def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>;
85def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>;
86def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>;
87def MipsSHLL_DSP : MipsDSPBase<"SHLL_DSP", SDT_MipsSHIFT_DSP>;
88def MipsSHRA_DSP : MipsDSPBase<"SHRA_DSP", SDT_MipsSHIFT_DSP>;
89def MipsSHRL_DSP : MipsDSPBase<"SHRL_DSP", SDT_MipsSHIFT_DSP>;
90def MipsSETCC_DSP : MipsDSPBase<"SETCC_DSP", SDTSetCC>;
91def MipsSELECT_CC_DSP : MipsDSPBase<"SELECT_CC_DSP", SDTSelectCC>;
92
93// Flags.
94class Uses<list<Register> Regs> {
95  list<Register> Uses = Regs;
96}
97
98class Defs<list<Register> Regs> {
99  list<Register> Defs = Regs;
100}
101
102// Instruction encoding.
103class ADDU_QB_ENC : ADDU_QB_FMT<0b00000>;
104class ADDU_S_QB_ENC : ADDU_QB_FMT<0b00100>;
105class SUBU_QB_ENC : ADDU_QB_FMT<0b00001>;
106class SUBU_S_QB_ENC : ADDU_QB_FMT<0b00101>;
107class ADDQ_PH_ENC : ADDU_QB_FMT<0b01010>;
108class ADDQ_S_PH_ENC : ADDU_QB_FMT<0b01110>;
109class SUBQ_PH_ENC : ADDU_QB_FMT<0b01011>;
110class SUBQ_S_PH_ENC : ADDU_QB_FMT<0b01111>;
111class ADDQ_S_W_ENC : ADDU_QB_FMT<0b10110>;
112class SUBQ_S_W_ENC : ADDU_QB_FMT<0b10111>;
113class ADDSC_ENC : ADDU_QB_FMT<0b10000>;
114class ADDWC_ENC : ADDU_QB_FMT<0b10001>;
115class MODSUB_ENC : ADDU_QB_FMT<0b10010>;
116class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>;
117class ABSQ_S_PH_ENC : ABSQ_S_PH_R2_FMT<0b01001>;
118class ABSQ_S_W_ENC : ABSQ_S_PH_R2_FMT<0b10001>;
119class PRECRQ_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01100>;
120class PRECRQ_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10100>;
121class PRECRQ_RS_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10101>;
122class PRECRQU_S_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01111>;
123class PRECEQ_W_PHL_ENC : ABSQ_S_PH_R2_FMT<0b01100>;
124class PRECEQ_W_PHR_ENC : ABSQ_S_PH_R2_FMT<0b01101>;
125class PRECEQU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b00100>;
126class PRECEQU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b00101>;
127class PRECEQU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b00110>;
128class PRECEQU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b00111>;
129class PRECEU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b11100>;
130class PRECEU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b11101>;
131class PRECEU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b11110>;
132class PRECEU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b11111>;
133class SHLL_QB_ENC : SHLL_QB_FMT<0b00000>;
134class SHLLV_QB_ENC : SHLL_QB_FMT<0b00010>;
135class SHRL_QB_ENC : SHLL_QB_FMT<0b00001>;
136class SHRLV_QB_ENC : SHLL_QB_FMT<0b00011>;
137class SHLL_PH_ENC : SHLL_QB_FMT<0b01000>;
138class SHLLV_PH_ENC : SHLL_QB_FMT<0b01010>;
139class SHLL_S_PH_ENC : SHLL_QB_FMT<0b01100>;
140class SHLLV_S_PH_ENC : SHLL_QB_FMT<0b01110>;
141class SHRA_PH_ENC : SHLL_QB_FMT<0b01001>;
142class SHRAV_PH_ENC : SHLL_QB_FMT<0b01011>;
143class SHRA_R_PH_ENC : SHLL_QB_FMT<0b01101>;
144class SHRAV_R_PH_ENC : SHLL_QB_FMT<0b01111>;
145class SHLL_S_W_ENC : SHLL_QB_FMT<0b10100>;
146class SHLLV_S_W_ENC : SHLL_QB_FMT<0b10110>;
147class SHRA_R_W_ENC : SHLL_QB_FMT<0b10101>;
148class SHRAV_R_W_ENC : SHLL_QB_FMT<0b10111>;
149class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>;
150class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>;
151class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>;
152class MULEQ_S_W_PHR_ENC : ADDU_QB_FMT<0b11101>;
153class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>;
154class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>;
155class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>;
156class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>;
157class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>;
158class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>;
159class MFHI_ENC : MFHI_FMT<0b010000>;
160class MFLO_ENC : MFHI_FMT<0b010010>;
161class MTHI_ENC : MTHI_FMT<0b010001>;
162class MTLO_ENC : MTHI_FMT<0b010011>;
163class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>;
164class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>;
165class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>;
166class DPSU_H_QBR_ENC : DPA_W_PH_FMT<0b01111>;
167class DPAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00100>;
168class DPSQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00101>;
169class DPAQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01100>;
170class DPSQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01101>;
171class MULT_DSP_ENC : MULT_FMT<0b000000, 0b011000>;
172class MULTU_DSP_ENC : MULT_FMT<0b000000, 0b011001>;
173class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>;
174class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>;
175class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>;
176class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>;
177class CMPU_EQ_QB_ENC : CMP_EQ_QB_R2_FMT<0b00000>;
178class CMPU_LT_QB_ENC : CMP_EQ_QB_R2_FMT<0b00001>;
179class CMPU_LE_QB_ENC : CMP_EQ_QB_R2_FMT<0b00010>;
180class CMPGU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b00100>;
181class CMPGU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b00101>;
182class CMPGU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b00110>;
183class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>;
184class CMP_LT_PH_ENC : CMP_EQ_QB_R2_FMT<0b01001>;
185class CMP_LE_PH_ENC : CMP_EQ_QB_R2_FMT<0b01010>;
186class BITREV_ENC : ABSQ_S_PH_R2_FMT<0b11011>;
187class PACKRL_PH_ENC : CMP_EQ_QB_R3_FMT<0b01110>;
188class REPL_QB_ENC : REPL_FMT<0b00010>;
189class REPL_PH_ENC : REPL_FMT<0b01010>;
190class REPLV_QB_ENC : ABSQ_S_PH_R2_FMT<0b00011>;
191class REPLV_PH_ENC : ABSQ_S_PH_R2_FMT<0b01011>;
192class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>;
193class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>;
194class LWX_ENC : LX_FMT<0b00000>;
195class LHX_ENC : LX_FMT<0b00100>;
196class LBUX_ENC : LX_FMT<0b00110>;
197class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>;
198class INSV_ENC : INSV_FMT<0b001100>;
199
200class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>;
201class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>;
202class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>;
203class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>;
204class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>;
205class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>;
206class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>;
207class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>;
208class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>;
209class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>;
210class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>;
211class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>;
212class SHILO_ENC : SHILO_R1_FMT<0b11010>;
213class SHILOV_ENC : SHILO_R2_FMT<0b11011>;
214class MTHLIP_ENC : SHILO_R2_FMT<0b11111>;
215
216class RDDSP_ENC : RDDSP_FMT<0b10010>;
217class WRDSP_ENC : WRDSP_FMT<0b10011>;
218class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>;
219class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>;
220class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>;
221class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>;
222class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>;
223class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>;
224class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>;
225class ABSQ_S_QB_ENC : ABSQ_S_PH_R2_FMT<0b00001>;
226class ADDUH_QB_ENC : ADDUH_QB_FMT<0b00000>;
227class ADDUH_R_QB_ENC : ADDUH_QB_FMT<0b00010>;
228class SUBUH_QB_ENC : ADDUH_QB_FMT<0b00001>;
229class SUBUH_R_QB_ENC : ADDUH_QB_FMT<0b00011>;
230class ADDQH_PH_ENC : ADDUH_QB_FMT<0b01000>;
231class ADDQH_R_PH_ENC : ADDUH_QB_FMT<0b01010>;
232class SUBQH_PH_ENC : ADDUH_QB_FMT<0b01001>;
233class SUBQH_R_PH_ENC : ADDUH_QB_FMT<0b01011>;
234class ADDQH_W_ENC : ADDUH_QB_FMT<0b10000>;
235class ADDQH_R_W_ENC : ADDUH_QB_FMT<0b10010>;
236class SUBQH_W_ENC : ADDUH_QB_FMT<0b10001>;
237class SUBQH_R_W_ENC : ADDUH_QB_FMT<0b10011>;
238class MUL_PH_ENC : ADDUH_QB_FMT<0b01100>;
239class MUL_S_PH_ENC : ADDUH_QB_FMT<0b01110>;
240class MULQ_S_W_ENC : ADDUH_QB_FMT<0b10110>;
241class MULQ_RS_W_ENC : ADDUH_QB_FMT<0b10111>;
242class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>;
243class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>;
244class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>;
245class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>;
246class DPAQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11010>;
247class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>;
248class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>;
249class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>;
250class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>;
251class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>;
252class PRECR_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01101>;
253class PRECR_SRA_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11110>;
254class PRECR_SRA_R_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11111>;
255class SHRA_QB_ENC : SHLL_QB_FMT<0b00100>;
256class SHRAV_QB_ENC : SHLL_QB_FMT<0b00110>;
257class SHRA_R_QB_ENC : SHLL_QB_FMT<0b00101>;
258class SHRAV_R_QB_ENC : SHLL_QB_FMT<0b00111>;
259class SHRL_PH_ENC : SHLL_QB_FMT<0b11001>;
260class SHRLV_PH_ENC : SHLL_QB_FMT<0b11011>;
261class APPEND_ENC : APPEND_FMT<0b00000>;
262class BALIGN_ENC : APPEND_FMT<0b10000>;
263class PREPEND_ENC : APPEND_FMT<0b00001>;
264
265// Instruction desc.
266class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
267                        InstrItinClass itin, RegisterOperand ROD,
268                        RegisterOperand ROS,  RegisterOperand ROT = ROS> {
269  dag OutOperandList = (outs ROD:$rd);
270  dag InOperandList = (ins ROS:$rs, ROT:$rt);
271  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
272  list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
273  InstrItinClass Itinerary = itin;
274  string BaseOpcode = instr_asm;
275}
276
277class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
278                           InstrItinClass itin, RegisterOperand ROD,
279                           RegisterOperand ROS = ROD> {
280  dag OutOperandList = (outs ROD:$rd);
281  dag InOperandList = (ins ROS:$rs);
282  string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
283  list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];
284  InstrItinClass Itinerary = itin;
285  string BaseOpcode = instr_asm;
286}
287
288class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
289                             InstrItinClass itin, RegisterOperand ROS,
290                             RegisterOperand ROT = ROS> {
291  dag OutOperandList = (outs);
292  dag InOperandList = (ins ROS:$rs, ROT:$rt);
293  string AsmString = !strconcat(instr_asm, "\t$rs, $rt");
294  list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
295  InstrItinClass Itinerary = itin;
296  string BaseOpcode = instr_asm;
297}
298
299class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
300                             InstrItinClass itin, RegisterOperand ROD,
301                             RegisterOperand ROS,  RegisterOperand ROT = ROS> {
302  dag OutOperandList = (outs ROD:$rd);
303  dag InOperandList = (ins ROS:$rs, ROT:$rt);
304  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
305  list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
306  InstrItinClass Itinerary = itin;
307  string BaseOpcode = instr_asm;
308}
309
310class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
311                               InstrItinClass itin, RegisterOperand ROT,
312                               RegisterOperand ROS = ROT> {
313  dag OutOperandList = (outs ROT:$rt);
314  dag InOperandList = (ins ROS:$rs, uimm5:$sa, ROS:$src);
315  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
316  list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, timmZExt5:$sa))];
317  InstrItinClass Itinerary = itin;
318  string Constraints = "$src = $rt";
319  string BaseOpcode = instr_asm;
320}
321
322class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
323                             InstrItinClass itin, RegisterOperand ROD,
324                             RegisterOperand ROT = ROD> {
325  dag OutOperandList = (outs ROD:$rd);
326  dag InOperandList = (ins ROT:$rt);
327  string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
328  list<dag> Pattern = [(set ROD:$rd, (OpNode ROT:$rt))];
329  InstrItinClass Itinerary = itin;
330  string BaseOpcode = instr_asm;
331}
332
333class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
334                     Operand ImmOp, ImmLeaf immPat, InstrItinClass itin,
335                     RegisterOperand RO> {
336  dag OutOperandList = (outs RO:$rd);
337  dag InOperandList = (ins ImmOp:$imm);
338  string AsmString = !strconcat(instr_asm, "\t$rd, $imm");
339  list<dag> Pattern = [(set RO:$rd, (OpNode immPat:$imm))];
340  InstrItinClass Itinerary = itin;
341  string BaseOpcode = instr_asm;
342}
343
344class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
345                           InstrItinClass itin, RegisterOperand RO> {
346  dag OutOperandList = (outs RO:$rd);
347  dag InOperandList =  (ins RO:$rt, GPR32Opnd:$rs_sa);
348  string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
349  list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs_sa))];
350  InstrItinClass Itinerary = itin;
351  string BaseOpcode = instr_asm;
352}
353
354class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
355                           SDPatternOperator ImmPat, InstrItinClass itin,
356                           RegisterOperand RO, Operand ImmOpnd> {
357  dag OutOperandList = (outs RO:$rd);
358  dag InOperandList = (ins RO:$rt, ImmOpnd:$rs_sa);
359  string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
360  list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, ImmPat:$rs_sa))];
361  InstrItinClass Itinerary = itin;
362  bit hasSideEffects = 1;
363  string BaseOpcode = instr_asm;
364}
365
366class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
367                   InstrItinClass itin> {
368  dag OutOperandList = (outs GPR32Opnd:$rd);
369  dag InOperandList = (ins PtrRC:$base, PtrRC:$index);
370  string AsmString = !strconcat(instr_asm, "\t$rd, ${index}(${base})");
371  list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode iPTR:$base, iPTR:$index))];
372  InstrItinClass Itinerary = itin;
373  bit mayLoad = 1;
374  string BaseOpcode = instr_asm;
375}
376
377class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
378                         InstrItinClass itin, RegisterOperand ROD,
379                         RegisterOperand ROS = ROD, RegisterOperand ROT = ROD> {
380  dag OutOperandList = (outs ROD:$rd);
381  dag InOperandList = (ins ROS:$rs, ROT:$rt);
382  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
383  list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
384  InstrItinClass Itinerary = itin;
385  string BaseOpcode = instr_asm;
386}
387
388class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
389                       Operand ImmOp, SDPatternOperator Imm,
390                       InstrItinClass itin> {
391  dag OutOperandList = (outs GPR32Opnd:$rt);
392  dag InOperandList = (ins GPR32Opnd:$rs, ImmOp:$sa, GPR32Opnd:$src);
393  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
394  list<dag> Pattern =  [(set GPR32Opnd:$rt,
395                        (OpNode GPR32Opnd:$src, GPR32Opnd:$rs, Imm:$sa))];
396  InstrItinClass Itinerary = itin;
397  string Constraints = "$src = $rt";
398  string BaseOpcode = instr_asm;
399}
400
401class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, InstrItinClass itin> {
402  dag OutOperandList = (outs GPR32Opnd:$rt);
403  dag InOperandList = (ins ACC64DSPOpnd:$ac, GPR32Opnd:$shift_rs);
404  string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
405  InstrItinClass Itinerary = itin;
406  string BaseOpcode = instr_asm;
407}
408
409class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, InstrItinClass itin> {
410  dag OutOperandList = (outs GPR32Opnd:$rt);
411  dag InOperandList = (ins ACC64DSPOpnd:$ac, uimm5:$shift_rs);
412  string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
413  InstrItinClass Itinerary = itin;
414  string BaseOpcode = instr_asm;
415}
416
417class SHILO_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
418  dag OutOperandList = (outs ACC64DSPOpnd:$ac);
419  dag InOperandList = (ins simm6:$shift, ACC64DSPOpnd:$acin);
420  string AsmString = !strconcat(instr_asm, "\t$ac, $shift");
421  list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
422                        (OpNode immSExt6:$shift, ACC64DSPOpnd:$acin))];
423  string Constraints = "$acin = $ac";
424  string BaseOpcode = instr_asm;
425}
426
427class SHILO_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
428  dag OutOperandList = (outs ACC64DSPOpnd:$ac);
429  dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin);
430  string AsmString = !strconcat(instr_asm, "\t$ac, $rs");
431  list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
432                        (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];
433  string Constraints = "$acin = $ac";
434  string BaseOpcode = instr_asm;
435}
436
437class MTHLIP_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
438  dag OutOperandList = (outs ACC64DSPOpnd:$ac);
439  dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin);
440  string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
441  list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
442                        (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];
443  string Constraints = "$acin = $ac";
444  string BaseOpcode = instr_asm;
445}
446
447class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
448                      InstrItinClass itin> {
449  dag OutOperandList = (outs GPR32Opnd:$rd);
450  dag InOperandList = (ins uimm10:$mask);
451  string AsmString = !strconcat(instr_asm, "\t$rd, $mask");
452  list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode timmZExt10:$mask))];
453  InstrItinClass Itinerary = itin;
454  string BaseOpcode = instr_asm;
455  bit isMoveReg = 1;
456}
457
458class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
459                      InstrItinClass itin> {
460  dag OutOperandList = (outs);
461  dag InOperandList = (ins GPR32Opnd:$rs, uimm10:$mask);
462  string AsmString = !strconcat(instr_asm, "\t$rs, $mask");
463  list<dag> Pattern = [(OpNode GPR32Opnd:$rs, timmZExt10:$mask)];
464  InstrItinClass Itinerary = itin;
465  string BaseOpcode = instr_asm;
466  bit isMoveReg = 1;
467}
468
469class DPA_W_PH_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
470  dag OutOperandList = (outs ACC64DSPOpnd:$ac);
471  dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin);
472  string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
473  list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
474                        (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];
475  string Constraints = "$acin = $ac";
476  string BaseOpcode = instr_asm;
477}
478
479class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
480                     InstrItinClass itin> {
481  dag OutOperandList = (outs ACC64DSPOpnd:$ac);
482  dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt);
483  string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
484  list<dag> Pattern = [(set ACC64DSPOpnd:$ac, (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt))];
485  InstrItinClass Itinerary = itin;
486  bit isCommutable = 1;
487  string BaseOpcode = instr_asm;
488}
489
490class MADD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
491                     InstrItinClass itin> {
492  dag OutOperandList = (outs ACC64DSPOpnd:$ac);
493  dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin);
494  string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
495  list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
496                        (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];
497  InstrItinClass Itinerary = itin;
498  string Constraints = "$acin = $ac";
499  string BaseOpcode = instr_asm;
500}
501
502class MFHI_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
503                     InstrItinClass itin> {
504  dag OutOperandList = (outs GPR32Opnd:$rd);
505  dag InOperandList = (ins RO:$ac);
506  string AsmString = !strconcat(instr_asm, "\t$rd, $ac");
507  list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode RO:$ac))];
508  InstrItinClass Itinerary = itin;
509  string BaseOpcode = instr_asm;
510  bit isMoveReg = 1;
511}
512
513class MTHI_DESC_BASE<string instr_asm, RegisterOperand RO,
514                     InstrItinClass itin> {
515  dag OutOperandList = (outs RO:$ac);
516  dag InOperandList = (ins GPR32Opnd:$rs);
517  string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
518  InstrItinClass Itinerary = itin;
519  string BaseOpcode = instr_asm;
520  bit isMoveReg = 1;
521}
522
523class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode> :
524  MipsPseudo<(outs GPR32Opnd:$dst), (ins), [(set GPR32Opnd:$dst, (OpNode))]> {
525  bit hasNoSchedulingInfo = 1;
526  bit usesCustomInserter = 1;
527}
528
529class BPOSGE32_DESC_BASE<string instr_asm, DAGOperand opnd,
530                         InstrItinClass itin> {
531  dag OutOperandList = (outs);
532  dag InOperandList = (ins opnd:$offset);
533  string AsmString = !strconcat(instr_asm, "\t$offset");
534  InstrItinClass Itinerary = itin;
535  bit isBranch = 1;
536  bit isTerminator = 1;
537  bit hasDelaySlot = 1;
538  string BaseOpcode = instr_asm;
539}
540
541class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
542                     InstrItinClass itin> {
543  dag OutOperandList = (outs GPR32Opnd:$rt);
544  dag InOperandList = (ins GPR32Opnd:$src, GPR32Opnd:$rs);
545  string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
546  list<dag> Pattern = [(set GPR32Opnd:$rt, (OpNode GPR32Opnd:$src, GPR32Opnd:$rs))];
547  InstrItinClass Itinerary = itin;
548  string Constraints = "$src = $rt";
549  string BaseOpcode = instr_asm;
550}
551
552//===----------------------------------------------------------------------===//
553// MIPS DSP Rev 1
554//===----------------------------------------------------------------------===//
555
556// Addition/subtraction
557class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", null_frag, NoItinerary,
558                                       DSPROpnd, DSPROpnd>, IsCommutable,
559                     Defs<[DSPOutFlag20]>;
560
561class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb,
562                                         NoItinerary, DSPROpnd, DSPROpnd>,
563                       IsCommutable, Defs<[DSPOutFlag20]>;
564
565class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", null_frag, NoItinerary,
566                                       DSPROpnd, DSPROpnd>,
567                     Defs<[DSPOutFlag20]>;
568
569class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb,
570                                         NoItinerary, DSPROpnd, DSPROpnd>,
571                       Defs<[DSPOutFlag20]>;
572
573class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", null_frag, NoItinerary,
574                                       DSPROpnd, DSPROpnd>, IsCommutable,
575                     Defs<[DSPOutFlag20]>;
576
577class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph,
578                                         NoItinerary, DSPROpnd, DSPROpnd>,
579                       IsCommutable, Defs<[DSPOutFlag20]>;
580
581class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", null_frag, NoItinerary,
582                                       DSPROpnd, DSPROpnd>,
583                     Defs<[DSPOutFlag20]>;
584
585class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph,
586                                         NoItinerary, DSPROpnd, DSPROpnd>,
587                       Defs<[DSPOutFlag20]>;
588
589class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w,
590                                        NoItinerary, GPR32Opnd, GPR32Opnd>,
591                      IsCommutable, Defs<[DSPOutFlag20]>;
592
593class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w,
594                                        NoItinerary, GPR32Opnd, GPR32Opnd>,
595                      Defs<[DSPOutFlag20]>;
596
597class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", null_frag, NoItinerary,
598                                     GPR32Opnd, GPR32Opnd>, IsCommutable,
599                   Defs<[DSPCarry]>;
600
601class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", null_frag, NoItinerary,
602                                     GPR32Opnd, GPR32Opnd>,
603                   IsCommutable, Uses<[DSPCarry]>, Defs<[DSPOutFlag20]>;
604
605class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary,
606                                      GPR32Opnd, GPR32Opnd>;
607
608class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb,
609                                             NoItinerary, GPR32Opnd, DSPROpnd>;
610
611// Absolute value
612class ABSQ_S_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.ph", int_mips_absq_s_ph,
613                                              NoItinerary, DSPROpnd>,
614                       Defs<[DSPOutFlag20]>;
615
616class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w,
617                                             NoItinerary, GPR32Opnd>,
618                      Defs<[DSPOutFlag20]>;
619
620// Precision reduce/expand
621class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph",
622                                                 int_mips_precrq_qb_ph,
623                                                 NoItinerary, DSPROpnd, DSPROpnd>;
624
625class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w",
626                                                int_mips_precrq_ph_w,
627                                                NoItinerary, DSPROpnd, GPR32Opnd>;
628
629class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w",
630                                                   int_mips_precrq_rs_ph_w,
631                                                   NoItinerary, DSPROpnd,
632                                                   GPR32Opnd>,
633                            Defs<[DSPOutFlag22]>;
634
635class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph",
636                                                    int_mips_precrqu_s_qb_ph,
637                                                    NoItinerary, DSPROpnd,
638                                                    DSPROpnd>,
639                             Defs<[DSPOutFlag22]>;
640
641class PRECEQ_W_PHL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phl",
642                                                 int_mips_preceq_w_phl,
643                                                 NoItinerary, GPR32Opnd, DSPROpnd>;
644
645class PRECEQ_W_PHR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phr",
646                                                 int_mips_preceq_w_phr,
647                                                 NoItinerary, GPR32Opnd, DSPROpnd>;
648
649class PRECEQU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbl",
650                                                   int_mips_precequ_ph_qbl,
651                                                   NoItinerary, DSPROpnd>;
652
653class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr",
654                                                   int_mips_precequ_ph_qbr,
655                                                   NoItinerary, DSPROpnd>;
656
657class PRECEQU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbla",
658                                                    int_mips_precequ_ph_qbla,
659                                                    NoItinerary, DSPROpnd>;
660
661class PRECEQU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbra",
662                                                    int_mips_precequ_ph_qbra,
663                                                    NoItinerary, DSPROpnd>;
664
665class PRECEU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbl",
666                                                  int_mips_preceu_ph_qbl,
667                                                  NoItinerary, DSPROpnd>;
668
669class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr",
670                                                  int_mips_preceu_ph_qbr,
671                                                  NoItinerary, DSPROpnd>;
672
673class PRECEU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbla",
674                                                   int_mips_preceu_ph_qbla,
675                                                   NoItinerary, DSPROpnd>;
676
677class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra",
678                                                   int_mips_preceu_ph_qbra,
679                                                   NoItinerary, DSPROpnd>;
680
681// Shift
682class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", null_frag, immZExt3,
683                                          NoItinerary, DSPROpnd, uimm3>,
684                     Defs<[DSPOutFlag22]>;
685
686class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb,
687                                           NoItinerary, DSPROpnd>,
688                      Defs<[DSPOutFlag22]>;
689
690class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", null_frag, immZExt3,
691                                          NoItinerary, DSPROpnd, uimm3>;
692
693class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb,
694                                           NoItinerary, DSPROpnd>;
695
696class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", null_frag, immZExt4,
697                                          NoItinerary, DSPROpnd, uimm4>,
698                     Defs<[DSPOutFlag22]>;
699
700class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph,
701                                           NoItinerary, DSPROpnd>,
702                      Defs<[DSPOutFlag22]>;
703
704class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph,
705                                            immZExt4, NoItinerary, DSPROpnd,
706                                            uimm4>,
707                       Defs<[DSPOutFlag22]>;
708
709class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph,
710                                             NoItinerary, DSPROpnd>,
711                        Defs<[DSPOutFlag22]>;
712
713class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", null_frag, immZExt4,
714                                          NoItinerary, DSPROpnd, uimm4>;
715
716class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph,
717                                           NoItinerary, DSPROpnd>;
718
719class SHRA_R_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.ph", int_mips_shra_r_ph,
720                                            immZExt4, NoItinerary, DSPROpnd,
721                                            uimm4>;
722
723class SHRAV_R_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.ph", int_mips_shra_r_ph,
724                                             NoItinerary, DSPROpnd>;
725
726class SHLL_S_W_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.w", int_mips_shll_s_w,
727                                           immZExt5, NoItinerary, GPR32Opnd,
728                                           uimm5>,
729                      Defs<[DSPOutFlag22]>;
730
731class SHLLV_S_W_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.w", int_mips_shll_s_w,
732                                            NoItinerary, GPR32Opnd>,
733                       Defs<[DSPOutFlag22]>;
734
735class SHRA_R_W_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.w", int_mips_shra_r_w,
736                                           immZExt5, NoItinerary, GPR32Opnd,
737                                           uimm5>;
738
739class SHRAV_R_W_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.w", int_mips_shra_r_w,
740                                            NoItinerary, GPR32Opnd>;
741
742// Multiplication
743class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl",
744                                              int_mips_muleu_s_ph_qbl,
745                                              NoItinerary, DSPROpnd, DSPROpnd>,
746                            Defs<[DSPOutFlag21]>;
747
748class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr",
749                                              int_mips_muleu_s_ph_qbr,
750                                              NoItinerary, DSPROpnd, DSPROpnd>,
751                            Defs<[DSPOutFlag21]>;
752
753class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl",
754                                             int_mips_muleq_s_w_phl,
755                                             NoItinerary, GPR32Opnd, DSPROpnd>,
756                           IsCommutable, Defs<[DSPOutFlag21]>;
757
758class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr",
759                                             int_mips_muleq_s_w_phr,
760                                             NoItinerary, GPR32Opnd, DSPROpnd>,
761                           IsCommutable, Defs<[DSPOutFlag21]>;
762
763class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph,
764                                          NoItinerary, DSPROpnd, DSPROpnd>,
765                        IsCommutable, Defs<[DSPOutFlag21]>;
766
767class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph",
768                                              MipsMULSAQ_S_W_PH>,
769                           Defs<[DSPOutFlag16_19]>;
770
771class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl", MipsMAQ_S_W_PHL>,
772                         Defs<[DSPOutFlag16_19]>;
773
774class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr", MipsMAQ_S_W_PHR>,
775                         Defs<[DSPOutFlag16_19]>;
776
777class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl", MipsMAQ_SA_W_PHL>,
778                          Defs<[DSPOutFlag16_19]>;
779
780class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr", MipsMAQ_SA_W_PHR>,
781                          Defs<[DSPOutFlag16_19]>;
782
783// Move from/to hi/lo.
784class MFHI_DESC : MFHI_DESC_BASE<"mfhi", ACC64DSPOpnd, MipsMFHI, NoItinerary>;
785class MFLO_DESC : MFHI_DESC_BASE<"mflo", ACC64DSPOpnd, MipsMFLO, NoItinerary>;
786class MTHI_DESC : MTHI_DESC_BASE<"mthi", HI32DSPOpnd, NoItinerary>;
787class MTLO_DESC : MTHI_DESC_BASE<"mtlo", LO32DSPOpnd, NoItinerary>;
788
789// Dot product with accumulate/subtract
790class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl", MipsDPAU_H_QBL>;
791
792class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr", MipsDPAU_H_QBR>;
793
794class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl", MipsDPSU_H_QBL>;
795
796class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr", MipsDPSU_H_QBR>;
797
798class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph", MipsDPAQ_S_W_PH>,
799                         Defs<[DSPOutFlag16_19]>;
800
801class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph", MipsDPSQ_S_W_PH>,
802                         Defs<[DSPOutFlag16_19]>;
803
804class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w", MipsDPAQ_SA_L_W>,
805                         Defs<[DSPOutFlag16_19]>;
806
807class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w", MipsDPSQ_SA_L_W>,
808                         Defs<[DSPOutFlag16_19]>;
809
810class MULT_DSP_DESC  : MULT_DESC_BASE<"mult", MipsMult, NoItinerary>;
811class MULTU_DSP_DESC : MULT_DESC_BASE<"multu", MipsMultu, NoItinerary>;
812class MADD_DSP_DESC  : MADD_DESC_BASE<"madd", MipsMAdd, NoItinerary>;
813class MADDU_DSP_DESC : MADD_DESC_BASE<"maddu", MipsMAddu, NoItinerary>;
814class MSUB_DSP_DESC  : MADD_DESC_BASE<"msub", MipsMSub, NoItinerary>;
815class MSUBU_DSP_DESC : MADD_DESC_BASE<"msubu", MipsMSubu, NoItinerary>;
816
817// Comparison
818class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb",
819                                               int_mips_cmpu_eq_qb, NoItinerary,
820                                               DSPROpnd>,
821                        IsCommutable, Defs<[DSPCCond]>;
822
823class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb",
824                                               int_mips_cmpu_lt_qb, NoItinerary,
825                                               DSPROpnd>, Defs<[DSPCCond]>;
826
827class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb",
828                                               int_mips_cmpu_le_qb, NoItinerary,
829                                               DSPROpnd>, Defs<[DSPCCond]>;
830
831class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb",
832                                                int_mips_cmpgu_eq_qb,
833                                                NoItinerary, GPR32Opnd, DSPROpnd>,
834                         IsCommutable;
835
836class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb",
837                                                int_mips_cmpgu_lt_qb,
838                                                NoItinerary, GPR32Opnd, DSPROpnd>;
839
840class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb",
841                                                int_mips_cmpgu_le_qb,
842                                                NoItinerary, GPR32Opnd, DSPROpnd>;
843
844class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph,
845                                              NoItinerary, DSPROpnd>,
846                       IsCommutable, Defs<[DSPCCond]>;
847
848class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph,
849                                              NoItinerary, DSPROpnd>,
850                       Defs<[DSPCCond]>;
851
852class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph,
853                                              NoItinerary, DSPROpnd>,
854                       Defs<[DSPCCond]>;
855
856// Misc
857class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev,
858                                           NoItinerary, GPR32Opnd>;
859
860class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph,
861                                              NoItinerary, DSPROpnd, DSPROpnd>;
862
863class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, uimm8,
864                                    immZExt8, NoItinerary, DSPROpnd>;
865
866class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, simm10,
867                                    immSExt10, NoItinerary, DSPROpnd>;
868
869class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb,
870                                             NoItinerary, DSPROpnd, GPR32Opnd>;
871
872class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph,
873                                             NoItinerary, DSPROpnd, GPR32Opnd>;
874
875class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb,
876                                            NoItinerary, DSPROpnd, DSPROpnd>,
877                     Uses<[DSPCCond]>;
878
879class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph,
880                                            NoItinerary, DSPROpnd, DSPROpnd>,
881                     Uses<[DSPCCond]>;
882
883class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx, NoItinerary>;
884
885class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx, NoItinerary>;
886
887class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>;
888
889class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", brtarget, NoItinerary>;
890
891// Extr
892class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", NoItinerary>,
893                  Uses<[DSPPos]>, Defs<[DSPEFI]>;
894
895class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", NoItinerary>,
896                   Uses<[DSPPos]>, Defs<[DSPEFI]>;
897
898class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", NoItinerary>,
899                    Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
900
901class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", NoItinerary>,
902                     Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
903
904class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", NoItinerary>,
905                    Defs<[DSPOutFlag23]>;
906
907class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", NoItinerary>,
908                     Defs<[DSPOutFlag23]>;
909
910class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", NoItinerary>,
911                      Defs<[DSPOutFlag23]>;
912
913class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", NoItinerary>,
914                       Defs<[DSPOutFlag23]>;
915
916class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", NoItinerary>,
917                       Defs<[DSPOutFlag23]>;
918
919class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", NoItinerary>,
920                        Defs<[DSPOutFlag23]>;
921
922class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", NoItinerary>,
923                      Defs<[DSPOutFlag23]>;
924
925class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", NoItinerary>,
926                       Defs<[DSPOutFlag23]>;
927
928class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo", MipsSHILO>;
929
930class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov", MipsSHILO>;
931
932class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip", MipsMTHLIP>, Defs<[DSPPos]>;
933
934class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>;
935
936class WRDSP_DESC : WRDSP_DESC_BASE<"wrdsp", int_mips_wrdsp, NoItinerary>;
937
938class INSV_DESC : INSV_DESC_BASE<"insv", int_mips_insv, NoItinerary>,
939                  Uses<[DSPPos, DSPSCount]>;
940
941//===----------------------------------------------------------------------===//
942// MIPS DSP Rev 2
943// Addition/subtraction
944class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary,
945                                       DSPROpnd, DSPROpnd>, IsCommutable,
946                     Defs<[DSPOutFlag20]>;
947
948class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph,
949                                         NoItinerary, DSPROpnd, DSPROpnd>,
950                       IsCommutable, Defs<[DSPOutFlag20]>;
951
952class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary,
953                                       DSPROpnd, DSPROpnd>,
954                     Defs<[DSPOutFlag20]>;
955
956class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph,
957                                         NoItinerary, DSPROpnd, DSPROpnd>,
958                       Defs<[DSPOutFlag20]>;
959
960class ADDUH_QB_DESC : ADDUH_QB_DESC_BASE<"adduh.qb", int_mips_adduh_qb,
961                                         NoItinerary, DSPROpnd>, IsCommutable;
962
963class ADDUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"adduh_r.qb", int_mips_adduh_r_qb,
964                                           NoItinerary, DSPROpnd>, IsCommutable;
965
966class SUBUH_QB_DESC : ADDUH_QB_DESC_BASE<"subuh.qb", int_mips_subuh_qb,
967                                         NoItinerary, DSPROpnd>;
968
969class SUBUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"subuh_r.qb", int_mips_subuh_r_qb,
970                                           NoItinerary, DSPROpnd>;
971
972class ADDQH_PH_DESC : ADDUH_QB_DESC_BASE<"addqh.ph", int_mips_addqh_ph,
973                                         NoItinerary, DSPROpnd>, IsCommutable;
974
975class ADDQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"addqh_r.ph", int_mips_addqh_r_ph,
976                                           NoItinerary, DSPROpnd>, IsCommutable;
977
978class SUBQH_PH_DESC : ADDUH_QB_DESC_BASE<"subqh.ph", int_mips_subqh_ph,
979                                         NoItinerary, DSPROpnd>;
980
981class SUBQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"subqh_r.ph", int_mips_subqh_r_ph,
982                                           NoItinerary, DSPROpnd>;
983
984class ADDQH_W_DESC : ADDUH_QB_DESC_BASE<"addqh.w", int_mips_addqh_w,
985                                        NoItinerary, GPR32Opnd>, IsCommutable;
986
987class ADDQH_R_W_DESC : ADDUH_QB_DESC_BASE<"addqh_r.w", int_mips_addqh_r_w,
988                                          NoItinerary, GPR32Opnd>, IsCommutable;
989
990class SUBQH_W_DESC : ADDUH_QB_DESC_BASE<"subqh.w", int_mips_subqh_w,
991                                        NoItinerary, GPR32Opnd>;
992
993class SUBQH_R_W_DESC : ADDUH_QB_DESC_BASE<"subqh_r.w", int_mips_subqh_r_w,
994                                          NoItinerary, GPR32Opnd>;
995
996// Comparison
997class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb",
998                                                 int_mips_cmpgdu_eq_qb,
999                                                 NoItinerary, GPR32Opnd, DSPROpnd>,
1000                          IsCommutable, Defs<[DSPCCond]>;
1001
1002class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb",
1003                                                 int_mips_cmpgdu_lt_qb,
1004                                                 NoItinerary, GPR32Opnd, DSPROpnd>,
1005                          Defs<[DSPCCond]>;
1006
1007class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb",
1008                                                 int_mips_cmpgdu_le_qb,
1009                                                 NoItinerary, GPR32Opnd, DSPROpnd>,
1010                          Defs<[DSPCCond]>;
1011
1012// Absolute
1013class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb,
1014                                              NoItinerary, DSPROpnd>,
1015                       Defs<[DSPOutFlag20]>;
1016
1017// Multiplication
1018class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", null_frag, NoItinerary,
1019                                       DSPROpnd>, IsCommutable,
1020                    Defs<[DSPOutFlag21]>;
1021
1022class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph,
1023                                         NoItinerary, DSPROpnd>, IsCommutable,
1024                      Defs<[DSPOutFlag21]>;
1025
1026class MULQ_S_W_DESC : ADDUH_QB_DESC_BASE<"mulq_s.w", int_mips_mulq_s_w,
1027                                         NoItinerary, GPR32Opnd>, IsCommutable,
1028                      Defs<[DSPOutFlag21]>;
1029
1030class MULQ_RS_W_DESC : ADDUH_QB_DESC_BASE<"mulq_rs.w", int_mips_mulq_rs_w,
1031                                          NoItinerary, GPR32Opnd>, IsCommutable,
1032                       Defs<[DSPOutFlag21]>;
1033
1034class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph,
1035                                         NoItinerary, DSPROpnd, DSPROpnd>,
1036                       IsCommutable, Defs<[DSPOutFlag21]>;
1037
1038// Dot product with accumulate/subtract
1039class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph", MipsDPA_W_PH>;
1040
1041class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph", MipsDPS_W_PH>;
1042
1043class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph", MipsDPAQX_S_W_PH>,
1044                          Defs<[DSPOutFlag16_19]>;
1045
1046class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph",
1047                                              MipsDPAQX_SA_W_PH>,
1048                           Defs<[DSPOutFlag16_19]>;
1049
1050class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph", MipsDPAX_W_PH>;
1051
1052class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph", MipsDPSX_W_PH>;
1053
1054class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph", MipsDPSQX_S_W_PH>,
1055                          Defs<[DSPOutFlag16_19]>;
1056
1057class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph",
1058                                              MipsDPSQX_SA_W_PH>,
1059                           Defs<[DSPOutFlag16_19]>;
1060
1061class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph", MipsMULSA_W_PH>;
1062
1063// Precision reduce/expand
1064class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph",
1065                                                int_mips_precr_qb_ph,
1066                                                NoItinerary, DSPROpnd, DSPROpnd>;
1067
1068class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w",
1069                                                     int_mips_precr_sra_ph_w,
1070                                                     NoItinerary, DSPROpnd,
1071                                                     GPR32Opnd>;
1072
1073class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w",
1074                                                      int_mips_precr_sra_r_ph_w,
1075                                                       NoItinerary, DSPROpnd,
1076                                                       GPR32Opnd>;
1077
1078// Shift
1079class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", null_frag, immZExt3,
1080                                          NoItinerary, DSPROpnd, uimm3>;
1081
1082class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb,
1083                                           NoItinerary, DSPROpnd>;
1084
1085class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb,
1086                                            immZExt3, NoItinerary, DSPROpnd,
1087                                            uimm3>;
1088
1089class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb,
1090                                             NoItinerary, DSPROpnd>;
1091
1092class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", null_frag, immZExt4,
1093                                          NoItinerary, DSPROpnd, uimm4>;
1094
1095class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph,
1096                                           NoItinerary, DSPROpnd>;
1097
1098// Misc
1099class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, uimm5, timmZExt5,
1100                                     NoItinerary>;
1101
1102class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, uimm2, timmZExt2,
1103                                     NoItinerary>;
1104
1105class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, uimm5,
1106                                      timmZExt5, NoItinerary>;
1107
1108// Pseudos.
1109def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32>,
1110                      Uses<[DSPPos]>;
1111
1112// Instruction defs.
1113// MIPS DSP Rev 1
1114def ADDU_QB : DspMMRel, ADDU_QB_ENC, ADDU_QB_DESC;
1115def ADDU_S_QB : DspMMRel, ADDU_S_QB_ENC, ADDU_S_QB_DESC;
1116def SUBU_QB : DspMMRel, SUBU_QB_ENC, SUBU_QB_DESC;
1117def SUBU_S_QB : DspMMRel, SUBU_S_QB_ENC, SUBU_S_QB_DESC;
1118def ADDQ_PH : DspMMRel, ADDQ_PH_ENC, ADDQ_PH_DESC;
1119def ADDQ_S_PH : DspMMRel, ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
1120def SUBQ_PH : DspMMRel, SUBQ_PH_ENC, SUBQ_PH_DESC;
1121def SUBQ_S_PH : DspMMRel, SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;
1122def ADDQ_S_W : DspMMRel, ADDQ_S_W_ENC, ADDQ_S_W_DESC;
1123def SUBQ_S_W : DspMMRel, SUBQ_S_W_ENC, SUBQ_S_W_DESC;
1124def ADDSC : DspMMRel, ADDSC_ENC, ADDSC_DESC;
1125def ADDWC : DspMMRel, ADDWC_ENC, ADDWC_DESC;
1126def MODSUB : DspMMRel, MODSUB_ENC, MODSUB_DESC;
1127def RADDU_W_QB : DspMMRel, RADDU_W_QB_ENC, RADDU_W_QB_DESC;
1128def ABSQ_S_PH : DspMMRel, ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
1129def ABSQ_S_W : DspMMRel, ABSQ_S_W_ENC, ABSQ_S_W_DESC;
1130def PRECRQ_QB_PH : DspMMRel, PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
1131def PRECRQ_PH_W : DspMMRel, PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
1132def PRECRQ_RS_PH_W : DspMMRel, PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;
1133def PRECRQU_S_QB_PH : DspMMRel, PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC;
1134def PRECEQ_W_PHL : DspMMRel, PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC;
1135def PRECEQ_W_PHR : DspMMRel, PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC;
1136def PRECEQU_PH_QBL : DspMMRel, PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC;
1137def PRECEQU_PH_QBR : DspMMRel, PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC;
1138def PRECEQU_PH_QBLA : DspMMRel, PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC;
1139def PRECEQU_PH_QBRA : DspMMRel, PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC;
1140def PRECEU_PH_QBL : DspMMRel, PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC;
1141def PRECEU_PH_QBR : DspMMRel, PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC;
1142def PRECEU_PH_QBLA : DspMMRel, PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC;
1143def PRECEU_PH_QBRA : DspMMRel, PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC;
1144def SHLL_QB : DspMMRel, SHLL_QB_ENC, SHLL_QB_DESC;
1145def SHLLV_QB : DspMMRel, SHLLV_QB_ENC, SHLLV_QB_DESC;
1146def SHRL_QB : DspMMRel, SHRL_QB_ENC, SHRL_QB_DESC;
1147def SHRLV_QB : DspMMRel, SHRLV_QB_ENC, SHRLV_QB_DESC;
1148def SHLL_PH : DspMMRel, SHLL_PH_ENC, SHLL_PH_DESC;
1149def SHLLV_PH : DspMMRel, SHLLV_PH_ENC, SHLLV_PH_DESC;
1150def SHLL_S_PH : DspMMRel, SHLL_S_PH_ENC, SHLL_S_PH_DESC;
1151def SHLLV_S_PH : DspMMRel, SHLLV_S_PH_ENC, SHLLV_S_PH_DESC;
1152def SHRA_PH : DspMMRel, SHRA_PH_ENC, SHRA_PH_DESC;
1153def SHRAV_PH : DspMMRel, SHRAV_PH_ENC, SHRAV_PH_DESC;
1154def SHRA_R_PH : DspMMRel, SHRA_R_PH_ENC, SHRA_R_PH_DESC;
1155def SHRAV_R_PH : DspMMRel, SHRAV_R_PH_ENC, SHRAV_R_PH_DESC;
1156def SHLL_S_W : DspMMRel, SHLL_S_W_ENC, SHLL_S_W_DESC;
1157def SHLLV_S_W : DspMMRel, SHLLV_S_W_ENC, SHLLV_S_W_DESC;
1158def SHRA_R_W : DspMMRel, SHRA_R_W_ENC, SHRA_R_W_DESC;
1159def SHRAV_R_W : DspMMRel, SHRAV_R_W_ENC, SHRAV_R_W_DESC;
1160def MULEU_S_PH_QBL : DspMMRel, MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC;
1161def MULEU_S_PH_QBR : DspMMRel, MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC;
1162def MULEQ_S_W_PHL : DspMMRel, MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC;
1163def MULEQ_S_W_PHR : DspMMRel, MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC;
1164def MULQ_RS_PH : DspMMRel, MULQ_RS_PH_ENC, MULQ_RS_PH_DESC;
1165def MULSAQ_S_W_PH : DspMMRel, MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC;
1166def MAQ_S_W_PHL : DspMMRel, MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC;
1167def MAQ_S_W_PHR : DspMMRel, MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC;
1168def MAQ_SA_W_PHL : DspMMRel, MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC;
1169def MAQ_SA_W_PHR : DspMMRel, MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC;
1170def MFHI_DSP : DspMMRel, MFHI_ENC, MFHI_DESC;
1171def MFLO_DSP : DspMMRel, MFLO_ENC, MFLO_DESC;
1172def MTHI_DSP : DspMMRel, MTHI_ENC, MTHI_DESC;
1173def MTLO_DSP : DspMMRel, MTLO_ENC, MTLO_DESC;
1174def DPAU_H_QBL : DspMMRel, DPAU_H_QBL_ENC, DPAU_H_QBL_DESC;
1175def DPAU_H_QBR : DspMMRel, DPAU_H_QBR_ENC, DPAU_H_QBR_DESC;
1176def DPSU_H_QBL : DspMMRel, DPSU_H_QBL_ENC, DPSU_H_QBL_DESC;
1177def DPSU_H_QBR : DspMMRel, DPSU_H_QBR_ENC, DPSU_H_QBR_DESC;
1178def DPAQ_S_W_PH : DspMMRel, DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC;
1179def DPSQ_S_W_PH : DspMMRel, DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC;
1180def DPAQ_SA_L_W : DspMMRel, DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC;
1181def DPSQ_SA_L_W : DspMMRel, DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC;
1182def MULT_DSP : DspMMRel, MULT_DSP_ENC, MULT_DSP_DESC;
1183def MULTU_DSP : DspMMRel, MULTU_DSP_ENC, MULTU_DSP_DESC;
1184def MADD_DSP : DspMMRel, MADD_DSP_ENC, MADD_DSP_DESC;
1185def MADDU_DSP : DspMMRel, MADDU_DSP_ENC, MADDU_DSP_DESC;
1186def MSUB_DSP : DspMMRel, MSUB_DSP_ENC, MSUB_DSP_DESC;
1187def MSUBU_DSP : DspMMRel, MSUBU_DSP_ENC, MSUBU_DSP_DESC;
1188def CMPU_EQ_QB : DspMMRel, CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC;
1189def CMPU_LT_QB : DspMMRel, CMPU_LT_QB_ENC, CMPU_LT_QB_DESC;
1190def CMPU_LE_QB : DspMMRel, CMPU_LE_QB_ENC, CMPU_LE_QB_DESC;
1191def CMPGU_EQ_QB : DspMMRel, CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC;
1192def CMPGU_LT_QB : DspMMRel, CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC;
1193def CMPGU_LE_QB : DspMMRel, CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC;
1194def CMP_EQ_PH : DspMMRel, CMP_EQ_PH_ENC, CMP_EQ_PH_DESC;
1195def CMP_LT_PH : DspMMRel, CMP_LT_PH_ENC, CMP_LT_PH_DESC;
1196def CMP_LE_PH : DspMMRel, CMP_LE_PH_ENC, CMP_LE_PH_DESC;
1197def BITREV : DspMMRel, BITREV_ENC, BITREV_DESC;
1198def PACKRL_PH : DspMMRel, PACKRL_PH_ENC, PACKRL_PH_DESC;
1199def REPL_QB : DspMMRel, REPL_QB_ENC, REPL_QB_DESC;
1200def REPL_PH : DspMMRel, REPL_PH_ENC, REPL_PH_DESC;
1201def REPLV_QB : DspMMRel, REPLV_QB_ENC, REPLV_QB_DESC;
1202def REPLV_PH : DspMMRel, REPLV_PH_ENC, REPLV_PH_DESC;
1203def PICK_QB : DspMMRel, PICK_QB_ENC, PICK_QB_DESC;
1204def PICK_PH : DspMMRel, PICK_PH_ENC, PICK_PH_DESC;
1205def LWX : DspMMRel, LWX_ENC, LWX_DESC;
1206def LHX : DspMMRel, LHX_ENC, LHX_DESC;
1207def LBUX : DspMMRel, LBUX_ENC, LBUX_DESC;
1208let AdditionalPredicates = [NotInMicroMips] in {
1209  def BPOSGE32 : DspMMRel, BPOSGE32_ENC, BPOSGE32_DESC;
1210}
1211def INSV : DspMMRel, INSV_ENC, INSV_DESC;
1212def EXTP : DspMMRel, EXTP_ENC, EXTP_DESC;
1213def EXTPV : DspMMRel, EXTPV_ENC, EXTPV_DESC;
1214def EXTPDP : DspMMRel, EXTPDP_ENC, EXTPDP_DESC;
1215def EXTPDPV : DspMMRel, EXTPDPV_ENC, EXTPDPV_DESC;
1216def EXTR_W : DspMMRel, EXTR_W_ENC, EXTR_W_DESC;
1217def EXTRV_W : DspMMRel, EXTRV_W_ENC, EXTRV_W_DESC;
1218def EXTR_R_W : DspMMRel, EXTR_R_W_ENC, EXTR_R_W_DESC;
1219def EXTRV_R_W : DspMMRel, EXTRV_R_W_ENC, EXTRV_R_W_DESC;
1220def EXTR_RS_W : DspMMRel, EXTR_RS_W_ENC, EXTR_RS_W_DESC;
1221def EXTRV_RS_W : DspMMRel, EXTRV_RS_W_ENC, EXTRV_RS_W_DESC;
1222def EXTR_S_H : DspMMRel, EXTR_S_H_ENC, EXTR_S_H_DESC;
1223def EXTRV_S_H : DspMMRel, EXTRV_S_H_ENC, EXTRV_S_H_DESC;
1224def SHILO : DspMMRel, SHILO_ENC, SHILO_DESC;
1225def SHILOV : DspMMRel, SHILOV_ENC, SHILOV_DESC;
1226def MTHLIP : DspMMRel, MTHLIP_ENC, MTHLIP_DESC;
1227def RDDSP : DspMMRel, RDDSP_ENC, RDDSP_DESC;
1228let AdditionalPredicates = [NotInMicroMips] in {
1229  def WRDSP : WRDSP_ENC, WRDSP_DESC;
1230}
1231
1232// MIPS DSP Rev 2
1233def ADDU_PH : DspMMRel, ADDU_PH_ENC, ADDU_PH_DESC, ISA_DSPR2;
1234def ADDU_S_PH : DspMMRel, ADDU_S_PH_ENC, ADDU_S_PH_DESC, ISA_DSPR2;
1235def SUBU_PH : DspMMRel, SUBU_PH_ENC, SUBU_PH_DESC, ISA_DSPR2;
1236def SUBU_S_PH : DspMMRel, SUBU_S_PH_ENC, SUBU_S_PH_DESC, ISA_DSPR2;
1237def CMPGDU_EQ_QB : DspMMRel, CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC, ISA_DSPR2;
1238def CMPGDU_LT_QB : DspMMRel, CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC, ISA_DSPR2;
1239def CMPGDU_LE_QB : DspMMRel, CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC, ISA_DSPR2;
1240def ABSQ_S_QB : DspMMRel, ABSQ_S_QB_ENC, ABSQ_S_QB_DESC, ISA_DSPR2;
1241def ADDUH_QB : DspMMRel, ADDUH_QB_ENC, ADDUH_QB_DESC, ISA_DSPR2;
1242def ADDUH_R_QB : DspMMRel, ADDUH_R_QB_ENC, ADDUH_R_QB_DESC, ISA_DSPR2;
1243def SUBUH_QB : DspMMRel, SUBUH_QB_ENC, SUBUH_QB_DESC, ISA_DSPR2;
1244def SUBUH_R_QB : DspMMRel, SUBUH_R_QB_ENC, SUBUH_R_QB_DESC, ISA_DSPR2;
1245def ADDQH_PH : DspMMRel, ADDQH_PH_ENC, ADDQH_PH_DESC, ISA_DSPR2;
1246def ADDQH_R_PH : DspMMRel, ADDQH_R_PH_ENC, ADDQH_R_PH_DESC, ISA_DSPR2;
1247def SUBQH_PH : DspMMRel, SUBQH_PH_ENC, SUBQH_PH_DESC, ISA_DSPR2;
1248def SUBQH_R_PH : DspMMRel, SUBQH_R_PH_ENC, SUBQH_R_PH_DESC, ISA_DSPR2;
1249def ADDQH_W : DspMMRel, ADDQH_W_ENC, ADDQH_W_DESC, ISA_DSPR2;
1250def ADDQH_R_W : DspMMRel, ADDQH_R_W_ENC, ADDQH_R_W_DESC, ISA_DSPR2;
1251def SUBQH_W : DspMMRel, SUBQH_W_ENC, SUBQH_W_DESC, ISA_DSPR2;
1252def SUBQH_R_W : DspMMRel, SUBQH_R_W_ENC, SUBQH_R_W_DESC, ISA_DSPR2;
1253def MUL_PH : DspMMRel, MUL_PH_ENC, MUL_PH_DESC, ISA_DSPR2;
1254def MUL_S_PH : DspMMRel, MUL_S_PH_ENC, MUL_S_PH_DESC, ISA_DSPR2;
1255def MULQ_S_W : DspMMRel, MULQ_S_W_ENC, MULQ_S_W_DESC, ISA_DSPR2;
1256def MULQ_RS_W : DspMMRel, MULQ_RS_W_ENC, MULQ_RS_W_DESC, ISA_DSPR2;
1257def MULQ_S_PH : DspMMRel, MULQ_S_PH_ENC, MULQ_S_PH_DESC, ISA_DSPR2;
1258def DPA_W_PH : DspMMRel, DPA_W_PH_ENC, DPA_W_PH_DESC, ISA_DSPR2;
1259def DPS_W_PH : DspMMRel, DPS_W_PH_ENC, DPS_W_PH_DESC, ISA_DSPR2;
1260def DPAQX_S_W_PH : DspMMRel, DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC, ISA_DSPR2;
1261def DPAQX_SA_W_PH : DspMMRel, DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC, ISA_DSPR2;
1262def DPAX_W_PH : DspMMRel, DPAX_W_PH_ENC, DPAX_W_PH_DESC, ISA_DSPR2;
1263def DPSX_W_PH : DspMMRel, DPSX_W_PH_ENC, DPSX_W_PH_DESC, ISA_DSPR2;
1264def DPSQX_S_W_PH : DspMMRel, DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC, ISA_DSPR2;
1265def DPSQX_SA_W_PH : DspMMRel, DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC, ISA_DSPR2;
1266def MULSA_W_PH : DspMMRel, MULSA_W_PH_ENC, MULSA_W_PH_DESC, ISA_DSPR2;
1267def PRECR_QB_PH : DspMMRel, PRECR_QB_PH_ENC, PRECR_QB_PH_DESC, ISA_DSPR2;
1268def PRECR_SRA_PH_W : DspMMRel, PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC, ISA_DSPR2;
1269def PRECR_SRA_R_PH_W : DspMMRel, PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC, ISA_DSPR2;
1270def SHRA_QB : DspMMRel, SHRA_QB_ENC, SHRA_QB_DESC, ISA_DSPR2;
1271def SHRAV_QB : DspMMRel, SHRAV_QB_ENC, SHRAV_QB_DESC, ISA_DSPR2;
1272def SHRA_R_QB : DspMMRel, SHRA_R_QB_ENC, SHRA_R_QB_DESC, ISA_DSPR2;
1273def SHRAV_R_QB : DspMMRel, SHRAV_R_QB_ENC, SHRAV_R_QB_DESC, ISA_DSPR2;
1274def SHRL_PH : DspMMRel, SHRL_PH_ENC, SHRL_PH_DESC, ISA_DSPR2;
1275def SHRLV_PH : DspMMRel, SHRLV_PH_ENC, SHRLV_PH_DESC, ISA_DSPR2;
1276def APPEND : DspMMRel, APPEND_ENC, APPEND_DESC, ISA_DSPR2;
1277def BALIGN : DspMMRel, BALIGN_ENC, BALIGN_DESC, ISA_DSPR2;
1278def PREPEND : DspMMRel, PREPEND_ENC, PREPEND_DESC, ISA_DSPR2;
1279
1280// Pseudos.
1281let isPseudo = 1, isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in {
1282  // Pseudo instructions for loading and storing accumulator registers.
1283  def LOAD_ACC64DSP  : Load<"", ACC64DSPOpnd>;
1284  def STORE_ACC64DSP : Store<"", ACC64DSPOpnd>;
1285
1286  // Pseudos for loading and storing ccond field of DSP control register.
1287  def LOAD_CCOND_DSP  : Load<"load_ccond_dsp", DSPCC>;
1288  def STORE_CCOND_DSP : Store<"store_ccond_dsp", DSPCC>;
1289}
1290
1291let DecoderNamespace = "MipsDSP", Arch = "dsp",
1292    ASEPredicate = [HasDSP] in {
1293  def LWDSP : Load<"lw", DSPROpnd, null_frag, II_LW>, DspMMRel, LW_FM<0x23>;
1294  def SWDSP : Store<"sw", DSPROpnd, null_frag, II_SW>, DspMMRel, LW_FM<0x2b>;
1295}
1296
1297// Pseudo CMP and PICK instructions.
1298class PseudoCMP<Instruction RealInst> :
1299  PseudoDSP<(outs DSPCC:$cmp), (ins DSPROpnd:$rs, DSPROpnd:$rt), []>,
1300  PseudoInstExpansion<(RealInst DSPROpnd:$rs, DSPROpnd:$rt)>,
1301  NeverHasSideEffects;
1302
1303class PseudoPICK<Instruction RealInst> :
1304  PseudoDSP<(outs DSPROpnd:$rd), (ins DSPCC:$cmp, DSPROpnd:$rs, DSPROpnd:$rt), []>,
1305  PseudoInstExpansion<(RealInst DSPROpnd:$rd, DSPROpnd:$rs, DSPROpnd:$rt)>,
1306  NeverHasSideEffects;
1307
1308def PseudoCMP_EQ_PH : PseudoCMP<CMP_EQ_PH>;
1309def PseudoCMP_LT_PH : PseudoCMP<CMP_LT_PH>;
1310def PseudoCMP_LE_PH : PseudoCMP<CMP_LE_PH>;
1311def PseudoCMPU_EQ_QB : PseudoCMP<CMPU_EQ_QB>;
1312def PseudoCMPU_LT_QB : PseudoCMP<CMPU_LT_QB>;
1313def PseudoCMPU_LE_QB : PseudoCMP<CMPU_LE_QB>;
1314
1315def PseudoPICK_PH : PseudoPICK<PICK_PH>;
1316def PseudoPICK_QB : PseudoPICK<PICK_QB>;
1317
1318let AdditionalPredicates = [HasDSP] in {
1319  def PseudoMTLOHI_DSP : PseudoMTLOHI<ACC64DSP, GPR32>;
1320}
1321
1322// Patterns.
1323class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
1324  Pat<pattern, result>, Requires<[pred]>;
1325
1326class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
1327                    RegisterClass SrcRC> :
1328   DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
1329          (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
1330
1331def : BitconvertPat<i32, v2i16, GPR32, DSPR>;
1332def : BitconvertPat<i32, v4i8, GPR32, DSPR>;
1333def : BitconvertPat<v2i16, i32, DSPR, GPR32>;
1334def : BitconvertPat<v4i8, i32, DSPR, GPR32>;
1335def : BitconvertPat<f32, v2i16, FGR32, DSPR>;
1336def : BitconvertPat<f32, v4i8, FGR32, DSPR>;
1337def : BitconvertPat<v2i16, f32, DSPR, FGR32>;
1338def : BitconvertPat<v4i8, f32, DSPR, FGR32>;
1339
1340def : DSPPat<(v2i16 (load addr:$a)),
1341             (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1342def : DSPPat<(v4i8 (load addr:$a)),
1343             (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1344def : DSPPat<(store (v2i16 DSPR:$val), addr:$a),
1345             (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1346def : DSPPat<(store (v4i8 DSPR:$val), addr:$a),
1347             (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1348
1349// Binary operations.
1350class DSPBinPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1351                Predicate Pred = HasDSP> :
1352  DSPPat<(Node ValTy:$a, ValTy:$b), (Inst ValTy:$a, ValTy:$b), Pred>;
1353
1354def : DSPBinPat<ADDQ_PH, v2i16, int_mips_addq_ph>;
1355def : DSPBinPat<ADDQ_PH, v2i16, add>;
1356def : DSPBinPat<SUBQ_PH, v2i16, int_mips_subq_ph>;
1357def : DSPBinPat<SUBQ_PH, v2i16, sub>;
1358def : DSPBinPat<MUL_PH, v2i16, int_mips_mul_ph, HasDSPR2>;
1359def : DSPBinPat<MUL_PH, v2i16, mul, HasDSPR2>;
1360def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>;
1361def : DSPBinPat<ADDU_QB, v4i8, add>;
1362def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>;
1363def : DSPBinPat<SUBU_QB, v4i8, sub>;
1364def : DSPBinPat<ADDSC, i32, int_mips_addsc>;
1365def : DSPBinPat<ADDSC, i32, addc>;
1366def : DSPBinPat<ADDWC, i32, int_mips_addwc>;
1367def : DSPBinPat<ADDWC, i32, adde>;
1368
1369// Shift immediate patterns.
1370class DSPShiftPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1371                  SDPatternOperator Imm, Predicate Pred = HasDSP> :
1372  DSPPat<(Node ValTy:$a, Imm:$shamt), (Inst ValTy:$a, Imm:$shamt), Pred>;
1373
1374def : DSPShiftPat<SHLL_PH, v2i16, MipsSHLL_DSP, imm>;
1375def : DSPShiftPat<SHRA_PH, v2i16, MipsSHRA_DSP, imm>;
1376def : DSPShiftPat<SHRL_PH, v2i16, MipsSHRL_DSP, imm, HasDSPR2>;
1377def : DSPShiftPat<SHLL_PH, v2i16, int_mips_shll_ph, immZExt4>;
1378def : DSPShiftPat<SHRA_PH, v2i16, int_mips_shra_ph, immZExt4>;
1379def : DSPShiftPat<SHRL_PH, v2i16, int_mips_shrl_ph, immZExt4, HasDSPR2>;
1380def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, imm>;
1381def : DSPShiftPat<SHRA_QB, v4i8, MipsSHRA_DSP, imm, HasDSPR2>;
1382def : DSPShiftPat<SHRL_QB, v4i8, MipsSHRL_DSP, imm>;
1383def : DSPShiftPat<SHLL_QB, v4i8, int_mips_shll_qb, immZExt3>;
1384def : DSPShiftPat<SHRA_QB, v4i8, int_mips_shra_qb, immZExt3, HasDSPR2>;
1385def : DSPShiftPat<SHRL_QB, v4i8, int_mips_shrl_qb, immZExt3>;
1386
1387// SETCC/SELECT_CC patterns.
1388class DSPSetCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
1389                  CondCode CC> :
1390  DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
1391         (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
1392                      (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR)),
1393                      (ValTy ZERO)))>;
1394
1395class DSPSetCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
1396                     CondCode CC> :
1397  DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
1398         (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
1399                      (ValTy ZERO),
1400                      (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR))))>;
1401
1402class DSPSelectCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
1403                     CondCode CC> :
1404  DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
1405         (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $c, $d))>;
1406
1407class DSPSelectCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
1408                        CondCode CC> :
1409  DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
1410         (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $d, $c))>;
1411
1412def : DSPSetCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1413def : DSPSetCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1414def : DSPSetCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
1415def : DSPSetCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1416def : DSPSetCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
1417def : DSPSetCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
1418def : DSPSetCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1419def : DSPSetCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1420def : DSPSetCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1421def : DSPSetCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1422def : DSPSetCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1423def : DSPSetCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1424
1425def : DSPSelectCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1426def : DSPSelectCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1427def : DSPSelectCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
1428def : DSPSelectCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1429def : DSPSelectCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
1430def : DSPSelectCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
1431def : DSPSelectCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1432def : DSPSelectCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1433def : DSPSelectCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1434def : DSPSelectCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1435def : DSPSelectCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1436def : DSPSelectCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1437
1438// Extr patterns.
1439class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :
1440  DSPPat<(i32 (OpNode GPR32:$rs, ACC64DSP:$ac)),
1441         (Instr ACC64DSP:$ac, GPR32:$rs)>;
1442
1443class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> :
1444  DSPPat<(i32 (OpNode immZExt5:$shift, ACC64DSP:$ac)),
1445         (Instr ACC64DSP:$ac, immZExt5:$shift)>;
1446
1447def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>;
1448def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>;
1449def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>;
1450def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>;
1451def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>;
1452def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>;
1453def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>;
1454def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>;
1455def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>;
1456def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>;
1457def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>;
1458def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>;
1459
1460// Indexed load patterns.
1461class IndexedLoadPat<SDPatternOperator LoadNode, Instruction Instr> :
1462  DSPPat<(i32 (LoadNode (add i32:$base, i32:$index))),
1463         (Instr i32:$base, i32:$index)>;
1464
1465let AddedComplexity = 20 in {
1466  def : IndexedLoadPat<zextloadi8, LBUX>;
1467  def : IndexedLoadPat<sextloadi16, LHX>;
1468  def : IndexedLoadPat<load, LWX>;
1469}
1470
1471// Instruction alias.
1472let AdditionalPredicates = [NotInMicroMips] in {
1473  def : DSPInstAlias<"wrdsp $rt", (WRDSP GPR32Opnd:$rt, 0x1F), 1>;
1474}
1475