1//===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10//  Describe MIPS instructions format
11//
12//  CPU INSTRUCTION FORMATS
13//
14//  opcode  - operation code.
15//  rs      - src reg.
16//  rt      - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
17//  rd      - dst reg, only used on 3 regs instr.
18//  shamt   - only used on shift instructions, contains the shift amount.
19//  funct   - combined with opcode field give us an operation code.
20//
21//===----------------------------------------------------------------------===//
22
23// Format specifies the encoding used by the instruction.  This is part of the
24// ad-hoc solution used to emit machine instruction encodings by our machine
25// code emitter.
26class Format<bits<4> val> {
27  bits<4> Value = val;
28}
29
30def Pseudo    : Format<0>;
31def FrmR      : Format<1>;
32def FrmI      : Format<2>;
33def FrmJ      : Format<3>;
34def FrmFR     : Format<4>;
35def FrmFI     : Format<5>;
36def FrmOther  : Format<6>; // Instruction w/ a custom format
37
38class MMRel;
39
40def Std2MicroMips : InstrMapping {
41  let FilterClass = "MMRel";
42  // Instructions with the same BaseOpcode and isNVStore values form a row.
43  let RowFields = ["BaseOpcode"];
44  // Instructions with the same predicate sense form a column.
45  let ColFields = ["Arch"];
46  // The key column is the unpredicated instructions.
47  let KeyCol = ["se"];
48  // Value columns are PredSense=true and PredSense=false
49  let ValueCols = [["se"], ["micromips"]];
50}
51
52class StdMMR6Rel;
53
54def Std2MicroMipsR6 : InstrMapping {
55  let FilterClass = "StdMMR6Rel";
56  // Instructions with the same BaseOpcode and isNVStore values form a row.
57  let RowFields = ["BaseOpcode"];
58  // Instructions with the same predicate sense form a column.
59  let ColFields = ["Arch"];
60  // The key column is the unpredicated instructions.
61  let KeyCol = ["se"];
62  // Value columns are PredSense=true and PredSense=false
63  let ValueCols = [["se"], ["micromipsr6"]];
64}
65
66class StdArch {
67  string Arch = "se";
68}
69
70// Generic Mips Format
71class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
72               InstrItinClass itin, Format f>: Instruction, PredicateControl
73{
74  field bits<32> Inst;
75  Format Form = f;
76
77  let Namespace = "Mips";
78
79  let Size = 4;
80
81  bits<6> Opcode = 0;
82
83  // Top 6 bits are the 'opcode' field
84  let Inst{31-26} = Opcode;
85
86  let OutOperandList = outs;
87  let InOperandList  = ins;
88
89  let AsmString   = asmstr;
90  let Pattern     = pattern;
91  let Itinerary   = itin;
92
93  //
94  // Attributes specific to Mips instructions...
95  //
96  bits<4> FormBits     = Form.Value;
97  bit isCTI            = 0; // Any form of Control Transfer Instruction.
98                            // Required for MIPSR6
99  bit hasForbiddenSlot = 0; // Instruction has a forbidden slot.
100  bit hasFCCRegOperand = 0; // Instruction uses $fcc<X> register and is
101                            // present in MIPS-I to MIPS-III.
102
103  // TSFlags layout should be kept in sync with MCTargetDesc/MipsBaseInfo.h.
104  let TSFlags{3-0}   = FormBits;
105  let TSFlags{4}     = isCTI;
106  let TSFlags{5}     = hasForbiddenSlot;
107  let TSFlags{6}     = hasFCCRegOperand;
108
109  let DecoderNamespace = "Mips";
110
111  field bits<32> SoftFail = 0;
112}
113
114// Mips32/64 Instruction Format
115class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
116             InstrItinClass itin, Format f, string opstr = ""> :
117  MipsInst<outs, ins, asmstr, pattern, itin, f> {
118  let EncodingPredicates = [NotInMips16Mode];
119  string BaseOpcode = opstr;
120  string Arch;
121}
122
123// Mips Pseudo Instructions Format
124class MipsPseudo<dag outs, dag ins, list<dag> pattern,
125                 InstrItinClass itin = IIPseudo> :
126  MipsInst<outs, ins, "", pattern, itin, Pseudo> {
127  let isCodeGenOnly = 1;
128  let isPseudo = 1;
129}
130
131// Mips32/64 Pseudo Instruction Format
132class PseudoSE<dag outs, dag ins, list<dag> pattern,
133               InstrItinClass itin = IIPseudo> :
134  MipsPseudo<outs, ins, pattern, itin> {
135  let EncodingPredicates = [NotInMips16Mode];
136}
137
138// Pseudo-instructions for alternate assembly syntax (never used by codegen).
139// These are aliases that require C++ handling to convert to the target
140// instruction, while InstAliases can be handled directly by tblgen.
141class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
142  MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
143  let isPseudo = 1;
144  let hasNoSchedulingInfo = 1;
145  let Pattern = [];
146}
147//===----------------------------------------------------------------------===//
148// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
149//===----------------------------------------------------------------------===//
150
151class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
152         list<dag> pattern, InstrItinClass itin>:
153  InstSE<outs, ins, asmstr, pattern, itin, FrmR>
154{
155  bits<5>  rd;
156  bits<5>  rs;
157  bits<5>  rt;
158  bits<5>  shamt;
159  bits<6>  funct;
160
161  let Opcode = op;
162  let funct  = _funct;
163
164  let Inst{25-21} = rs;
165  let Inst{20-16} = rt;
166  let Inst{15-11} = rd;
167  let Inst{10-6}  = shamt;
168  let Inst{5-0}   = funct;
169}
170
171//===----------------------------------------------------------------------===//
172// Format J instruction class in Mips : <|opcode|address|>
173//===----------------------------------------------------------------------===//
174
175class FJ<bits<6> op> : StdArch
176{
177  bits<26> target;
178
179  bits<32> Inst;
180
181  let Inst{31-26} = op;
182  let Inst{25-0}  = target;
183}
184
185//===----------------------------------------------------------------------===//
186// MFC instruction class in Mips : <|op|mf|rt|rd|gst|0000|sel|>
187//===----------------------------------------------------------------------===//
188class MFC3OP_FM<bits<6> op, bits<5> mfmt, bits<3> guest> : StdArch {
189  bits<5> rt;
190  bits<5> rd;
191  bits<3> sel;
192
193  bits<32> Inst;
194
195  let Inst{31-26} = op;
196  let Inst{25-21} = mfmt;
197  let Inst{20-16} = rt;
198  let Inst{15-11} = rd;
199  let Inst{10-8}  = guest;
200  let Inst{7-3}   = 0;
201  let Inst{2-0}   = sel;
202}
203
204class MFC2OP_FM<bits<6> op, bits<5> mfmt> : StdArch {
205  bits<5>  rt;
206  bits<16> imm16;
207
208  bits<32> Inst;
209
210  let Inst{31-26} = op;
211  let Inst{25-21} = mfmt;
212  let Inst{20-16} = rt;
213  let Inst{15-0}  = imm16;
214}
215
216class ADD_FM<bits<6> op, bits<6> funct> : StdArch {
217  bits<5> rd;
218  bits<5> rs;
219  bits<5> rt;
220
221  bits<32> Inst;
222
223  let Inst{31-26} = op;
224  let Inst{25-21} = rs;
225  let Inst{20-16} = rt;
226  let Inst{15-11} = rd;
227  let Inst{10-6}  = 0;
228  let Inst{5-0}   = funct;
229}
230
231class ADDI_FM<bits<6> op> : StdArch {
232  bits<5>  rs;
233  bits<5>  rt;
234  bits<16> imm16;
235
236  bits<32> Inst;
237
238  let Inst{31-26} = op;
239  let Inst{25-21} = rs;
240  let Inst{20-16} = rt;
241  let Inst{15-0}  = imm16;
242}
243
244class SRA_FM<bits<6> funct, bit rotate> : StdArch {
245  bits<5> rd;
246  bits<5> rt;
247  bits<5> shamt;
248
249  bits<32> Inst;
250
251  let Inst{31-26} = 0;
252  let Inst{25-22} = 0;
253  let Inst{21}    = rotate;
254  let Inst{20-16} = rt;
255  let Inst{15-11} = rd;
256  let Inst{10-6}  = shamt;
257  let Inst{5-0}   = funct;
258}
259
260class SRLV_FM<bits<6> funct, bit rotate> : StdArch {
261  bits<5> rd;
262  bits<5> rt;
263  bits<5> rs;
264
265  bits<32> Inst;
266
267  let Inst{31-26} = 0;
268  let Inst{25-21} = rs;
269  let Inst{20-16} = rt;
270  let Inst{15-11} = rd;
271  let Inst{10-7}  = 0;
272  let Inst{6}     = rotate;
273  let Inst{5-0}   = funct;
274}
275
276class BEQ_FM<bits<6> op> : StdArch {
277  bits<5>  rs;
278  bits<5>  rt;
279  bits<16> offset;
280
281  bits<32> Inst;
282
283  let Inst{31-26} = op;
284  let Inst{25-21} = rs;
285  let Inst{20-16} = rt;
286  let Inst{15-0}  = offset;
287}
288
289class BGEZ_FM<bits<6> op, bits<5> funct> : StdArch {
290  bits<5>  rs;
291  bits<16> offset;
292
293  bits<32> Inst;
294
295  let Inst{31-26} = op;
296  let Inst{25-21} = rs;
297  let Inst{20-16} = funct;
298  let Inst{15-0}  = offset;
299}
300
301class BBIT_FM<bits<6> op> : StdArch {
302  bits<5>  rs;
303  bits<5>  p;
304  bits<16> offset;
305
306  bits<32> Inst;
307
308  let Inst{31-26} = op;
309  let Inst{25-21} = rs;
310  let Inst{20-16} = p;
311  let Inst{15-0}  = offset;
312}
313
314class SLTI_FM<bits<6> op> : StdArch {
315  bits<5> rt;
316  bits<5> rs;
317  bits<16> imm16;
318
319  bits<32> Inst;
320
321  let Inst{31-26} = op;
322  let Inst{25-21} = rs;
323  let Inst{20-16} = rt;
324  let Inst{15-0}  = imm16;
325}
326
327class MFLO_FM<bits<6> funct> : StdArch {
328  bits<5> rd;
329
330  bits<32> Inst;
331
332  let Inst{31-26} = 0;
333  let Inst{25-16} = 0;
334  let Inst{15-11} = rd;
335  let Inst{10-6}  = 0;
336  let Inst{5-0}   = funct;
337}
338
339class MTLO_FM<bits<6> funct> : StdArch {
340  bits<5> rs;
341
342  bits<32> Inst;
343
344  let Inst{31-26} = 0;
345  let Inst{25-21} = rs;
346  let Inst{20-6}  = 0;
347  let Inst{5-0}   = funct;
348}
349
350class SEB_FM<bits<5> funct, bits<6> funct2> : StdArch {
351  bits<5> rd;
352  bits<5> rt;
353
354  bits<32> Inst;
355
356  let Inst{31-26} = 0x1f;
357  let Inst{25-21} = 0;
358  let Inst{20-16} = rt;
359  let Inst{15-11} = rd;
360  let Inst{10-6}  = funct;
361  let Inst{5-0}   = funct2;
362}
363
364class CLO_FM<bits<6> funct> : StdArch {
365  bits<5> rd;
366  bits<5> rs;
367  bits<5> rt;
368
369  bits<32> Inst;
370
371  let Inst{31-26} = 0x1c;
372  let Inst{25-21} = rs;
373  let Inst{20-16} = rt;
374  let Inst{15-11} = rd;
375  let Inst{10-6}  = 0;
376  let Inst{5-0}   = funct;
377  let rt = rd;
378}
379
380class LUI_FM : StdArch {
381  bits<5> rt;
382  bits<16> imm16;
383
384  bits<32> Inst;
385
386  let Inst{31-26} = 0xf;
387  let Inst{25-21} = 0;
388  let Inst{20-16} = rt;
389  let Inst{15-0}  = imm16;
390}
391
392class JALR_FM {
393  bits<5> rd;
394  bits<5> rs;
395
396  bits<32> Inst;
397
398  let Inst{31-26} = 0;
399  let Inst{25-21} = rs;
400  let Inst{20-16} = 0;
401  let Inst{15-11} = rd;
402  let Inst{10-6}  = 0;
403  let Inst{5-0}   = 9;
404}
405
406class BGEZAL_FM<bits<5> funct> : StdArch {
407  bits<5>  rs;
408  bits<16> offset;
409
410  bits<32> Inst;
411
412  let Inst{31-26} = 1;
413  let Inst{25-21} = rs;
414  let Inst{20-16} = funct;
415  let Inst{15-0}  = offset;
416}
417
418class SYNC_FM : StdArch {
419  bits<5> stype;
420
421  bits<32> Inst;
422
423  let Inst{31-26} = 0;
424  let Inst{10-6}  = stype;
425  let Inst{5-0}   = 0xf;
426}
427
428class SYNCI_FM : StdArch {
429  // Produced by the mem_simm16 address as reg << 16 | imm (see getMemEncoding).
430  bits<21> addr;
431  bits<5> rs = addr{20-16};
432  bits<16> offset = addr{15-0};
433
434  bits<32> Inst;
435
436  let Inst{31-26} = 0b000001;
437  let Inst{25-21} = rs;
438  let Inst{20-16} = 0b11111;
439  let Inst{15-0}  = offset;
440}
441
442class MULT_FM<bits<6> op, bits<6> funct> : StdArch {
443  bits<5>  rs;
444  bits<5>  rt;
445
446  bits<32> Inst;
447
448  let Inst{31-26} = op;
449  let Inst{25-21} = rs;
450  let Inst{20-16} = rt;
451  let Inst{15-6}  = 0;
452  let Inst{5-0}   = funct;
453}
454
455class EXT_FM<bits<6> funct> : StdArch {
456  bits<5> rt;
457  bits<5> rs;
458  bits<5> pos;
459  bits<5> size;
460
461  bits<32> Inst;
462
463  let Inst{31-26} = 0x1f;
464  let Inst{25-21} = rs;
465  let Inst{20-16} = rt;
466  let Inst{15-11} = size;
467  let Inst{10-6}  = pos;
468  let Inst{5-0}   = funct;
469}
470
471class RDHWR_FM : StdArch {
472  bits<5> rt;
473  bits<5> rd;
474  bits<3> sel;
475
476  bits<32> Inst;
477
478  let Inst{31-26} = 0x1f;
479  let Inst{25-21} = 0;
480  let Inst{20-16} = rt;
481  let Inst{15-11} = rd;
482  let Inst{10-9}  = 0b00;
483  let Inst{8-6}   = sel;
484  let Inst{5-0}   = 0x3b;
485}
486
487class TEQ_FM<bits<6> funct> : StdArch {
488  bits<5> rs;
489  bits<5> rt;
490  bits<10> code_;
491
492  bits<32> Inst;
493
494  let Inst{31-26} = 0;
495  let Inst{25-21} = rs;
496  let Inst{20-16} = rt;
497  let Inst{15-6}  = code_;
498  let Inst{5-0}   = funct;
499}
500
501class TEQI_FM<bits<5> funct> : StdArch {
502  bits<5> rs;
503  bits<16> imm16;
504
505  bits<32> Inst;
506
507  let Inst{31-26} = 1;
508  let Inst{25-21} = rs;
509  let Inst{20-16}   = funct;
510  let Inst{15-0}  = imm16;
511}
512
513class WAIT_FM : StdArch {
514  bits<32> Inst;
515
516  let Inst{31-26} = 0x10;
517  let Inst{25}    = 1;
518  let Inst{24-6}  = 0;
519  let Inst{5-0}   = 0x20;
520}
521
522class EXTS_FM<bits<6> funct> : StdArch {
523  bits<5> rt;
524  bits<5> rs;
525  bits<5> pos;
526  bits<5> lenm1;
527
528  bits<32> Inst;
529
530  let Inst{31-26} = 0x1c;
531  let Inst{25-21} = rs;
532  let Inst{20-16} = rt;
533  let Inst{15-11} = lenm1;
534  let Inst{10-6}  = pos;
535  let Inst{5-0}   = funct;
536}
537
538class MTMR_FM<bits<6> funct> : StdArch {
539  bits<5> rs;
540
541  bits<32> Inst;
542
543  let Inst{31-26} = 0x1c;
544  let Inst{25-21} = rs;
545  let Inst{20-6}  = 0;
546  let Inst{5-0}   = funct;
547}
548
549class POP_FM<bits<6> funct> : StdArch {
550  bits<5> rd;
551  bits<5> rs;
552
553  bits<32> Inst;
554
555  let Inst{31-26} = 0x1c;
556  let Inst{25-21} = rs;
557  let Inst{20-16} = 0;
558  let Inst{15-11} = rd;
559  let Inst{10-6}  = 0;
560  let Inst{5-0}   = funct;
561}
562
563class SEQ_FM<bits<6> funct> : StdArch {
564  bits<5> rd;
565  bits<5> rs;
566  bits<5> rt;
567
568  bits<32> Inst;
569
570  let Inst{31-26} = 0x1c;
571  let Inst{25-21} = rs;
572  let Inst{20-16} = rt;
573  let Inst{15-11} = rd;
574  let Inst{10-6}  = 0;
575  let Inst{5-0}   = funct;
576}
577
578class SEQI_FM<bits<6> funct> : StdArch {
579  bits<5> rs;
580  bits<5> rt;
581  bits<10> imm10;
582
583  bits<32> Inst;
584
585  let Inst{31-26} = 0x1c;
586  let Inst{25-21} = rs;
587  let Inst{20-16} = rt;
588  let Inst{15-6}  = imm10;
589  let Inst{5-0}   = funct;
590}
591
592class SAA_FM<bits<6> funct> : StdArch {
593  bits<5> rt;
594  bits<5> rs;
595
596  bits<32> Inst;
597
598  let Inst{31-26} = 0x1c;
599  let Inst{25-21} = rs;
600  let Inst{20-16} = rt;
601  let Inst{15-6}  = 0;
602  let Inst{5-0}   = funct;
603}
604
605//===----------------------------------------------------------------------===//
606//  System calls format <op|code_|funct>
607//===----------------------------------------------------------------------===//
608
609class SYS_FM<bits<6> funct> : StdArch
610{
611  bits<20> code_;
612  bits<32> Inst;
613  let Inst{31-26} = 0x0;
614  let Inst{25-6} = code_;
615  let Inst{5-0}  = funct;
616}
617
618//===----------------------------------------------------------------------===//
619//  Break instruction format <op|code_1|funct>
620//===----------------------------------------------------------------------===//
621
622class BRK_FM<bits<6> funct> : StdArch
623{
624  bits<10> code_1;
625  bits<10> code_2;
626  bits<32> Inst;
627  let Inst{31-26} = 0x0;
628  let Inst{25-16} = code_1;
629  let Inst{15-6}  = code_2;
630  let Inst{5-0}   = funct;
631}
632
633//===----------------------------------------------------------------------===//
634//  Exception return format <Cop0|1|0|funct>
635//===----------------------------------------------------------------------===//
636
637class ER_FM<bits<6> funct, bit LLBit> : StdArch
638{
639  bits<32> Inst;
640  let Inst{31-26} = 0x10;
641  let Inst{25}    = 1;
642  let Inst{24-7}  = 0;
643  let Inst{6} = LLBit;
644  let Inst{5-0}   = funct;
645}
646
647//===----------------------------------------------------------------------===//
648//  Enable/disable interrupt instruction format <Cop0|MFMC0|rt|12|0|sc|0|0>
649//===----------------------------------------------------------------------===//
650
651class EI_FM<bits<1> sc> : StdArch
652{
653  bits<32> Inst;
654  bits<5> rt;
655  let Inst{31-26} = 0x10;
656  let Inst{25-21} = 0xb;
657  let Inst{20-16} = rt;
658  let Inst{15-11} = 0xc;
659  let Inst{10-6}  = 0;
660  let Inst{5}     = sc;
661  let Inst{4-0}   = 0;
662}
663
664//===----------------------------------------------------------------------===//
665//
666//  FLOATING POINT INSTRUCTION FORMATS
667//
668//  opcode  - operation code.
669//  fs      - src reg.
670//  ft      - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
671//  fd      - dst reg, only used on 3 regs instr.
672//  fmt     - double or single precision.
673//  funct   - combined with opcode field give us an operation code.
674//
675//===----------------------------------------------------------------------===//
676
677//===----------------------------------------------------------------------===//
678// Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
679//===----------------------------------------------------------------------===//
680
681class ADDS_FM<bits<6> funct, bits<5> fmt> : StdArch {
682  bits<5> fd;
683  bits<5> fs;
684  bits<5> ft;
685
686  bits<32> Inst;
687
688  let Inst{31-26} = 0x11;
689  let Inst{25-21} = fmt;
690  let Inst{20-16} = ft;
691  let Inst{15-11} = fs;
692  let Inst{10-6}  = fd;
693  let Inst{5-0}   = funct;
694}
695
696class ABSS_FM<bits<6> funct, bits<5> fmt> : StdArch {
697  bits<5> fd;
698  bits<5> fs;
699
700  bits<32> Inst;
701
702  let Inst{31-26} = 0x11;
703  let Inst{25-21} = fmt;
704  let Inst{20-16} = 0;
705  let Inst{15-11} = fs;
706  let Inst{10-6}  = fd;
707  let Inst{5-0}   = funct;
708}
709
710class MFC1_FM<bits<5> funct> : StdArch {
711  bits<5> rt;
712  bits<5> fs;
713
714  bits<32> Inst;
715
716  let Inst{31-26} = 0x11;
717  let Inst{25-21} = funct;
718  let Inst{20-16} = rt;
719  let Inst{15-11} = fs;
720  let Inst{10-0}  = 0;
721}
722
723class LW_FM<bits<6> op> : StdArch {
724  bits<5> rt;
725  bits<21> addr;
726
727  bits<32> Inst;
728
729  let Inst{31-26} = op;
730  let Inst{25-21} = addr{20-16};
731  let Inst{20-16} = rt;
732  let Inst{15-0}  = addr{15-0};
733}
734
735class MADDS_FM<bits<3> funct, bits<3> fmt> : StdArch {
736  bits<5> fd;
737  bits<5> fr;
738  bits<5> fs;
739  bits<5> ft;
740
741  bits<32> Inst;
742
743  let Inst{31-26} = 0x13;
744  let Inst{25-21} = fr;
745  let Inst{20-16} = ft;
746  let Inst{15-11} = fs;
747  let Inst{10-6}  = fd;
748  let Inst{5-3}   = funct;
749  let Inst{2-0}   = fmt;
750}
751
752class LWXC1_FM<bits<6> funct> : StdArch {
753  bits<5> fd;
754  bits<5> base;
755  bits<5> index;
756
757  bits<32> Inst;
758
759  let Inst{31-26} = 0x13;
760  let Inst{25-21} = base;
761  let Inst{20-16} = index;
762  let Inst{15-11} = 0;
763  let Inst{10-6}  = fd;
764  let Inst{5-0}   = funct;
765}
766
767class SWXC1_FM<bits<6> funct> : StdArch {
768  bits<5> fs;
769  bits<5> base;
770  bits<5> index;
771
772  bits<32> Inst;
773
774  let Inst{31-26} = 0x13;
775  let Inst{25-21} = base;
776  let Inst{20-16} = index;
777  let Inst{15-11} = fs;
778  let Inst{10-6}  = 0;
779  let Inst{5-0}   = funct;
780}
781
782class BC1F_FM<bit nd, bit tf> : StdArch {
783  bits<3>  fcc;
784  bits<16> offset;
785
786  bits<32> Inst;
787
788  let Inst{31-26} = 0x11;
789  let Inst{25-21} = 0x8;
790  let Inst{20-18} = fcc;
791  let Inst{17} = nd;
792  let Inst{16} = tf;
793  let Inst{15-0} = offset;
794}
795
796class CEQS_FM<bits<5> fmt> : StdArch {
797  bits<5> fs;
798  bits<5> ft;
799  bits<3> fcc;
800  bits<4> cond;
801
802  bits<32> Inst;
803
804  let Inst{31-26} = 0x11;
805  let Inst{25-21} = fmt;
806  let Inst{20-16} = ft;
807  let Inst{15-11} = fs;
808  let Inst{10-8} = fcc;
809  let Inst{7-4} = 0x3;
810  let Inst{3-0} = cond;
811}
812
813class C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> {
814  let cond = c;
815}
816
817class CMov_I_F_FM<bits<6> funct, bits<5> fmt> : StdArch {
818  bits<5> fd;
819  bits<5> fs;
820  bits<5> rt;
821
822  bits<32> Inst;
823
824  let Inst{31-26} = 0x11;
825  let Inst{25-21} = fmt;
826  let Inst{20-16} = rt;
827  let Inst{15-11} = fs;
828  let Inst{10-6} = fd;
829  let Inst{5-0} = funct;
830}
831
832class CMov_F_I_FM<bit tf> : StdArch {
833  bits<5> rd;
834  bits<5> rs;
835  bits<3> fcc;
836
837  bits<32> Inst;
838
839  let Inst{31-26} = 0;
840  let Inst{25-21} = rs;
841  let Inst{20-18} = fcc;
842  let Inst{17} = 0;
843  let Inst{16} = tf;
844  let Inst{15-11} = rd;
845  let Inst{10-6} = 0;
846  let Inst{5-0} = 1;
847}
848
849class CMov_F_F_FM<bits<5> fmt, bit tf> : StdArch {
850  bits<5> fd;
851  bits<5> fs;
852  bits<3> fcc;
853
854  bits<32> Inst;
855
856  let Inst{31-26} = 0x11;
857  let Inst{25-21} = fmt;
858  let Inst{20-18} = fcc;
859  let Inst{17} = 0;
860  let Inst{16} = tf;
861  let Inst{15-11} = fs;
862  let Inst{10-6} = fd;
863  let Inst{5-0} = 0x11;
864}
865
866class BARRIER_FM<bits<5> op> : StdArch {
867  bits<32> Inst;
868
869  let Inst{31-26} = 0; // SPECIAL
870  let Inst{25-21} = 0;
871  let Inst{20-16} = 0; // rt = 0
872  let Inst{15-11} = 0; // rd = 0
873  let Inst{10-6} = op; // Operation
874  let Inst{5-0} = 0;   // SLL
875}
876
877class SDBBP_FM : StdArch {
878  bits<20> code_;
879
880  bits<32> Inst;
881
882  let Inst{31-26} = 0b011100; // SPECIAL2
883  let Inst{25-6} = code_;
884  let Inst{5-0} = 0b111111;   // SDBBP
885}
886
887class JR_HB_FM<bits<6> op> : StdArch{
888  bits<5> rs;
889
890  bits<32> Inst;
891
892  let Inst{31-26} = 0; // SPECIAL
893  let Inst{25-21} = rs;
894  let Inst{20-11} = 0;
895  let Inst{10} = 1;
896  let Inst{9-6} = 0;
897  let Inst{5-0} = op;
898}
899
900class JALR_HB_FM<bits<6> op> : StdArch {
901  bits<5> rd;
902  bits<5> rs;
903
904  bits<32> Inst;
905
906  let Inst{31-26} = 0; // SPECIAL
907  let Inst{25-21} = rs;
908  let Inst{20-16} = 0;
909  let Inst{15-11} = rd;
910  let Inst{10} = 1;
911  let Inst{9-6} = 0;
912  let Inst{5-0} = op;
913}
914
915class COP0_TLB_FM<bits<6> op> : StdArch {
916  bits<32> Inst;
917
918  let Inst{31-26} = 0x10; // COP0
919  let Inst{25} = 1;       // CO
920  let Inst{24-6} = 0;
921  let Inst{5-0} = op;     // Operation
922}
923
924class CACHEOP_FM<bits<6> op> : StdArch {
925  bits<21> addr;
926  bits<5> hint;
927  bits<5> base = addr{20-16};
928  bits<16> offset = addr{15-0};
929
930  bits<32> Inst;
931
932  let Inst{31-26} = op;
933  let Inst{25-21} = base;
934  let Inst{20-16} = hint;
935  let Inst{15-0}  = offset;
936}
937
938class HYPCALL_FM<bits<6> op> : StdArch {
939  bits<10> code_;
940
941  bits<32> Inst;
942
943  let Inst{31-26} = 0b010000;
944  let Inst{25}    = 1;
945  let Inst{20-11} = code_;
946  let Inst{5-0}   = op;
947}
948