1//===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10//  Describe MIPS instructions format
11//
12//  CPU INSTRUCTION FORMATS
13//
14//  opcode  - operation code.
15//  rs      - src reg.
16//  rt      - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
17//  rd      - dst reg, only used on 3 regs instr.
18//  shamt   - only used on shift instructions, contains the shift amount.
19//  funct   - combined with opcode field give us an operation code.
20//
21//===----------------------------------------------------------------------===//
22
23// Format specifies the encoding used by the instruction.  This is part of the
24// ad-hoc solution used to emit machine instruction encodings by our machine
25// code emitter.
26class Format<bits<4> val> {
27  bits<4> Value = val;
28}
29
30def Pseudo    : Format<0>;
31def FrmR      : Format<1>;
32def FrmI      : Format<2>;
33def FrmJ      : Format<3>;
34def FrmFR     : Format<4>;
35def FrmFI     : Format<5>;
36def FrmOther  : Format<6>; // Instruction w/ a custom format
37
38class MMRel;
39
40def Std2MicroMips : InstrMapping {
41  let FilterClass = "MMRel";
42  // Instructions with the same BaseOpcode and isNVStore values form a row.
43  let RowFields = ["BaseOpcode"];
44  // Instructions with the same predicate sense form a column.
45  let ColFields = ["Arch"];
46  // The key column is the unpredicated instructions.
47  let KeyCol = ["se"];
48  // Value columns are PredSense=true and PredSense=false
49  let ValueCols = [["se"], ["micromips"]];
50}
51
52class StdMMR6Rel;
53
54def Std2MicroMipsR6 : InstrMapping {
55  let FilterClass = "StdMMR6Rel";
56  // Instructions with the same BaseOpcode and isNVStore values form a row.
57  let RowFields = ["BaseOpcode"];
58  // Instructions with the same predicate sense form a column.
59  let ColFields = ["Arch"];
60  // The key column is the unpredicated instructions.
61  let KeyCol = ["se"];
62  // Value columns are PredSense=true and PredSense=false
63  let ValueCols = [["se"], ["micromipsr6"]];
64}
65
66class StdArch {
67  string Arch = "se";
68}
69
70// Generic Mips Format
71class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
72               InstrItinClass itin, Format f>: Instruction, PredicateControl
73{
74  field bits<32> Inst;
75  Format Form = f;
76
77  let Namespace = "Mips";
78
79  let Size = 4;
80
81  bits<6> Opcode = 0;
82
83  // Top 6 bits are the 'opcode' field
84  let Inst{31-26} = Opcode;
85
86  let OutOperandList = outs;
87  let InOperandList  = ins;
88
89  let AsmString   = asmstr;
90  let Pattern     = pattern;
91  let Itinerary   = itin;
92
93  //
94  // Attributes specific to Mips instructions...
95  //
96  bits<4> FormBits     = Form.Value;
97  bit isCTI            = 0; // Any form of Control Transfer Instruction.
98                            // Required for MIPSR6
99  bit hasForbiddenSlot = 0; // Instruction has a forbidden slot.
100  bit hasFCCRegOperand = 0; // Instruction uses $fcc<X> register and is
101                            // present in MIPS-I to MIPS-III.
102
103  // TSFlags layout should be kept in sync with MCTargetDesc/MipsBaseInfo.h.
104  let TSFlags{3-0}   = FormBits;
105  let TSFlags{4}     = isCTI;
106  let TSFlags{5}     = hasForbiddenSlot;
107  let TSFlags{6}     = hasFCCRegOperand;
108
109  let DecoderNamespace = "Mips";
110
111  field bits<32> SoftFail = 0;
112}
113
114// Mips32/64 Instruction Format
115class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
116             InstrItinClass itin, Format f, string opstr = ""> :
117  MipsInst<outs, ins, asmstr, pattern, itin, f> {
118  let EncodingPredicates = [NotInMips16Mode];
119  string BaseOpcode = opstr;
120  string Arch;
121}
122
123// Mips Pseudo Instructions Format
124class MipsPseudo<dag outs, dag ins, list<dag> pattern,
125                 InstrItinClass itin = IIPseudo> :
126  MipsInst<outs, ins, "", pattern, itin, Pseudo> {
127  let isCodeGenOnly = 1;
128  let isPseudo = 1;
129}
130
131// Mips32/64 Pseudo Instruction Format
132class PseudoSE<dag outs, dag ins, list<dag> pattern,
133               InstrItinClass itin = IIPseudo> :
134  MipsPseudo<outs, ins, pattern, itin> {
135  let EncodingPredicates = [NotInMips16Mode];
136}
137
138// Pseudo-instructions for alternate assembly syntax (never used by codegen).
139// These are aliases that require C++ handling to convert to the target
140// instruction, while InstAliases can be handled directly by tblgen.
141class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
142  MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
143  let isPseudo = 1;
144  let hasNoSchedulingInfo = 1;
145  let Pattern = [];
146}
147//===----------------------------------------------------------------------===//
148// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
149//===----------------------------------------------------------------------===//
150
151class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
152         list<dag> pattern, InstrItinClass itin>:
153  InstSE<outs, ins, asmstr, pattern, itin, FrmR>
154{
155  bits<5>  rd;
156  bits<5>  rs;
157  bits<5>  rt;
158  bits<5>  shamt;
159  bits<6>  funct;
160
161  let Opcode = op;
162  let funct  = _funct;
163
164  let Inst{25-21} = rs;
165  let Inst{20-16} = rt;
166  let Inst{15-11} = rd;
167  let Inst{10-6}  = shamt;
168  let Inst{5-0}   = funct;
169}
170
171//===----------------------------------------------------------------------===//
172// Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
173//===----------------------------------------------------------------------===//
174
175class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
176         InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI>
177{
178  bits<5>  rt;
179  bits<5>  rs;
180  bits<16> imm16;
181
182  let Opcode = op;
183
184  let Inst{25-21} = rs;
185  let Inst{20-16} = rt;
186  let Inst{15-0}  = imm16;
187}
188
189class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
190                  list<dag> pattern, InstrItinClass itin>:
191  InstSE<outs, ins, asmstr, pattern, itin, FrmI>
192{
193  bits<5>  rs;
194  bits<5>  rt;
195  bits<16> imm16;
196
197  let Opcode = op;
198
199  let Inst{25-21} = rs;
200  let Inst{20-16} = rt;
201  let Inst{15-0}  = imm16;
202}
203
204//===----------------------------------------------------------------------===//
205// Format J instruction class in Mips : <|opcode|address|>
206//===----------------------------------------------------------------------===//
207
208class FJ<bits<6> op> : StdArch
209{
210  bits<26> target;
211
212  bits<32> Inst;
213
214  let Inst{31-26} = op;
215  let Inst{25-0}  = target;
216}
217
218//===----------------------------------------------------------------------===//
219// MFC instruction class in Mips : <|op|mf|rt|rd|gst|0000|sel|>
220//===----------------------------------------------------------------------===//
221class MFC3OP_FM<bits<6> op, bits<5> mfmt, bits<3> guest> : StdArch {
222  bits<5> rt;
223  bits<5> rd;
224  bits<3> sel;
225
226  bits<32> Inst;
227
228  let Inst{31-26} = op;
229  let Inst{25-21} = mfmt;
230  let Inst{20-16} = rt;
231  let Inst{15-11} = rd;
232  let Inst{10-8}  = guest;
233  let Inst{7-3}   = 0;
234  let Inst{2-0}   = sel;
235}
236
237class MFC2OP_FM<bits<6> op, bits<5> mfmt> : StdArch {
238  bits<5>  rt;
239  bits<16> imm16;
240
241  bits<32> Inst;
242
243  let Inst{31-26} = op;
244  let Inst{25-21} = mfmt;
245  let Inst{20-16} = rt;
246  let Inst{15-0}  = imm16;
247}
248
249class ADD_FM<bits<6> op, bits<6> funct> : StdArch {
250  bits<5> rd;
251  bits<5> rs;
252  bits<5> rt;
253
254  bits<32> Inst;
255
256  let Inst{31-26} = op;
257  let Inst{25-21} = rs;
258  let Inst{20-16} = rt;
259  let Inst{15-11} = rd;
260  let Inst{10-6}  = 0;
261  let Inst{5-0}   = funct;
262}
263
264class ADDI_FM<bits<6> op> : StdArch {
265  bits<5>  rs;
266  bits<5>  rt;
267  bits<16> imm16;
268
269  bits<32> Inst;
270
271  let Inst{31-26} = op;
272  let Inst{25-21} = rs;
273  let Inst{20-16} = rt;
274  let Inst{15-0}  = imm16;
275}
276
277class SRA_FM<bits<6> funct, bit rotate> : StdArch {
278  bits<5> rd;
279  bits<5> rt;
280  bits<5> shamt;
281
282  bits<32> Inst;
283
284  let Inst{31-26} = 0;
285  let Inst{25-22} = 0;
286  let Inst{21}    = rotate;
287  let Inst{20-16} = rt;
288  let Inst{15-11} = rd;
289  let Inst{10-6}  = shamt;
290  let Inst{5-0}   = funct;
291}
292
293class SRLV_FM<bits<6> funct, bit rotate> : StdArch {
294  bits<5> rd;
295  bits<5> rt;
296  bits<5> rs;
297
298  bits<32> Inst;
299
300  let Inst{31-26} = 0;
301  let Inst{25-21} = rs;
302  let Inst{20-16} = rt;
303  let Inst{15-11} = rd;
304  let Inst{10-7}  = 0;
305  let Inst{6}     = rotate;
306  let Inst{5-0}   = funct;
307}
308
309class BEQ_FM<bits<6> op> : StdArch {
310  bits<5>  rs;
311  bits<5>  rt;
312  bits<16> offset;
313
314  bits<32> Inst;
315
316  let Inst{31-26} = op;
317  let Inst{25-21} = rs;
318  let Inst{20-16} = rt;
319  let Inst{15-0}  = offset;
320}
321
322class BGEZ_FM<bits<6> op, bits<5> funct> : StdArch {
323  bits<5>  rs;
324  bits<16> offset;
325
326  bits<32> Inst;
327
328  let Inst{31-26} = op;
329  let Inst{25-21} = rs;
330  let Inst{20-16} = funct;
331  let Inst{15-0}  = offset;
332}
333
334class BBIT_FM<bits<6> op> : StdArch {
335  bits<5>  rs;
336  bits<5>  p;
337  bits<16> offset;
338
339  bits<32> Inst;
340
341  let Inst{31-26} = op;
342  let Inst{25-21} = rs;
343  let Inst{20-16} = p;
344  let Inst{15-0}  = offset;
345}
346
347class SLTI_FM<bits<6> op> : StdArch {
348  bits<5> rt;
349  bits<5> rs;
350  bits<16> imm16;
351
352  bits<32> Inst;
353
354  let Inst{31-26} = op;
355  let Inst{25-21} = rs;
356  let Inst{20-16} = rt;
357  let Inst{15-0}  = imm16;
358}
359
360class MFLO_FM<bits<6> funct> : StdArch {
361  bits<5> rd;
362
363  bits<32> Inst;
364
365  let Inst{31-26} = 0;
366  let Inst{25-16} = 0;
367  let Inst{15-11} = rd;
368  let Inst{10-6}  = 0;
369  let Inst{5-0}   = funct;
370}
371
372class MTLO_FM<bits<6> funct> : StdArch {
373  bits<5> rs;
374
375  bits<32> Inst;
376
377  let Inst{31-26} = 0;
378  let Inst{25-21} = rs;
379  let Inst{20-6}  = 0;
380  let Inst{5-0}   = funct;
381}
382
383class SEB_FM<bits<5> funct, bits<6> funct2> : StdArch {
384  bits<5> rd;
385  bits<5> rt;
386
387  bits<32> Inst;
388
389  let Inst{31-26} = 0x1f;
390  let Inst{25-21} = 0;
391  let Inst{20-16} = rt;
392  let Inst{15-11} = rd;
393  let Inst{10-6}  = funct;
394  let Inst{5-0}   = funct2;
395}
396
397class CLO_FM<bits<6> funct> : StdArch {
398  bits<5> rd;
399  bits<5> rs;
400  bits<5> rt;
401
402  bits<32> Inst;
403
404  let Inst{31-26} = 0x1c;
405  let Inst{25-21} = rs;
406  let Inst{20-16} = rt;
407  let Inst{15-11} = rd;
408  let Inst{10-6}  = 0;
409  let Inst{5-0}   = funct;
410  let rt = rd;
411}
412
413class LUI_FM : StdArch {
414  bits<5> rt;
415  bits<16> imm16;
416
417  bits<32> Inst;
418
419  let Inst{31-26} = 0xf;
420  let Inst{25-21} = 0;
421  let Inst{20-16} = rt;
422  let Inst{15-0}  = imm16;
423}
424
425class JALR_FM {
426  bits<5> rd;
427  bits<5> rs;
428
429  bits<32> Inst;
430
431  let Inst{31-26} = 0;
432  let Inst{25-21} = rs;
433  let Inst{20-16} = 0;
434  let Inst{15-11} = rd;
435  let Inst{10-6}  = 0;
436  let Inst{5-0}   = 9;
437}
438
439class BGEZAL_FM<bits<5> funct> : StdArch {
440  bits<5>  rs;
441  bits<16> offset;
442
443  bits<32> Inst;
444
445  let Inst{31-26} = 1;
446  let Inst{25-21} = rs;
447  let Inst{20-16} = funct;
448  let Inst{15-0}  = offset;
449}
450
451class SYNC_FM : StdArch {
452  bits<5> stype;
453
454  bits<32> Inst;
455
456  let Inst{31-26} = 0;
457  let Inst{10-6}  = stype;
458  let Inst{5-0}   = 0xf;
459}
460
461class SYNCI_FM : StdArch {
462  // Produced by the mem_simm16 address as reg << 16 | imm (see getMemEncoding).
463  bits<21> addr;
464  bits<5> rs = addr{20-16};
465  bits<16> offset = addr{15-0};
466
467  bits<32> Inst;
468
469  let Inst{31-26} = 0b000001;
470  let Inst{25-21} = rs;
471  let Inst{20-16} = 0b11111;
472  let Inst{15-0}  = offset;
473}
474
475class MULT_FM<bits<6> op, bits<6> funct> : StdArch {
476  bits<5>  rs;
477  bits<5>  rt;
478
479  bits<32> Inst;
480
481  let Inst{31-26} = op;
482  let Inst{25-21} = rs;
483  let Inst{20-16} = rt;
484  let Inst{15-6}  = 0;
485  let Inst{5-0}   = funct;
486}
487
488class EXT_FM<bits<6> funct> : StdArch {
489  bits<5> rt;
490  bits<5> rs;
491  bits<5> pos;
492  bits<5> size;
493
494  bits<32> Inst;
495
496  let Inst{31-26} = 0x1f;
497  let Inst{25-21} = rs;
498  let Inst{20-16} = rt;
499  let Inst{15-11} = size;
500  let Inst{10-6}  = pos;
501  let Inst{5-0}   = funct;
502}
503
504class RDHWR_FM : StdArch {
505  bits<5> rt;
506  bits<5> rd;
507  bits<3> sel;
508
509  bits<32> Inst;
510
511  let Inst{31-26} = 0x1f;
512  let Inst{25-21} = 0;
513  let Inst{20-16} = rt;
514  let Inst{15-11} = rd;
515  let Inst{10-9}  = 0b00;
516  let Inst{8-6}   = sel;
517  let Inst{5-0}   = 0x3b;
518}
519
520class TEQ_FM<bits<6> funct> : StdArch {
521  bits<5> rs;
522  bits<5> rt;
523  bits<10> code_;
524
525  bits<32> Inst;
526
527  let Inst{31-26} = 0;
528  let Inst{25-21} = rs;
529  let Inst{20-16} = rt;
530  let Inst{15-6}  = code_;
531  let Inst{5-0}   = funct;
532}
533
534class TEQI_FM<bits<5> funct> : StdArch {
535  bits<5> rs;
536  bits<16> imm16;
537
538  bits<32> Inst;
539
540  let Inst{31-26} = 1;
541  let Inst{25-21} = rs;
542  let Inst{20-16}   = funct;
543  let Inst{15-0}  = imm16;
544}
545
546class WAIT_FM : StdArch {
547  bits<32> Inst;
548
549  let Inst{31-26} = 0x10;
550  let Inst{25}    = 1;
551  let Inst{24-6}  = 0;
552  let Inst{5-0}   = 0x20;
553}
554
555class EXTS_FM<bits<6> funct> : StdArch {
556  bits<5> rt;
557  bits<5> rs;
558  bits<5> pos;
559  bits<5> lenm1;
560
561  bits<32> Inst;
562
563  let Inst{31-26} = 0x1c;
564  let Inst{25-21} = rs;
565  let Inst{20-16} = rt;
566  let Inst{15-11} = lenm1;
567  let Inst{10-6}  = pos;
568  let Inst{5-0}   = funct;
569}
570
571class MTMR_FM<bits<6> funct> : StdArch {
572  bits<5> rs;
573
574  bits<32> Inst;
575
576  let Inst{31-26} = 0x1c;
577  let Inst{25-21} = rs;
578  let Inst{20-6}  = 0;
579  let Inst{5-0}   = funct;
580}
581
582class POP_FM<bits<6> funct> : StdArch {
583  bits<5> rd;
584  bits<5> rs;
585
586  bits<32> Inst;
587
588  let Inst{31-26} = 0x1c;
589  let Inst{25-21} = rs;
590  let Inst{20-16} = 0;
591  let Inst{15-11} = rd;
592  let Inst{10-6}  = 0;
593  let Inst{5-0}   = funct;
594}
595
596class SEQ_FM<bits<6> funct> : StdArch {
597  bits<5> rd;
598  bits<5> rs;
599  bits<5> rt;
600
601  bits<32> Inst;
602
603  let Inst{31-26} = 0x1c;
604  let Inst{25-21} = rs;
605  let Inst{20-16} = rt;
606  let Inst{15-11} = rd;
607  let Inst{10-6}  = 0;
608  let Inst{5-0}   = funct;
609}
610
611class SEQI_FM<bits<6> funct> : StdArch {
612  bits<5> rs;
613  bits<5> rt;
614  bits<10> imm10;
615
616  bits<32> Inst;
617
618  let Inst{31-26} = 0x1c;
619  let Inst{25-21} = rs;
620  let Inst{20-16} = rt;
621  let Inst{15-6}  = imm10;
622  let Inst{5-0}   = funct;
623}
624
625class SAA_FM<bits<6> funct> : StdArch {
626  bits<5> rt;
627  bits<5> rs;
628
629  bits<32> Inst;
630
631  let Inst{31-26} = 0x1c;
632  let Inst{25-21} = rs;
633  let Inst{20-16} = rt;
634  let Inst{15-6}  = 0;
635  let Inst{5-0}   = funct;
636}
637
638//===----------------------------------------------------------------------===//
639//  System calls format <op|code_|funct>
640//===----------------------------------------------------------------------===//
641
642class SYS_FM<bits<6> funct> : StdArch
643{
644  bits<20> code_;
645  bits<32> Inst;
646  let Inst{31-26} = 0x0;
647  let Inst{25-6} = code_;
648  let Inst{5-0}  = funct;
649}
650
651//===----------------------------------------------------------------------===//
652//  Break instruction format <op|code_1|funct>
653//===----------------------------------------------------------------------===//
654
655class BRK_FM<bits<6> funct> : StdArch
656{
657  bits<10> code_1;
658  bits<10> code_2;
659  bits<32> Inst;
660  let Inst{31-26} = 0x0;
661  let Inst{25-16} = code_1;
662  let Inst{15-6}  = code_2;
663  let Inst{5-0}   = funct;
664}
665
666//===----------------------------------------------------------------------===//
667//  Exception return format <Cop0|1|0|funct>
668//===----------------------------------------------------------------------===//
669
670class ER_FM<bits<6> funct, bit LLBit> : StdArch
671{
672  bits<32> Inst;
673  let Inst{31-26} = 0x10;
674  let Inst{25}    = 1;
675  let Inst{24-7}  = 0;
676  let Inst{6} = LLBit;
677  let Inst{5-0}   = funct;
678}
679
680//===----------------------------------------------------------------------===//
681//  Enable/disable interrupt instruction format <Cop0|MFMC0|rt|12|0|sc|0|0>
682//===----------------------------------------------------------------------===//
683
684class EI_FM<bits<1> sc> : StdArch
685{
686  bits<32> Inst;
687  bits<5> rt;
688  let Inst{31-26} = 0x10;
689  let Inst{25-21} = 0xb;
690  let Inst{20-16} = rt;
691  let Inst{15-11} = 0xc;
692  let Inst{10-6}  = 0;
693  let Inst{5}     = sc;
694  let Inst{4-0}   = 0;
695}
696
697//===----------------------------------------------------------------------===//
698//
699//  FLOATING POINT INSTRUCTION FORMATS
700//
701//  opcode  - operation code.
702//  fs      - src reg.
703//  ft      - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
704//  fd      - dst reg, only used on 3 regs instr.
705//  fmt     - double or single precision.
706//  funct   - combined with opcode field give us an operation code.
707//
708//===----------------------------------------------------------------------===//
709
710//===----------------------------------------------------------------------===//
711// Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
712//===----------------------------------------------------------------------===//
713
714class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
715  InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
716{
717  bits<5>  ft;
718  bits<5>  base;
719  bits<16> imm16;
720
721  let Opcode = op;
722
723  let Inst{25-21} = base;
724  let Inst{20-16} = ft;
725  let Inst{15-0}  = imm16;
726}
727
728class ADDS_FM<bits<6> funct, bits<5> fmt> : StdArch {
729  bits<5> fd;
730  bits<5> fs;
731  bits<5> ft;
732
733  bits<32> Inst;
734
735  let Inst{31-26} = 0x11;
736  let Inst{25-21} = fmt;
737  let Inst{20-16} = ft;
738  let Inst{15-11} = fs;
739  let Inst{10-6}  = fd;
740  let Inst{5-0}   = funct;
741}
742
743class ABSS_FM<bits<6> funct, bits<5> fmt> : StdArch {
744  bits<5> fd;
745  bits<5> fs;
746
747  bits<32> Inst;
748
749  let Inst{31-26} = 0x11;
750  let Inst{25-21} = fmt;
751  let Inst{20-16} = 0;
752  let Inst{15-11} = fs;
753  let Inst{10-6}  = fd;
754  let Inst{5-0}   = funct;
755}
756
757class MFC1_FM<bits<5> funct> : StdArch {
758  bits<5> rt;
759  bits<5> fs;
760
761  bits<32> Inst;
762
763  let Inst{31-26} = 0x11;
764  let Inst{25-21} = funct;
765  let Inst{20-16} = rt;
766  let Inst{15-11} = fs;
767  let Inst{10-0}  = 0;
768}
769
770class LW_FM<bits<6> op> : StdArch {
771  bits<5> rt;
772  bits<21> addr;
773
774  bits<32> Inst;
775
776  let Inst{31-26} = op;
777  let Inst{25-21} = addr{20-16};
778  let Inst{20-16} = rt;
779  let Inst{15-0}  = addr{15-0};
780}
781
782class MADDS_FM<bits<3> funct, bits<3> fmt> : StdArch {
783  bits<5> fd;
784  bits<5> fr;
785  bits<5> fs;
786  bits<5> ft;
787
788  bits<32> Inst;
789
790  let Inst{31-26} = 0x13;
791  let Inst{25-21} = fr;
792  let Inst{20-16} = ft;
793  let Inst{15-11} = fs;
794  let Inst{10-6}  = fd;
795  let Inst{5-3}   = funct;
796  let Inst{2-0}   = fmt;
797}
798
799class LWXC1_FM<bits<6> funct> : StdArch {
800  bits<5> fd;
801  bits<5> base;
802  bits<5> index;
803
804  bits<32> Inst;
805
806  let Inst{31-26} = 0x13;
807  let Inst{25-21} = base;
808  let Inst{20-16} = index;
809  let Inst{15-11} = 0;
810  let Inst{10-6}  = fd;
811  let Inst{5-0}   = funct;
812}
813
814class SWXC1_FM<bits<6> funct> : StdArch {
815  bits<5> fs;
816  bits<5> base;
817  bits<5> index;
818
819  bits<32> Inst;
820
821  let Inst{31-26} = 0x13;
822  let Inst{25-21} = base;
823  let Inst{20-16} = index;
824  let Inst{15-11} = fs;
825  let Inst{10-6}  = 0;
826  let Inst{5-0}   = funct;
827}
828
829class BC1F_FM<bit nd, bit tf> : StdArch {
830  bits<3>  fcc;
831  bits<16> offset;
832
833  bits<32> Inst;
834
835  let Inst{31-26} = 0x11;
836  let Inst{25-21} = 0x8;
837  let Inst{20-18} = fcc;
838  let Inst{17} = nd;
839  let Inst{16} = tf;
840  let Inst{15-0} = offset;
841}
842
843class CEQS_FM<bits<5> fmt> : StdArch {
844  bits<5> fs;
845  bits<5> ft;
846  bits<3> fcc;
847  bits<4> cond;
848
849  bits<32> Inst;
850
851  let Inst{31-26} = 0x11;
852  let Inst{25-21} = fmt;
853  let Inst{20-16} = ft;
854  let Inst{15-11} = fs;
855  let Inst{10-8} = fcc;
856  let Inst{7-4} = 0x3;
857  let Inst{3-0} = cond;
858}
859
860class C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> {
861  let cond = c;
862}
863
864class CMov_I_F_FM<bits<6> funct, bits<5> fmt> : StdArch {
865  bits<5> fd;
866  bits<5> fs;
867  bits<5> rt;
868
869  bits<32> Inst;
870
871  let Inst{31-26} = 0x11;
872  let Inst{25-21} = fmt;
873  let Inst{20-16} = rt;
874  let Inst{15-11} = fs;
875  let Inst{10-6} = fd;
876  let Inst{5-0} = funct;
877}
878
879class CMov_F_I_FM<bit tf> : StdArch {
880  bits<5> rd;
881  bits<5> rs;
882  bits<3> fcc;
883
884  bits<32> Inst;
885
886  let Inst{31-26} = 0;
887  let Inst{25-21} = rs;
888  let Inst{20-18} = fcc;
889  let Inst{17} = 0;
890  let Inst{16} = tf;
891  let Inst{15-11} = rd;
892  let Inst{10-6} = 0;
893  let Inst{5-0} = 1;
894}
895
896class CMov_F_F_FM<bits<5> fmt, bit tf> : StdArch {
897  bits<5> fd;
898  bits<5> fs;
899  bits<3> fcc;
900
901  bits<32> Inst;
902
903  let Inst{31-26} = 0x11;
904  let Inst{25-21} = fmt;
905  let Inst{20-18} = fcc;
906  let Inst{17} = 0;
907  let Inst{16} = tf;
908  let Inst{15-11} = fs;
909  let Inst{10-6} = fd;
910  let Inst{5-0} = 0x11;
911}
912
913class BARRIER_FM<bits<5> op> : StdArch {
914  bits<32> Inst;
915
916  let Inst{31-26} = 0; // SPECIAL
917  let Inst{25-21} = 0;
918  let Inst{20-16} = 0; // rt = 0
919  let Inst{15-11} = 0; // rd = 0
920  let Inst{10-6} = op; // Operation
921  let Inst{5-0} = 0;   // SLL
922}
923
924class SDBBP_FM : StdArch {
925  bits<20> code_;
926
927  bits<32> Inst;
928
929  let Inst{31-26} = 0b011100; // SPECIAL2
930  let Inst{25-6} = code_;
931  let Inst{5-0} = 0b111111;   // SDBBP
932}
933
934class JR_HB_FM<bits<6> op> : StdArch{
935  bits<5> rs;
936
937  bits<32> Inst;
938
939  let Inst{31-26} = 0; // SPECIAL
940  let Inst{25-21} = rs;
941  let Inst{20-11} = 0;
942  let Inst{10} = 1;
943  let Inst{9-6} = 0;
944  let Inst{5-0} = op;
945}
946
947class JALR_HB_FM<bits<6> op> : StdArch {
948  bits<5> rd;
949  bits<5> rs;
950
951  bits<32> Inst;
952
953  let Inst{31-26} = 0; // SPECIAL
954  let Inst{25-21} = rs;
955  let Inst{20-16} = 0;
956  let Inst{15-11} = rd;
957  let Inst{10} = 1;
958  let Inst{9-6} = 0;
959  let Inst{5-0} = op;
960}
961
962class COP0_TLB_FM<bits<6> op> : StdArch {
963  bits<32> Inst;
964
965  let Inst{31-26} = 0x10; // COP0
966  let Inst{25} = 1;       // CO
967  let Inst{24-6} = 0;
968  let Inst{5-0} = op;     // Operation
969}
970
971class CACHEOP_FM<bits<6> op> : StdArch {
972  bits<21> addr;
973  bits<5> hint;
974  bits<5> base = addr{20-16};
975  bits<16> offset = addr{15-0};
976
977  bits<32> Inst;
978
979  let Inst{31-26} = op;
980  let Inst{25-21} = base;
981  let Inst{20-16} = hint;
982  let Inst{15-0}  = offset;
983}
984
985class HYPCALL_FM<bits<6> op> : StdArch {
986  bits<10> code_;
987
988  bits<32> Inst;
989
990  let Inst{31-26} = 0b010000;
991  let Inst{25}    = 1;
992  let Inst{20-11} = code_;
993  let Inst{5-0}   = op;
994}
995