1 //===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the Mips implementation of the TargetInstrInfo class. 10 // 11 // FIXME: We need to override TargetInstrInfo::getInlineAsmLength method in 12 // order for MipsLongBranch pass to work correctly when the code has inline 13 // assembly. The returned value doesn't have to be the asm instruction's exact 14 // size in bytes; MipsLongBranch only expects it to be the correct upper bound. 15 //===----------------------------------------------------------------------===// 16 17 #ifndef LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H 18 #define LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H 19 20 #include "MCTargetDesc/MipsMCTargetDesc.h" 21 #include "Mips.h" 22 #include "MipsRegisterInfo.h" 23 #include "llvm/ADT/ArrayRef.h" 24 #include "llvm/CodeGen/MachineBasicBlock.h" 25 #include "llvm/CodeGen/MachineInstrBuilder.h" 26 #include "llvm/CodeGen/MachineMemOperand.h" 27 #include "llvm/CodeGen/TargetInstrInfo.h" 28 #include <cstdint> 29 30 #define GET_INSTRINFO_HEADER 31 #include "MipsGenInstrInfo.inc" 32 33 namespace llvm { 34 35 class MachineInstr; 36 class MachineOperand; 37 class MipsSubtarget; 38 class TargetRegisterClass; 39 class TargetRegisterInfo; 40 41 class MipsInstrInfo : public MipsGenInstrInfo { 42 virtual void anchor(); 43 44 protected: 45 const MipsSubtarget &Subtarget; 46 unsigned UncondBrOpc; 47 48 public: 49 enum BranchType { 50 BT_None, // Couldn't analyze branch. 51 BT_NoBranch, // No branches found. 52 BT_Uncond, // One unconditional branch. 53 BT_Cond, // One conditional branch. 54 BT_CondUncond, // A conditional branch followed by an unconditional branch. 55 BT_Indirect // One indirct branch. 56 }; 57 58 explicit MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc); 59 60 static const MipsInstrInfo *create(MipsSubtarget &STI); 61 62 /// Branch Analysis 63 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 64 MachineBasicBlock *&FBB, 65 SmallVectorImpl<MachineOperand> &Cond, 66 bool AllowModify) const override; 67 68 unsigned removeBranch(MachineBasicBlock &MBB, 69 int *BytesRemoved = nullptr) const override; 70 71 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 72 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 73 const DebugLoc &DL, 74 int *BytesAdded = nullptr) const override; 75 76 bool 77 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 78 79 BranchType analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 80 MachineBasicBlock *&FBB, 81 SmallVectorImpl<MachineOperand> &Cond, 82 bool AllowModify, 83 SmallVectorImpl<MachineInstr *> &BranchInstrs) const; 84 85 /// Determine the opcode of a non-delay slot form for a branch if one exists. 86 unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const; 87 88 /// Determine if the branch target is in range. 89 bool isBranchOffsetInRange(unsigned BranchOpc, 90 int64_t BrOffset) const override; 91 92 /// Predicate to determine if an instruction can go in a forbidden slot. 93 bool SafeInForbiddenSlot(const MachineInstr &MI) const; 94 95 /// Predicate to determine if an instruction can go in an FPU delay slot. 96 bool SafeInFPUDelaySlot(const MachineInstr &MIInSlot, 97 const MachineInstr &FPUMI) const; 98 99 /// Predicate to determine if an instruction can go in a load delay slot. 100 bool SafeInLoadDelaySlot(const MachineInstr &MIInSlot, 101 const MachineInstr &LoadMI) const; 102 103 /// Predicate to determine if an instruction has a forbidden slot. 104 bool HasForbiddenSlot(const MachineInstr &MI) const; 105 106 /// Predicate to determine if an instruction has an FPU delay slot. 107 bool HasFPUDelaySlot(const MachineInstr &MI) const; 108 109 /// Predicate to determine if an instruction has a load delay slot. 110 bool HasLoadDelaySlot(const MachineInstr &MI) const; 111 112 /// Insert nop instruction when hazard condition is found 113 void insertNoop(MachineBasicBlock &MBB, 114 MachineBasicBlock::iterator MI) const override; 115 116 /// Insert an ISA appropriate `nop`. 117 // FIXME: Add support for MIPS16e. 118 MachineInstrBuilder insertNop(MachineBasicBlock &MBB, 119 MachineBasicBlock::iterator MI, 120 DebugLoc DL) const; 121 122 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 123 /// such, whenever a client has an instance of instruction info, it should 124 /// always be able to get register info as well (through this method). 125 virtual const MipsRegisterInfo &getRegisterInfo() const = 0; 126 127 virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0; 128 129 virtual bool isBranchWithImm(unsigned Opc) const { 130 return false; 131 } 132 133 /// Return the number of bytes of code the specified instruction may be. 134 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 135 136 void storeRegToStackSlot(MachineBasicBlock &MBB, 137 MachineBasicBlock::iterator MBBI, 138 Register SrcReg, bool isKill, int FrameIndex, 139 const TargetRegisterClass *RC, 140 const TargetRegisterInfo *TRI) const override { 141 storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0); 142 } 143 144 void loadRegFromStackSlot(MachineBasicBlock &MBB, 145 MachineBasicBlock::iterator MBBI, 146 Register DestReg, int FrameIndex, 147 const TargetRegisterClass *RC, 148 const TargetRegisterInfo *TRI) const override { 149 loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0); 150 } 151 152 virtual void storeRegToStack(MachineBasicBlock &MBB, 153 MachineBasicBlock::iterator MI, 154 Register SrcReg, bool isKill, int FrameIndex, 155 const TargetRegisterClass *RC, 156 const TargetRegisterInfo *TRI, 157 int64_t Offset) const = 0; 158 159 virtual void loadRegFromStack(MachineBasicBlock &MBB, 160 MachineBasicBlock::iterator MI, 161 Register DestReg, int FrameIndex, 162 const TargetRegisterClass *RC, 163 const TargetRegisterInfo *TRI, 164 int64_t Offset) const = 0; 165 166 virtual void adjustStackPtr(unsigned SP, int64_t Amount, 167 MachineBasicBlock &MBB, 168 MachineBasicBlock::iterator I) const = 0; 169 170 /// Create an instruction which has the same operands and memory operands 171 /// as MI but has a new opcode. 172 MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc, 173 MachineBasicBlock::iterator I) const; 174 175 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, 176 unsigned &SrcOpIdx2) const override; 177 178 /// Perform target specific instruction verification. 179 bool verifyInstruction(const MachineInstr &MI, 180 StringRef &ErrInfo) const override; 181 182 std::pair<unsigned, unsigned> 183 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 184 185 ArrayRef<std::pair<unsigned, const char *>> 186 getSerializableDirectMachineOperandTargetFlags() const override; 187 188 Optional<RegImmPair> isAddImmediate(const MachineInstr &MI, 189 Register Reg) const override; 190 191 Optional<ParamLoadedValue> describeLoadedValue(const MachineInstr &MI, 192 Register Reg) const override; 193 194 protected: 195 bool isZeroImm(const MachineOperand &op) const; 196 197 MachineMemOperand *GetMemOperand(MachineBasicBlock &MBB, int FI, 198 MachineMemOperand::Flags Flags) const; 199 200 private: 201 virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0; 202 203 void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc, 204 MachineBasicBlock *&BB, 205 SmallVectorImpl<MachineOperand> &Cond) const; 206 207 void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 208 const DebugLoc &DL, ArrayRef<MachineOperand> Cond) const; 209 }; 210 211 /// Create MipsInstrInfo objects. 212 const MipsInstrInfo *createMips16InstrInfo(const MipsSubtarget &STI); 213 const MipsInstrInfo *createMipsSEInstrInfo(const MipsSubtarget &STI); 214 215 } // end namespace llvm 216 217 #endif // LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H 218