10b57cec5SDimitry Andric//===- MipsMSAInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric 90b57cec5SDimitry Andricclass MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, 100b57cec5SDimitry Andric ASE_MSA { 110b57cec5SDimitry Andric let EncodingPredicates = [HasStdEnc]; 120b57cec5SDimitry Andric let Inst{31-26} = 0b011110; 130b57cec5SDimitry Andric} 140b57cec5SDimitry Andric 150b57cec5SDimitry Andricclass MSACBranch : MSAInst { 160b57cec5SDimitry Andric let Inst{31-26} = 0b010001; 170b57cec5SDimitry Andric} 180b57cec5SDimitry Andric 190b57cec5SDimitry Andricclass MSASpecial : MSAInst { 200b57cec5SDimitry Andric let Inst{31-26} = 0b000000; 210b57cec5SDimitry Andric} 220b57cec5SDimitry Andric 230b57cec5SDimitry Andricclass MSAPseudo<dag outs, dag ins, list<dag> pattern, 240b57cec5SDimitry Andric InstrItinClass itin = IIPseudo>: 250b57cec5SDimitry Andric MipsPseudo<outs, ins, pattern, itin> { 260b57cec5SDimitry Andric let EncodingPredicates = [HasStdEnc]; 270b57cec5SDimitry Andric let ASEPredicate = [HasMSA]; 280b57cec5SDimitry Andric} 290b57cec5SDimitry Andric 300b57cec5SDimitry Andricclass MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst { 310b57cec5SDimitry Andric bits<5> ws; 320b57cec5SDimitry Andric bits<5> wd; 330b57cec5SDimitry Andric bits<3> m; 340b57cec5SDimitry Andric 350b57cec5SDimitry Andric let Inst{25-23} = major; 360b57cec5SDimitry Andric let Inst{22-19} = 0b1110; 370b57cec5SDimitry Andric let Inst{18-16} = m; 380b57cec5SDimitry Andric let Inst{15-11} = ws; 390b57cec5SDimitry Andric let Inst{10-6} = wd; 400b57cec5SDimitry Andric let Inst{5-0} = minor; 410b57cec5SDimitry Andric} 420b57cec5SDimitry Andric 430b57cec5SDimitry Andricclass MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst { 440b57cec5SDimitry Andric bits<5> ws; 450b57cec5SDimitry Andric bits<5> wd; 460b57cec5SDimitry Andric bits<4> m; 470b57cec5SDimitry Andric 480b57cec5SDimitry Andric let Inst{25-23} = major; 490b57cec5SDimitry Andric let Inst{22-20} = 0b110; 500b57cec5SDimitry Andric let Inst{19-16} = m; 510b57cec5SDimitry Andric let Inst{15-11} = ws; 520b57cec5SDimitry Andric let Inst{10-6} = wd; 530b57cec5SDimitry Andric let Inst{5-0} = minor; 540b57cec5SDimitry Andric} 550b57cec5SDimitry Andric 560b57cec5SDimitry Andricclass MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst { 570b57cec5SDimitry Andric bits<5> ws; 580b57cec5SDimitry Andric bits<5> wd; 590b57cec5SDimitry Andric bits<5> m; 600b57cec5SDimitry Andric 610b57cec5SDimitry Andric let Inst{25-23} = major; 620b57cec5SDimitry Andric let Inst{22-21} = 0b10; 630b57cec5SDimitry Andric let Inst{20-16} = m; 640b57cec5SDimitry Andric let Inst{15-11} = ws; 650b57cec5SDimitry Andric let Inst{10-6} = wd; 660b57cec5SDimitry Andric let Inst{5-0} = minor; 670b57cec5SDimitry Andric} 680b57cec5SDimitry Andric 690b57cec5SDimitry Andricclass MSA_BIT_D_FMT<bits<3> major, bits<6> minor>: MSAInst { 700b57cec5SDimitry Andric bits<5> ws; 710b57cec5SDimitry Andric bits<5> wd; 720b57cec5SDimitry Andric bits<6> m; 730b57cec5SDimitry Andric 740b57cec5SDimitry Andric let Inst{25-23} = major; 750b57cec5SDimitry Andric let Inst{22} = 0b0; 760b57cec5SDimitry Andric let Inst{21-16} = m; 770b57cec5SDimitry Andric let Inst{15-11} = ws; 780b57cec5SDimitry Andric let Inst{10-6} = wd; 790b57cec5SDimitry Andric let Inst{5-0} = minor; 800b57cec5SDimitry Andric} 810b57cec5SDimitry Andric 820b57cec5SDimitry Andricclass MSA_2R_FILL_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst { 830b57cec5SDimitry Andric bits<5> rs; 840b57cec5SDimitry Andric bits<5> wd; 850b57cec5SDimitry Andric 860b57cec5SDimitry Andric let Inst{25-18} = major; 870b57cec5SDimitry Andric let Inst{17-16} = df; 880b57cec5SDimitry Andric let Inst{15-11} = rs; 890b57cec5SDimitry Andric let Inst{10-6} = wd; 900b57cec5SDimitry Andric let Inst{5-0} = minor; 910b57cec5SDimitry Andric} 920b57cec5SDimitry Andric 930b57cec5SDimitry Andricclass MSA_2R_FILL_D_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst { 940b57cec5SDimitry Andric bits<5> rs; 950b57cec5SDimitry Andric bits<5> wd; 960b57cec5SDimitry Andric 970b57cec5SDimitry Andric let Inst{25-18} = major; 980b57cec5SDimitry Andric let Inst{17-16} = df; 990b57cec5SDimitry Andric let Inst{15-11} = rs; 1000b57cec5SDimitry Andric let Inst{10-6} = wd; 1010b57cec5SDimitry Andric let Inst{5-0} = minor; 1020b57cec5SDimitry Andric} 1030b57cec5SDimitry Andric 1040b57cec5SDimitry Andricclass MSA_2R_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst { 1050b57cec5SDimitry Andric bits<5> ws; 1060b57cec5SDimitry Andric bits<5> wd; 1070b57cec5SDimitry Andric 1080b57cec5SDimitry Andric let Inst{25-18} = major; 1090b57cec5SDimitry Andric let Inst{17-16} = df; 1100b57cec5SDimitry Andric let Inst{15-11} = ws; 1110b57cec5SDimitry Andric let Inst{10-6} = wd; 1120b57cec5SDimitry Andric let Inst{5-0} = minor; 1130b57cec5SDimitry Andric} 1140b57cec5SDimitry Andric 1150b57cec5SDimitry Andricclass MSA_2RF_FMT<bits<9> major, bits<1> df, bits<6> minor>: MSAInst { 1160b57cec5SDimitry Andric bits<5> ws; 1170b57cec5SDimitry Andric bits<5> wd; 1180b57cec5SDimitry Andric 1190b57cec5SDimitry Andric let Inst{25-17} = major; 1200b57cec5SDimitry Andric let Inst{16} = df; 1210b57cec5SDimitry Andric let Inst{15-11} = ws; 1220b57cec5SDimitry Andric let Inst{10-6} = wd; 1230b57cec5SDimitry Andric let Inst{5-0} = minor; 1240b57cec5SDimitry Andric} 1250b57cec5SDimitry Andric 1260b57cec5SDimitry Andricclass MSA_3R_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst { 1270b57cec5SDimitry Andric bits<5> wt; 1280b57cec5SDimitry Andric bits<5> ws; 1290b57cec5SDimitry Andric bits<5> wd; 1300b57cec5SDimitry Andric 1310b57cec5SDimitry Andric let Inst{25-23} = major; 1320b57cec5SDimitry Andric let Inst{22-21} = df; 1330b57cec5SDimitry Andric let Inst{20-16} = wt; 1340b57cec5SDimitry Andric let Inst{15-11} = ws; 1350b57cec5SDimitry Andric let Inst{10-6} = wd; 1360b57cec5SDimitry Andric let Inst{5-0} = minor; 1370b57cec5SDimitry Andric} 1380b57cec5SDimitry Andric 1390b57cec5SDimitry Andricclass MSA_3RF_FMT<bits<4> major, bits<1> df, bits<6> minor>: MSAInst { 1400b57cec5SDimitry Andric bits<5> wt; 1410b57cec5SDimitry Andric bits<5> ws; 1420b57cec5SDimitry Andric bits<5> wd; 1430b57cec5SDimitry Andric 1440b57cec5SDimitry Andric let Inst{25-22} = major; 1450b57cec5SDimitry Andric let Inst{21} = df; 1460b57cec5SDimitry Andric let Inst{20-16} = wt; 1470b57cec5SDimitry Andric let Inst{15-11} = ws; 1480b57cec5SDimitry Andric let Inst{10-6} = wd; 1490b57cec5SDimitry Andric let Inst{5-0} = minor; 1500b57cec5SDimitry Andric} 1510b57cec5SDimitry Andric 1520b57cec5SDimitry Andricclass MSA_3R_INDEX_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst { 1530b57cec5SDimitry Andric bits<5> rt; 1540b57cec5SDimitry Andric bits<5> ws; 1550b57cec5SDimitry Andric bits<5> wd; 1560b57cec5SDimitry Andric 1570b57cec5SDimitry Andric let Inst{25-23} = major; 1580b57cec5SDimitry Andric let Inst{22-21} = df; 1590b57cec5SDimitry Andric let Inst{20-16} = rt; 1600b57cec5SDimitry Andric let Inst{15-11} = ws; 1610b57cec5SDimitry Andric let Inst{10-6} = wd; 1620b57cec5SDimitry Andric let Inst{5-0} = minor; 1630b57cec5SDimitry Andric} 1640b57cec5SDimitry Andric 1650b57cec5SDimitry Andricclass MSA_ELM_FMT<bits<10> major, bits<6> minor>: MSAInst { 1660b57cec5SDimitry Andric bits<5> ws; 1670b57cec5SDimitry Andric bits<5> wd; 1680b57cec5SDimitry Andric 1690b57cec5SDimitry Andric let Inst{25-16} = major; 1700b57cec5SDimitry Andric let Inst{15-11} = ws; 1710b57cec5SDimitry Andric let Inst{10-6} = wd; 1720b57cec5SDimitry Andric let Inst{5-0} = minor; 1730b57cec5SDimitry Andric} 1740b57cec5SDimitry Andric 1750b57cec5SDimitry Andricclass MSA_ELM_CFCMSA_FMT<bits<10> major, bits<6> minor>: MSAInst { 1760b57cec5SDimitry Andric bits<5> rd; 1770b57cec5SDimitry Andric bits<5> cs; 1780b57cec5SDimitry Andric 1790b57cec5SDimitry Andric let Inst{25-16} = major; 1800b57cec5SDimitry Andric let Inst{15-11} = cs; 1810b57cec5SDimitry Andric let Inst{10-6} = rd; 1820b57cec5SDimitry Andric let Inst{5-0} = minor; 1830b57cec5SDimitry Andric} 1840b57cec5SDimitry Andric 1850b57cec5SDimitry Andricclass MSA_ELM_CTCMSA_FMT<bits<10> major, bits<6> minor>: MSAInst { 1860b57cec5SDimitry Andric bits<5> rs; 1870b57cec5SDimitry Andric bits<5> cd; 1880b57cec5SDimitry Andric 1890b57cec5SDimitry Andric let Inst{25-16} = major; 1900b57cec5SDimitry Andric let Inst{15-11} = rs; 1910b57cec5SDimitry Andric let Inst{10-6} = cd; 1920b57cec5SDimitry Andric let Inst{5-0} = minor; 1930b57cec5SDimitry Andric} 1940b57cec5SDimitry Andric 1950b57cec5SDimitry Andricclass MSA_ELM_B_FMT<bits<4> major, bits<6> minor>: MSAInst { 1960b57cec5SDimitry Andric bits<4> n; 1970b57cec5SDimitry Andric bits<5> ws; 1980b57cec5SDimitry Andric bits<5> wd; 1990b57cec5SDimitry Andric 2000b57cec5SDimitry Andric let Inst{25-22} = major; 2010b57cec5SDimitry Andric let Inst{21-20} = 0b00; 2020b57cec5SDimitry Andric let Inst{19-16} = n{3-0}; 2030b57cec5SDimitry Andric let Inst{15-11} = ws; 2040b57cec5SDimitry Andric let Inst{10-6} = wd; 2050b57cec5SDimitry Andric let Inst{5-0} = minor; 2060b57cec5SDimitry Andric} 2070b57cec5SDimitry Andric 2080b57cec5SDimitry Andricclass MSA_ELM_H_FMT<bits<4> major, bits<6> minor>: MSAInst { 2090b57cec5SDimitry Andric bits<4> n; 2100b57cec5SDimitry Andric bits<5> ws; 2110b57cec5SDimitry Andric bits<5> wd; 2120b57cec5SDimitry Andric 2130b57cec5SDimitry Andric let Inst{25-22} = major; 2140b57cec5SDimitry Andric let Inst{21-19} = 0b100; 2150b57cec5SDimitry Andric let Inst{18-16} = n{2-0}; 2160b57cec5SDimitry Andric let Inst{15-11} = ws; 2170b57cec5SDimitry Andric let Inst{10-6} = wd; 2180b57cec5SDimitry Andric let Inst{5-0} = minor; 2190b57cec5SDimitry Andric} 2200b57cec5SDimitry Andric 2210b57cec5SDimitry Andricclass MSA_ELM_W_FMT<bits<4> major, bits<6> minor>: MSAInst { 2220b57cec5SDimitry Andric bits<4> n; 2230b57cec5SDimitry Andric bits<5> ws; 2240b57cec5SDimitry Andric bits<5> wd; 2250b57cec5SDimitry Andric 2260b57cec5SDimitry Andric let Inst{25-22} = major; 2270b57cec5SDimitry Andric let Inst{21-18} = 0b1100; 2280b57cec5SDimitry Andric let Inst{17-16} = n{1-0}; 2290b57cec5SDimitry Andric let Inst{15-11} = ws; 2300b57cec5SDimitry Andric let Inst{10-6} = wd; 2310b57cec5SDimitry Andric let Inst{5-0} = minor; 2320b57cec5SDimitry Andric} 2330b57cec5SDimitry Andric 2340b57cec5SDimitry Andricclass MSA_ELM_D_FMT<bits<4> major, bits<6> minor>: MSAInst { 2350b57cec5SDimitry Andric bits<4> n; 2360b57cec5SDimitry Andric bits<5> ws; 2370b57cec5SDimitry Andric bits<5> wd; 2380b57cec5SDimitry Andric 2390b57cec5SDimitry Andric let Inst{25-22} = major; 2400b57cec5SDimitry Andric let Inst{21-17} = 0b11100; 2410b57cec5SDimitry Andric let Inst{16} = n{0}; 2420b57cec5SDimitry Andric let Inst{15-11} = ws; 2430b57cec5SDimitry Andric let Inst{10-6} = wd; 2440b57cec5SDimitry Andric let Inst{5-0} = minor; 2450b57cec5SDimitry Andric} 2460b57cec5SDimitry Andric 2470b57cec5SDimitry Andricclass MSA_ELM_COPY_B_FMT<bits<4> major, bits<6> minor>: MSAInst { 2480b57cec5SDimitry Andric bits<4> n; 2490b57cec5SDimitry Andric bits<5> ws; 2500b57cec5SDimitry Andric bits<5> rd; 2510b57cec5SDimitry Andric 2520b57cec5SDimitry Andric let Inst{25-22} = major; 2530b57cec5SDimitry Andric let Inst{21-20} = 0b00; 2540b57cec5SDimitry Andric let Inst{19-16} = n{3-0}; 2550b57cec5SDimitry Andric let Inst{15-11} = ws; 2560b57cec5SDimitry Andric let Inst{10-6} = rd; 2570b57cec5SDimitry Andric let Inst{5-0} = minor; 2580b57cec5SDimitry Andric} 2590b57cec5SDimitry Andric 2600b57cec5SDimitry Andricclass MSA_ELM_COPY_H_FMT<bits<4> major, bits<6> minor>: MSAInst { 2610b57cec5SDimitry Andric bits<4> n; 2620b57cec5SDimitry Andric bits<5> ws; 2630b57cec5SDimitry Andric bits<5> rd; 2640b57cec5SDimitry Andric 2650b57cec5SDimitry Andric let Inst{25-22} = major; 2660b57cec5SDimitry Andric let Inst{21-19} = 0b100; 2670b57cec5SDimitry Andric let Inst{18-16} = n{2-0}; 2680b57cec5SDimitry Andric let Inst{15-11} = ws; 2690b57cec5SDimitry Andric let Inst{10-6} = rd; 2700b57cec5SDimitry Andric let Inst{5-0} = minor; 2710b57cec5SDimitry Andric} 2720b57cec5SDimitry Andric 2730b57cec5SDimitry Andricclass MSA_ELM_COPY_W_FMT<bits<4> major, bits<6> minor>: MSAInst { 2740b57cec5SDimitry Andric bits<4> n; 2750b57cec5SDimitry Andric bits<5> ws; 2760b57cec5SDimitry Andric bits<5> rd; 2770b57cec5SDimitry Andric 2780b57cec5SDimitry Andric let Inst{25-22} = major; 2790b57cec5SDimitry Andric let Inst{21-18} = 0b1100; 2800b57cec5SDimitry Andric let Inst{17-16} = n{1-0}; 2810b57cec5SDimitry Andric let Inst{15-11} = ws; 2820b57cec5SDimitry Andric let Inst{10-6} = rd; 2830b57cec5SDimitry Andric let Inst{5-0} = minor; 2840b57cec5SDimitry Andric} 2850b57cec5SDimitry Andric 2860b57cec5SDimitry Andricclass MSA_ELM_COPY_D_FMT<bits<4> major, bits<6> minor>: MSAInst { 2870b57cec5SDimitry Andric bits<4> n; 2880b57cec5SDimitry Andric bits<5> ws; 2890b57cec5SDimitry Andric bits<5> rd; 2900b57cec5SDimitry Andric 2910b57cec5SDimitry Andric let Inst{25-22} = major; 2920b57cec5SDimitry Andric let Inst{21-17} = 0b11100; 2930b57cec5SDimitry Andric let Inst{16} = n{0}; 2940b57cec5SDimitry Andric let Inst{15-11} = ws; 2950b57cec5SDimitry Andric let Inst{10-6} = rd; 2960b57cec5SDimitry Andric let Inst{5-0} = minor; 2970b57cec5SDimitry Andric} 2980b57cec5SDimitry Andric 2990b57cec5SDimitry Andricclass MSA_ELM_INSERT_B_FMT<bits<4> major, bits<6> minor>: MSAInst { 3000b57cec5SDimitry Andric bits<6> n; 3010b57cec5SDimitry Andric bits<5> rs; 3020b57cec5SDimitry Andric bits<5> wd; 3030b57cec5SDimitry Andric 3040b57cec5SDimitry Andric let Inst{25-22} = major; 3050b57cec5SDimitry Andric let Inst{21-20} = 0b00; 3060b57cec5SDimitry Andric let Inst{19-16} = n{3-0}; 3070b57cec5SDimitry Andric let Inst{15-11} = rs; 3080b57cec5SDimitry Andric let Inst{10-6} = wd; 3090b57cec5SDimitry Andric let Inst{5-0} = minor; 3100b57cec5SDimitry Andric} 3110b57cec5SDimitry Andric 3120b57cec5SDimitry Andricclass MSA_ELM_INSERT_H_FMT<bits<4> major, bits<6> minor>: MSAInst { 3130b57cec5SDimitry Andric bits<6> n; 3140b57cec5SDimitry Andric bits<5> rs; 3150b57cec5SDimitry Andric bits<5> wd; 3160b57cec5SDimitry Andric 3170b57cec5SDimitry Andric let Inst{25-22} = major; 3180b57cec5SDimitry Andric let Inst{21-19} = 0b100; 3190b57cec5SDimitry Andric let Inst{18-16} = n{2-0}; 3200b57cec5SDimitry Andric let Inst{15-11} = rs; 3210b57cec5SDimitry Andric let Inst{10-6} = wd; 3220b57cec5SDimitry Andric let Inst{5-0} = minor; 3230b57cec5SDimitry Andric} 3240b57cec5SDimitry Andric 3250b57cec5SDimitry Andricclass MSA_ELM_INSERT_W_FMT<bits<4> major, bits<6> minor>: MSAInst { 3260b57cec5SDimitry Andric bits<6> n; 3270b57cec5SDimitry Andric bits<5> rs; 3280b57cec5SDimitry Andric bits<5> wd; 3290b57cec5SDimitry Andric 3300b57cec5SDimitry Andric let Inst{25-22} = major; 3310b57cec5SDimitry Andric let Inst{21-18} = 0b1100; 3320b57cec5SDimitry Andric let Inst{17-16} = n{1-0}; 3330b57cec5SDimitry Andric let Inst{15-11} = rs; 3340b57cec5SDimitry Andric let Inst{10-6} = wd; 3350b57cec5SDimitry Andric let Inst{5-0} = minor; 3360b57cec5SDimitry Andric} 3370b57cec5SDimitry Andric 3380b57cec5SDimitry Andricclass MSA_ELM_INSERT_D_FMT<bits<4> major, bits<6> minor>: MSAInst { 3390b57cec5SDimitry Andric bits<6> n; 3400b57cec5SDimitry Andric bits<5> rs; 3410b57cec5SDimitry Andric bits<5> wd; 3420b57cec5SDimitry Andric 3430b57cec5SDimitry Andric let Inst{25-22} = major; 3440b57cec5SDimitry Andric let Inst{21-17} = 0b11100; 3450b57cec5SDimitry Andric let Inst{16} = n{0}; 3460b57cec5SDimitry Andric let Inst{15-11} = rs; 3470b57cec5SDimitry Andric let Inst{10-6} = wd; 3480b57cec5SDimitry Andric let Inst{5-0} = minor; 3490b57cec5SDimitry Andric} 3500b57cec5SDimitry Andric 3510b57cec5SDimitry Andricclass MSA_I5_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst { 3520b57cec5SDimitry Andric bits<5> imm; 3530b57cec5SDimitry Andric bits<5> ws; 3540b57cec5SDimitry Andric bits<5> wd; 3550b57cec5SDimitry Andric 3560b57cec5SDimitry Andric let Inst{25-23} = major; 3570b57cec5SDimitry Andric let Inst{22-21} = df; 3580b57cec5SDimitry Andric let Inst{20-16} = imm; 3590b57cec5SDimitry Andric let Inst{15-11} = ws; 3600b57cec5SDimitry Andric let Inst{10-6} = wd; 3610b57cec5SDimitry Andric let Inst{5-0} = minor; 3620b57cec5SDimitry Andric} 3630b57cec5SDimitry Andric 3640b57cec5SDimitry Andricclass MSA_I8_FMT<bits<2> major, bits<6> minor>: MSAInst { 3650b57cec5SDimitry Andric bits<8> u8; 3660b57cec5SDimitry Andric bits<5> ws; 3670b57cec5SDimitry Andric bits<5> wd; 3680b57cec5SDimitry Andric 3690b57cec5SDimitry Andric let Inst{25-24} = major; 3700b57cec5SDimitry Andric let Inst{23-16} = u8; 3710b57cec5SDimitry Andric let Inst{15-11} = ws; 3720b57cec5SDimitry Andric let Inst{10-6} = wd; 3730b57cec5SDimitry Andric let Inst{5-0} = minor; 3740b57cec5SDimitry Andric} 3750b57cec5SDimitry Andric 3760b57cec5SDimitry Andricclass MSA_I10_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst { 3770b57cec5SDimitry Andric bits<10> s10; 3780b57cec5SDimitry Andric bits<5> wd; 3790b57cec5SDimitry Andric 3800b57cec5SDimitry Andric let Inst{25-23} = major; 3810b57cec5SDimitry Andric let Inst{22-21} = df; 3820b57cec5SDimitry Andric let Inst{20-11} = s10; 3830b57cec5SDimitry Andric let Inst{10-6} = wd; 3840b57cec5SDimitry Andric let Inst{5-0} = minor; 3850b57cec5SDimitry Andric} 3860b57cec5SDimitry Andric 3870b57cec5SDimitry Andricclass MSA_MI10_FMT<bits<2> df, bits<4> minor>: MSAInst { 3880b57cec5SDimitry Andric bits<21> addr; 3890b57cec5SDimitry Andric bits<5> wd; 3900b57cec5SDimitry Andric 3910b57cec5SDimitry Andric let Inst{25-16} = addr{9-0}; 3920b57cec5SDimitry Andric let Inst{15-11} = addr{20-16}; 3930b57cec5SDimitry Andric let Inst{10-6} = wd; 3940b57cec5SDimitry Andric let Inst{5-2} = minor; 3950b57cec5SDimitry Andric let Inst{1-0} = df; 3960b57cec5SDimitry Andric} 3970b57cec5SDimitry Andric 3980b57cec5SDimitry Andricclass MSA_VEC_FMT<bits<5> major, bits<6> minor>: MSAInst { 3990b57cec5SDimitry Andric bits<5> wt; 4000b57cec5SDimitry Andric bits<5> ws; 4010b57cec5SDimitry Andric bits<5> wd; 4020b57cec5SDimitry Andric 4030b57cec5SDimitry Andric let Inst{25-21} = major; 4040b57cec5SDimitry Andric let Inst{20-16} = wt; 4050b57cec5SDimitry Andric let Inst{15-11} = ws; 4060b57cec5SDimitry Andric let Inst{10-6} = wd; 4070b57cec5SDimitry Andric let Inst{5-0} = minor; 4080b57cec5SDimitry Andric} 4090b57cec5SDimitry Andric 4100b57cec5SDimitry Andricclass MSA_CBRANCH_FMT<bits<3> major, bits<2> df>: MSACBranch { 4110b57cec5SDimitry Andric bits<16> offset; 4120b57cec5SDimitry Andric bits<5> wt; 4130b57cec5SDimitry Andric 4140b57cec5SDimitry Andric let Inst{25-23} = major; 4150b57cec5SDimitry Andric let Inst{22-21} = df; 4160b57cec5SDimitry Andric let Inst{20-16} = wt; 4170b57cec5SDimitry Andric let Inst{15-0} = offset; 4180b57cec5SDimitry Andric} 4190b57cec5SDimitry Andric 4200b57cec5SDimitry Andricclass MSA_CBRANCH_V_FMT<bits<5> major>: MSACBranch { 4210b57cec5SDimitry Andric bits<16> offset; 4220b57cec5SDimitry Andric bits<5> wt; 4230b57cec5SDimitry Andric 4240b57cec5SDimitry Andric let Inst{25-21} = major; 4250b57cec5SDimitry Andric let Inst{20-16} = wt; 4260b57cec5SDimitry Andric let Inst{15-0} = offset; 4270b57cec5SDimitry Andric} 4280b57cec5SDimitry Andric 4290b57cec5SDimitry Andricclass SPECIAL_LSA_FMT<bits<6> minor>: MSASpecial { 4300b57cec5SDimitry Andric bits<5> rs; 4310b57cec5SDimitry Andric bits<5> rt; 4320b57cec5SDimitry Andric bits<5> rd; 4330b57cec5SDimitry Andric bits<2> sa; 4340b57cec5SDimitry Andric 4350b57cec5SDimitry Andric let Inst{25-21} = rs; 4360b57cec5SDimitry Andric let Inst{20-16} = rt; 4370b57cec5SDimitry Andric let Inst{15-11} = rd; 4380b57cec5SDimitry Andric let Inst{10-8} = 0b000; 4390b57cec5SDimitry Andric let Inst{7-6} = sa; 4400b57cec5SDimitry Andric let Inst{5-0} = minor; 4410b57cec5SDimitry Andric} 4420b57cec5SDimitry Andric 4430b57cec5SDimitry Andricclass SPECIAL_DLSA_FMT<bits<6> minor>: MSASpecial { 4440b57cec5SDimitry Andric bits<5> rs; 4450b57cec5SDimitry Andric bits<5> rt; 4460b57cec5SDimitry Andric bits<5> rd; 4470b57cec5SDimitry Andric bits<2> sa; 4480b57cec5SDimitry Andric 4490b57cec5SDimitry Andric let Inst{25-21} = rs; 4500b57cec5SDimitry Andric let Inst{20-16} = rt; 4510b57cec5SDimitry Andric let Inst{15-11} = rd; 4520b57cec5SDimitry Andric let Inst{10-8} = 0b000; 4530b57cec5SDimitry Andric let Inst{7-6} = sa; 4540b57cec5SDimitry Andric let Inst{5-0} = minor; 4550b57cec5SDimitry Andric} 456