1 //===- MipsOptimizePICCall.cpp - Optimize PIC Calls -----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This pass eliminates unnecessary instructions that set up $gp and replace
10 // instructions that load target function addresses with copy instructions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MCTargetDesc/MipsBaseInfo.h"
15 #include "Mips.h"
16 #include "MipsRegisterInfo.h"
17 #include "MipsSubtarget.h"
18 #include "llvm/ADT/PointerUnion.h"
19 #include "llvm/ADT/ScopedHashTable.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/CodeGen/MachineBasicBlock.h"
22 #include "llvm/CodeGen/MachineDominators.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineOperand.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/TargetInstrInfo.h"
30 #include "llvm/CodeGen/TargetOpcodes.h"
31 #include "llvm/CodeGen/TargetRegisterInfo.h"
32 #include "llvm/CodeGen/TargetSubtargetInfo.h"
33 #include "llvm/Support/Allocator.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/MachineValueType.h"
37 #include "llvm/Support/RecyclingAllocator.h"
38 #include <cassert>
39 #include <utility>
40 #include <vector>
41 
42 using namespace llvm;
43 
44 #define DEBUG_TYPE "optimize-mips-pic-call"
45 
46 static cl::opt<bool> LoadTargetFromGOT("mips-load-target-from-got",
47                                        cl::init(true),
48                                        cl::desc("Load target address from GOT"),
49                                        cl::Hidden);
50 
51 static cl::opt<bool> EraseGPOpnd("mips-erase-gp-opnd",
52                                  cl::init(true), cl::desc("Erase GP Operand"),
53                                  cl::Hidden);
54 
55 namespace {
56 
57 using ValueType = PointerUnion<const Value *, const PseudoSourceValue *>;
58 using CntRegP = std::pair<unsigned, unsigned>;
59 using AllocatorTy = RecyclingAllocator<BumpPtrAllocator,
60                                        ScopedHashTableVal<ValueType, CntRegP>>;
61 using ScopedHTType = ScopedHashTable<ValueType, CntRegP,
62                                      DenseMapInfo<ValueType>, AllocatorTy>;
63 
64 class MBBInfo {
65 public:
66   MBBInfo(MachineDomTreeNode *N);
67 
68   const MachineDomTreeNode *getNode() const;
69   bool isVisited() const;
70   void preVisit(ScopedHTType &ScopedHT);
71   void postVisit();
72 
73 private:
74   MachineDomTreeNode *Node;
75   ScopedHTType::ScopeTy *HTScope;
76 };
77 
78 class OptimizePICCall : public MachineFunctionPass {
79 public:
80   OptimizePICCall() : MachineFunctionPass(ID) {}
81 
82   StringRef getPassName() const override { return "Mips OptimizePICCall"; }
83 
84   bool runOnMachineFunction(MachineFunction &F) override;
85 
86   void getAnalysisUsage(AnalysisUsage &AU) const override {
87     AU.addRequired<MachineDominatorTree>();
88     MachineFunctionPass::getAnalysisUsage(AU);
89   }
90 
91 private:
92   /// Visit MBB.
93   bool visitNode(MBBInfo &MBBI);
94 
95   /// Test if MI jumps to a function via a register.
96   ///
97   /// Also, return the virtual register containing the target function's address
98   /// and the underlying object in Reg and Val respectively, if the function's
99   /// address can be resolved lazily.
100   bool isCallViaRegister(MachineInstr &MI, unsigned &Reg,
101                          ValueType &Val) const;
102 
103   /// Return the number of instructions that dominate the current
104   /// instruction and load the function address from object Entry.
105   unsigned getCount(ValueType Entry);
106 
107   /// Return the destination virtual register of the last instruction
108   /// that loads from object Entry.
109   unsigned getReg(ValueType Entry);
110 
111   /// Update ScopedHT.
112   void incCntAndSetReg(ValueType Entry, unsigned Reg);
113 
114   ScopedHTType ScopedHT;
115 
116   static char ID;
117 };
118 
119 } // end of anonymous namespace
120 
121 char OptimizePICCall::ID = 0;
122 
123 /// Return the first MachineOperand of MI if it is a used virtual register.
124 static MachineOperand *getCallTargetRegOpnd(MachineInstr &MI) {
125   if (MI.getNumOperands() == 0)
126     return nullptr;
127 
128   MachineOperand &MO = MI.getOperand(0);
129 
130   if (!MO.isReg() || !MO.isUse() || !Register::isVirtualRegister(MO.getReg()))
131     return nullptr;
132 
133   return &MO;
134 }
135 
136 /// Return type of register Reg.
137 static MVT::SimpleValueType getRegTy(unsigned Reg, MachineFunction &MF) {
138   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
139   const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg);
140   assert(TRI.legalclasstypes_end(*RC) - TRI.legalclasstypes_begin(*RC) == 1);
141   return *TRI.legalclasstypes_begin(*RC);
142 }
143 
144 /// Do the following transformation:
145 ///
146 /// jalr $vreg
147 /// =>
148 /// copy $t9, $vreg
149 /// jalr $t9
150 static void setCallTargetReg(MachineBasicBlock *MBB,
151                              MachineBasicBlock::iterator I) {
152   MachineFunction &MF = *MBB->getParent();
153   const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
154   Register SrcReg = I->getOperand(0).getReg();
155   unsigned DstReg = getRegTy(SrcReg, MF) == MVT::i32 ? Mips::T9 : Mips::T9_64;
156   BuildMI(*MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), DstReg)
157       .addReg(SrcReg);
158   I->getOperand(0).setReg(DstReg);
159 }
160 
161 /// Search MI's operands for register GP and erase it.
162 static void eraseGPOpnd(MachineInstr &MI) {
163   if (!EraseGPOpnd)
164     return;
165 
166   MachineFunction &MF = *MI.getParent()->getParent();
167   MVT::SimpleValueType Ty = getRegTy(MI.getOperand(0).getReg(), MF);
168   unsigned Reg = Ty == MVT::i32 ? Mips::GP : Mips::GP_64;
169 
170   for (unsigned I = 0; I < MI.getNumOperands(); ++I) {
171     MachineOperand &MO = MI.getOperand(I);
172     if (MO.isReg() && MO.getReg() == Reg) {
173       MI.RemoveOperand(I);
174       return;
175     }
176   }
177 
178   llvm_unreachable(nullptr);
179 }
180 
181 MBBInfo::MBBInfo(MachineDomTreeNode *N) : Node(N), HTScope(nullptr) {}
182 
183 const MachineDomTreeNode *MBBInfo::getNode() const { return Node; }
184 
185 bool MBBInfo::isVisited() const { return HTScope; }
186 
187 void MBBInfo::preVisit(ScopedHTType &ScopedHT) {
188   HTScope = new ScopedHTType::ScopeTy(ScopedHT);
189 }
190 
191 void MBBInfo::postVisit() {
192   delete HTScope;
193 }
194 
195 // OptimizePICCall methods.
196 bool OptimizePICCall::runOnMachineFunction(MachineFunction &F) {
197   if (static_cast<const MipsSubtarget &>(F.getSubtarget()).inMips16Mode())
198     return false;
199 
200   // Do a pre-order traversal of the dominator tree.
201   MachineDominatorTree *MDT = &getAnalysis<MachineDominatorTree>();
202   bool Changed = false;
203 
204   SmallVector<MBBInfo, 8> WorkList(1, MBBInfo(MDT->getRootNode()));
205 
206   while (!WorkList.empty()) {
207     MBBInfo &MBBI = WorkList.back();
208 
209     // If this MBB has already been visited, destroy the scope for the MBB and
210     // pop it from the work list.
211     if (MBBI.isVisited()) {
212       MBBI.postVisit();
213       WorkList.pop_back();
214       continue;
215     }
216 
217     // Visit the MBB and add its children to the work list.
218     MBBI.preVisit(ScopedHT);
219     Changed |= visitNode(MBBI);
220     const MachineDomTreeNode *Node = MBBI.getNode();
221     const std::vector<MachineDomTreeNode *> &Children = Node->getChildren();
222     WorkList.append(Children.begin(), Children.end());
223   }
224 
225   return Changed;
226 }
227 
228 bool OptimizePICCall::visitNode(MBBInfo &MBBI) {
229   bool Changed = false;
230   MachineBasicBlock *MBB = MBBI.getNode()->getBlock();
231 
232   for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
233        ++I) {
234     unsigned Reg;
235     ValueType Entry;
236 
237     // Skip instructions that are not call instructions via registers.
238     if (!isCallViaRegister(*I, Reg, Entry))
239       continue;
240 
241     Changed = true;
242     unsigned N = getCount(Entry);
243 
244     if (N != 0) {
245       // If a function has been called more than twice, we do not have to emit a
246       // load instruction to get the function address from the GOT, but can
247       // instead reuse the address that has been loaded before.
248       if (N >= 2 && !LoadTargetFromGOT)
249         getCallTargetRegOpnd(*I)->setReg(getReg(Entry));
250 
251       // Erase the $gp operand if this isn't the first time a function has
252       // been called. $gp needs to be set up only if the function call can go
253       // through a lazy binding stub.
254       eraseGPOpnd(*I);
255     }
256 
257     if (Entry)
258       incCntAndSetReg(Entry, Reg);
259 
260     setCallTargetReg(MBB, I);
261   }
262 
263   return Changed;
264 }
265 
266 bool OptimizePICCall::isCallViaRegister(MachineInstr &MI, unsigned &Reg,
267                                         ValueType &Val) const {
268   if (!MI.isCall())
269     return false;
270 
271   MachineOperand *MO = getCallTargetRegOpnd(MI);
272 
273   // Return if MI is not a function call via a register.
274   if (!MO)
275     return false;
276 
277   // Get the instruction that loads the function address from the GOT.
278   Reg = MO->getReg();
279   Val = nullptr;
280   MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
281   MachineInstr *DefMI = MRI.getVRegDef(Reg);
282 
283   assert(DefMI);
284 
285   // See if DefMI is an instruction that loads from a GOT entry that holds the
286   // address of a lazy binding stub.
287   if (!DefMI->mayLoad() || DefMI->getNumOperands() < 3)
288     return true;
289 
290   unsigned Flags = DefMI->getOperand(2).getTargetFlags();
291 
292   if (Flags != MipsII::MO_GOT_CALL && Flags != MipsII::MO_CALL_LO16)
293     return true;
294 
295   // Return the underlying object for the GOT entry in Val.
296   assert(DefMI->hasOneMemOperand());
297   Val = (*DefMI->memoperands_begin())->getValue();
298   if (!Val)
299     Val = (*DefMI->memoperands_begin())->getPseudoValue();
300   return true;
301 }
302 
303 unsigned OptimizePICCall::getCount(ValueType Entry) {
304   return ScopedHT.lookup(Entry).first;
305 }
306 
307 unsigned OptimizePICCall::getReg(ValueType Entry) {
308   unsigned Reg = ScopedHT.lookup(Entry).second;
309   assert(Reg);
310   return Reg;
311 }
312 
313 void OptimizePICCall::incCntAndSetReg(ValueType Entry, unsigned Reg) {
314   CntRegP P = ScopedHT.lookup(Entry);
315   ScopedHT.insert(Entry, std::make_pair(P.first + 1, Reg));
316 }
317 
318 /// Return an OptimizeCall object.
319 FunctionPass *llvm::createMipsOptimizePICCallPass() {
320   return new OptimizePICCall();
321 }
322