1 //===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the Mips specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsSubtarget.h"
14 #include "Mips.h"
15 #include "MipsCallLowering.h"
16 #include "MipsLegalizerInfo.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsRegisterBankInfo.h"
19 #include "MipsRegisterInfo.h"
20 #include "MipsTargetMachine.h"
21 #include "llvm/IR/Attributes.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/MC/TargetRegistry.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/raw_ostream.h"
27 
28 using namespace llvm;
29 
30 #define DEBUG_TYPE "mips-subtarget"
31 
32 #define GET_SUBTARGETINFO_TARGET_DESC
33 #define GET_SUBTARGETINFO_CTOR
34 #include "MipsGenSubtargetInfo.inc"
35 
36 // FIXME: Maybe this should be on by default when Mips16 is specified
37 //
38 static cl::opt<bool>
39     Mixed16_32("mips-mixed-16-32", cl::init(false),
40                cl::desc("Allow for a mixture of Mips16 "
41                         "and Mips32 code in a single output file"),
42                cl::Hidden);
43 
44 static cl::opt<bool> Mips_Os16("mips-os16", cl::init(false),
45                                cl::desc("Compile all functions that don't use "
46                                         "floating point as Mips 16"),
47                                cl::Hidden);
48 
49 static cl::opt<bool> Mips16HardFloat("mips16-hard-float", cl::NotHidden,
50                                      cl::desc("Enable mips16 hard float."),
51                                      cl::init(false));
52 
53 static cl::opt<bool>
54     Mips16ConstantIslands("mips16-constant-islands", cl::NotHidden,
55                           cl::desc("Enable mips16 constant islands."),
56                           cl::init(true));
57 
58 static cl::opt<bool>
59     GPOpt("mgpopt", cl::Hidden,
60           cl::desc("Enable gp-relative addressing of mips small data items"));
61 
62 bool MipsSubtarget::DspWarningPrinted = false;
63 bool MipsSubtarget::MSAWarningPrinted = false;
64 bool MipsSubtarget::VirtWarningPrinted = false;
65 bool MipsSubtarget::CRCWarningPrinted = false;
66 bool MipsSubtarget::GINVWarningPrinted = false;
67 bool MipsSubtarget::MIPS1WarningPrinted = false;
68 
69 void MipsSubtarget::anchor() {}
70 
71 MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
72                              bool little, const MipsTargetMachine &TM,
73                              MaybeAlign StackAlignOverride)
74     : MipsGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
75       MipsArchVersion(MipsDefault), IsLittle(little), IsSoftFloat(false),
76       IsSingleFloat(false), IsFPXX(false), NoABICalls(false), Abs2008(false),
77       IsFP64bit(false), UseOddSPReg(true), IsNaN2008bit(false),
78       IsGP64bit(false), HasVFPU(false), HasCnMips(false), HasCnMipsP(false),
79       HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
80       HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
81       InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
82       HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 || Mips_Os16),
83       Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false),
84       HasEVA(false), DisableMadd4(false), HasMT(false), HasCRC(false),
85       HasVirt(false), HasGINV(false), UseIndirectJumpsHazard(false),
86       StackAlignOverride(StackAlignOverride), TM(TM), TargetTriple(TT),
87       TSInfo(), InstrInfo(MipsInstrInfo::create(
88                     initializeSubtargetDependencies(CPU, FS, TM))),
89       FrameLowering(MipsFrameLowering::create(*this)),
90       TLInfo(MipsTargetLowering::create(TM, *this)) {
91 
92   if (MipsArchVersion == MipsDefault)
93     MipsArchVersion = Mips32;
94 
95   // MIPS-I has not been tested.
96   if (MipsArchVersion == Mips1 && !MIPS1WarningPrinted) {
97     errs() << "warning: MIPS-I support is experimental\n";
98     MIPS1WarningPrinted = true;
99   }
100 
101   // Don't even attempt to generate code for MIPS-V. It has not
102   // been tested and currently exists for the integrated assembler only.
103   if (MipsArchVersion == Mips5)
104     report_fatal_error("Code generation for MIPS-V is not implemented", false);
105 
106   // Check if Architecture and ABI are compatible.
107   assert(((!isGP64bit() && isABI_O32()) || isGP64bit()) &&
108          "Invalid  Arch & ABI pair.");
109 
110   if (hasMSA() && !isFP64bit())
111     report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). "
112                        "See -mattr=+fp64.",
113                        false);
114 
115   if (isFP64bit() && !hasMips64() && hasMips32() && !hasMips32r2())
116     report_fatal_error(
117         "FPU with 64-bit registers is not available on MIPS32 pre revision 2. "
118         "Use -mcpu=mips32r2 or greater.", false);
119 
120   if (!isABI_O32() && !useOddSPReg())
121     report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false);
122 
123   if (IsFPXX && (isABI_N32() || isABI_N64()))
124     report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false);
125 
126   if (hasMips64r6() && InMicroMipsMode)
127     report_fatal_error("microMIPS64R6 is not supported", false);
128 
129   if (!isABI_O32() && InMicroMipsMode)
130     report_fatal_error("microMIPS64 is not supported.", false);
131 
132   if (UseIndirectJumpsHazard) {
133     if (InMicroMipsMode)
134       report_fatal_error(
135           "cannot combine indirect jumps with hazard barriers and microMIPS");
136     if (!hasMips32r2())
137       report_fatal_error(
138           "indirect jumps with hazard barriers requires MIPS32R2 or later");
139   }
140   if (inAbs2008Mode() && hasMips32() && !hasMips32r2()) {
141     report_fatal_error("IEEE 754-2008 abs.fmt is not supported for the given "
142                        "architecture.",
143                        false);
144   }
145 
146   if (hasMips32r6()) {
147     StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
148 
149     assert(isFP64bit());
150     assert(isNaN2008());
151     assert(inAbs2008Mode());
152     if (hasDSP())
153       report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
154   }
155 
156   if (NoABICalls && TM.isPositionIndependent())
157     report_fatal_error("position-independent code requires '-mabicalls'");
158 
159   if (isABI_N64() && !TM.isPositionIndependent() && !hasSym32())
160     NoABICalls = true;
161 
162   // Set UseSmallSection.
163   UseSmallSection = GPOpt;
164   if (!NoABICalls && GPOpt) {
165     errs() << "warning: cannot use small-data accesses for '-mabicalls'"
166            << "\n";
167     UseSmallSection = false;
168   }
169 
170   if (hasDSPR2() && !DspWarningPrinted) {
171     if (hasMips64() && !hasMips64r2()) {
172       errs() << "warning: the 'dspr2' ASE requires MIPS64 revision 2 or "
173              << "greater\n";
174       DspWarningPrinted = true;
175     } else if (hasMips32() && !hasMips32r2()) {
176       errs() << "warning: the 'dspr2' ASE requires MIPS32 revision 2 or "
177              << "greater\n";
178       DspWarningPrinted = true;
179     }
180   } else if (hasDSP() && !DspWarningPrinted) {
181     if (hasMips64() && !hasMips64r2()) {
182       errs() << "warning: the 'dsp' ASE requires MIPS64 revision 2 or "
183              << "greater\n";
184       DspWarningPrinted = true;
185     } else if (hasMips32() && !hasMips32r2()) {
186       errs() << "warning: the 'dsp' ASE requires MIPS32 revision 2 or "
187              << "greater\n";
188       DspWarningPrinted = true;
189     }
190   }
191 
192   StringRef ArchName = hasMips64() ? "MIPS64" : "MIPS32";
193 
194   if (!hasMips32r5() && hasMSA() && !MSAWarningPrinted) {
195     errs() << "warning: the 'msa' ASE requires " << ArchName
196            << " revision 5 or greater\n";
197     MSAWarningPrinted = true;
198   }
199   if (!hasMips32r5() && hasVirt() && !VirtWarningPrinted) {
200     errs() << "warning: the 'virt' ASE requires " << ArchName
201            << " revision 5 or greater\n";
202     VirtWarningPrinted = true;
203   }
204   if (!hasMips32r6() && hasCRC() && !CRCWarningPrinted) {
205     errs() << "warning: the 'crc' ASE requires " << ArchName
206            << " revision 6 or greater\n";
207     CRCWarningPrinted = true;
208   }
209   if (!hasMips32r6() && hasGINV() && !GINVWarningPrinted) {
210     errs() << "warning: the 'ginv' ASE requires " << ArchName
211            << " revision 6 or greater\n";
212     GINVWarningPrinted = true;
213   }
214 
215   CallLoweringInfo.reset(new MipsCallLowering(*getTargetLowering()));
216   Legalizer.reset(new MipsLegalizerInfo(*this));
217 
218   auto *RBI = new MipsRegisterBankInfo(*getRegisterInfo());
219   RegBankInfo.reset(RBI);
220   InstSelector.reset(createMipsInstructionSelector(
221       *static_cast<const MipsTargetMachine *>(&TM), *this, *RBI));
222 }
223 
224 bool MipsSubtarget::isPositionIndependent() const {
225   return TM.isPositionIndependent();
226 }
227 
228 /// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
229 bool MipsSubtarget::enablePostRAScheduler() const { return true; }
230 
231 void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
232   CriticalPathRCs.clear();
233   CriticalPathRCs.push_back(isGP64bit() ? &Mips::GPR64RegClass
234                                         : &Mips::GPR32RegClass);
235 }
236 
237 CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
238   return CodeGenOpt::Aggressive;
239 }
240 
241 MipsSubtarget &
242 MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
243                                                const TargetMachine &TM) {
244   StringRef CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU);
245 
246   // Parse features string.
247   ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS);
248   // Initialize scheduling itinerary for the specified CPU.
249   InstrItins = getInstrItineraryForCPU(CPUName);
250 
251   if (InMips16Mode && !IsSoftFloat)
252     InMips16HardFloat = true;
253 
254   if (StackAlignOverride)
255     stackAlignment = *StackAlignOverride;
256   else if (isABI_N32() || isABI_N64())
257     stackAlignment = Align(16);
258   else {
259     assert(isABI_O32() && "Unknown ABI for stack alignment!");
260     stackAlignment = Align(8);
261   }
262 
263   if ((isABI_N32() || isABI_N64()) && !isGP64bit())
264     report_fatal_error("64-bit code requested on a subtarget that doesn't "
265                        "support it!");
266 
267   return *this;
268 }
269 
270 bool MipsSubtarget::useConstantIslands() {
271   LLVM_DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands
272                     << "\n");
273   return Mips16ConstantIslands;
274 }
275 
276 Reloc::Model MipsSubtarget::getRelocationModel() const {
277   return TM.getRelocationModel();
278 }
279 
280 bool MipsSubtarget::isABI_N64() const { return getABI().IsN64(); }
281 bool MipsSubtarget::isABI_N32() const { return getABI().IsN32(); }
282 bool MipsSubtarget::isABI_O32() const { return getABI().IsO32(); }
283 const MipsABIInfo &MipsSubtarget::getABI() const { return TM.getABI(); }
284 
285 const CallLowering *MipsSubtarget::getCallLowering() const {
286   return CallLoweringInfo.get();
287 }
288 
289 const LegalizerInfo *MipsSubtarget::getLegalizerInfo() const {
290   return Legalizer.get();
291 }
292 
293 const RegisterBankInfo *MipsSubtarget::getRegBankInfo() const {
294   return RegBankInfo.get();
295 }
296 
297 InstructionSelector *MipsSubtarget::getInstructionSelector() const {
298   return InstSelector.get();
299 }
300