1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // Implements the info about Mips target spec. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MipsTargetMachine.h" 14 #include "MCTargetDesc/MipsABIInfo.h" 15 #include "MCTargetDesc/MipsMCTargetDesc.h" 16 #include "Mips.h" 17 #include "Mips16ISelDAGToDAG.h" 18 #include "MipsSEISelDAGToDAG.h" 19 #include "MipsSubtarget.h" 20 #include "MipsTargetObjectFile.h" 21 #include "TargetInfo/MipsTargetInfo.h" 22 #include "llvm/ADT/Optional.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringRef.h" 25 #include "llvm/Analysis/TargetTransformInfo.h" 26 #include "llvm/CodeGen/BasicTTIImpl.h" 27 #include "llvm/CodeGen/GlobalISel/IRTranslator.h" 28 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h" 29 #include "llvm/CodeGen/GlobalISel/Legalizer.h" 30 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h" 31 #include "llvm/CodeGen/MachineFunction.h" 32 #include "llvm/CodeGen/Passes.h" 33 #include "llvm/CodeGen/TargetPassConfig.h" 34 #include "llvm/IR/Attributes.h" 35 #include "llvm/IR/Function.h" 36 #include "llvm/InitializePasses.h" 37 #include "llvm/Support/CodeGen.h" 38 #include "llvm/Support/Debug.h" 39 #include "llvm/Support/TargetRegistry.h" 40 #include "llvm/Support/raw_ostream.h" 41 #include "llvm/Target/TargetOptions.h" 42 #include <string> 43 44 using namespace llvm; 45 46 #define DEBUG_TYPE "mips" 47 48 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTarget() { 49 // Register the target. 50 RegisterTargetMachine<MipsebTargetMachine> X(getTheMipsTarget()); 51 RegisterTargetMachine<MipselTargetMachine> Y(getTheMipselTarget()); 52 RegisterTargetMachine<MipsebTargetMachine> A(getTheMips64Target()); 53 RegisterTargetMachine<MipselTargetMachine> B(getTheMips64elTarget()); 54 55 PassRegistry *PR = PassRegistry::getPassRegistry(); 56 initializeGlobalISel(*PR); 57 initializeMipsDelaySlotFillerPass(*PR); 58 initializeMipsBranchExpansionPass(*PR); 59 initializeMicroMipsSizeReducePass(*PR); 60 initializeMipsPreLegalizerCombinerPass(*PR); 61 } 62 63 static std::string computeDataLayout(const Triple &TT, StringRef CPU, 64 const TargetOptions &Options, 65 bool isLittle) { 66 std::string Ret; 67 MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions); 68 69 // There are both little and big endian mips. 70 if (isLittle) 71 Ret += "e"; 72 else 73 Ret += "E"; 74 75 if (ABI.IsO32()) 76 Ret += "-m:m"; 77 else 78 Ret += "-m:e"; 79 80 // Pointers are 32 bit on some ABIs. 81 if (!ABI.IsN64()) 82 Ret += "-p:32:32"; 83 84 // 8 and 16 bit integers only need to have natural alignment, but try to 85 // align them to 32 bits. 64 bit integers have natural alignment. 86 Ret += "-i8:8:32-i16:16:32-i64:64"; 87 88 // 32 bit registers are always available and the stack is at least 64 bit 89 // aligned. On N64 64 bit registers are also available and the stack is 90 // 128 bit aligned. 91 if (ABI.IsN64() || ABI.IsN32()) 92 Ret += "-n32:64-S128"; 93 else 94 Ret += "-n32-S64"; 95 96 return Ret; 97 } 98 99 static Reloc::Model getEffectiveRelocModel(bool JIT, 100 Optional<Reloc::Model> RM) { 101 if (!RM.hasValue() || JIT) 102 return Reloc::Static; 103 return *RM; 104 } 105 106 // On function prologue, the stack is created by decrementing 107 // its pointer. Once decremented, all references are done with positive 108 // offset from the stack/frame pointer, using StackGrowsUp enables 109 // an easier handling. 110 // Using CodeModel::Large enables different CALL behavior. 111 MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT, 112 StringRef CPU, StringRef FS, 113 const TargetOptions &Options, 114 Optional<Reloc::Model> RM, 115 Optional<CodeModel::Model> CM, 116 CodeGenOpt::Level OL, bool JIT, 117 bool isLittle) 118 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, 119 CPU, FS, Options, getEffectiveRelocModel(JIT, RM), 120 getEffectiveCodeModel(CM, CodeModel::Small), OL), 121 isLittle(isLittle), TLOF(std::make_unique<MipsTargetObjectFile>()), 122 ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)), 123 Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this, None), 124 NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16", 125 isLittle, *this, None), 126 Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16", 127 isLittle, *this, None) { 128 Subtarget = &DefaultSubtarget; 129 initAsmInfo(); 130 131 // Mips supports the debug entry values. 132 setSupportsDebugEntryValues(true); 133 } 134 135 MipsTargetMachine::~MipsTargetMachine() = default; 136 137 void MipsebTargetMachine::anchor() {} 138 139 MipsebTargetMachine::MipsebTargetMachine(const Target &T, const Triple &TT, 140 StringRef CPU, StringRef FS, 141 const TargetOptions &Options, 142 Optional<Reloc::Model> RM, 143 Optional<CodeModel::Model> CM, 144 CodeGenOpt::Level OL, bool JIT) 145 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {} 146 147 void MipselTargetMachine::anchor() {} 148 149 MipselTargetMachine::MipselTargetMachine(const Target &T, const Triple &TT, 150 StringRef CPU, StringRef FS, 151 const TargetOptions &Options, 152 Optional<Reloc::Model> RM, 153 Optional<CodeModel::Model> CM, 154 CodeGenOpt::Level OL, bool JIT) 155 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {} 156 157 const MipsSubtarget * 158 MipsTargetMachine::getSubtargetImpl(const Function &F) const { 159 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 160 Attribute FSAttr = F.getFnAttribute("target-features"); 161 162 std::string CPU = 163 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU; 164 std::string FS = 165 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS; 166 bool hasMips16Attr = F.getFnAttribute("mips16").isValid(); 167 bool hasNoMips16Attr = F.getFnAttribute("nomips16").isValid(); 168 169 bool HasMicroMipsAttr = F.getFnAttribute("micromips").isValid(); 170 bool HasNoMicroMipsAttr = F.getFnAttribute("nomicromips").isValid(); 171 172 // FIXME: This is related to the code below to reset the target options, 173 // we need to know whether or not the soft float flag is set on the 174 // function, so we can enable it as a subtarget feature. 175 bool softFloat = F.getFnAttribute("use-soft-float").getValueAsBool(); 176 177 if (hasMips16Attr) 178 FS += FS.empty() ? "+mips16" : ",+mips16"; 179 else if (hasNoMips16Attr) 180 FS += FS.empty() ? "-mips16" : ",-mips16"; 181 if (HasMicroMipsAttr) 182 FS += FS.empty() ? "+micromips" : ",+micromips"; 183 else if (HasNoMicroMipsAttr) 184 FS += FS.empty() ? "-micromips" : ",-micromips"; 185 if (softFloat) 186 FS += FS.empty() ? "+soft-float" : ",+soft-float"; 187 188 auto &I = SubtargetMap[CPU + FS]; 189 if (!I) { 190 // This needs to be done before we create a new subtarget since any 191 // creation will depend on the TM and the code generation flags on the 192 // function that reside in TargetOptions. 193 resetTargetOptions(F); 194 I = std::make_unique<MipsSubtarget>( 195 TargetTriple, CPU, FS, isLittle, *this, 196 MaybeAlign(F.getParent()->getOverrideStackAlignment())); 197 } 198 return I.get(); 199 } 200 201 void MipsTargetMachine::resetSubtarget(MachineFunction *MF) { 202 LLVM_DEBUG(dbgs() << "resetSubtarget\n"); 203 204 Subtarget = &MF->getSubtarget<MipsSubtarget>(); 205 } 206 207 namespace { 208 209 /// Mips Code Generator Pass Configuration Options. 210 class MipsPassConfig : public TargetPassConfig { 211 public: 212 MipsPassConfig(MipsTargetMachine &TM, PassManagerBase &PM) 213 : TargetPassConfig(TM, PM) { 214 // The current implementation of long branch pass requires a scratch 215 // register ($at) to be available before branch instructions. Tail merging 216 // can break this requirement, so disable it when long branch pass is 217 // enabled. 218 EnableTailMerge = !getMipsSubtarget().enableLongBranchPass(); 219 } 220 221 MipsTargetMachine &getMipsTargetMachine() const { 222 return getTM<MipsTargetMachine>(); 223 } 224 225 const MipsSubtarget &getMipsSubtarget() const { 226 return *getMipsTargetMachine().getSubtargetImpl(); 227 } 228 229 void addIRPasses() override; 230 bool addInstSelector() override; 231 void addPreEmitPass() override; 232 void addPreRegAlloc() override; 233 bool addIRTranslator() override; 234 void addPreLegalizeMachineIR() override; 235 bool addLegalizeMachineIR() override; 236 bool addRegBankSelect() override; 237 bool addGlobalInstructionSelect() override; 238 239 std::unique_ptr<CSEConfigBase> getCSEConfig() const override; 240 }; 241 242 } // end anonymous namespace 243 244 TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) { 245 return new MipsPassConfig(*this, PM); 246 } 247 248 std::unique_ptr<CSEConfigBase> MipsPassConfig::getCSEConfig() const { 249 return getStandardCSEConfigForOpt(TM->getOptLevel()); 250 } 251 252 void MipsPassConfig::addIRPasses() { 253 TargetPassConfig::addIRPasses(); 254 addPass(createAtomicExpandPass()); 255 if (getMipsSubtarget().os16()) 256 addPass(createMipsOs16Pass()); 257 if (getMipsSubtarget().inMips16HardFloat()) 258 addPass(createMips16HardFloatPass()); 259 } 260 // Install an instruction selector pass using 261 // the ISelDag to gen Mips code. 262 bool MipsPassConfig::addInstSelector() { 263 addPass(createMipsModuleISelDagPass()); 264 addPass(createMips16ISelDag(getMipsTargetMachine(), getOptLevel())); 265 addPass(createMipsSEISelDag(getMipsTargetMachine(), getOptLevel())); 266 return false; 267 } 268 269 void MipsPassConfig::addPreRegAlloc() { 270 addPass(createMipsOptimizePICCallPass()); 271 } 272 273 TargetTransformInfo 274 MipsTargetMachine::getTargetTransformInfo(const Function &F) { 275 if (Subtarget->allowMixed16_32()) { 276 LLVM_DEBUG(errs() << "No Target Transform Info Pass Added\n"); 277 // FIXME: This is no longer necessary as the TTI returned is per-function. 278 return TargetTransformInfo(F.getParent()->getDataLayout()); 279 } 280 281 LLVM_DEBUG(errs() << "Target Transform Info Pass Added\n"); 282 return TargetTransformInfo(BasicTTIImpl(this, F)); 283 } 284 285 // Implemented by targets that want to run passes immediately before 286 // machine code is emitted. 287 void MipsPassConfig::addPreEmitPass() { 288 // Expand pseudo instructions that are sensitive to register allocation. 289 addPass(createMipsExpandPseudoPass()); 290 291 // The microMIPS size reduction pass performs instruction reselection for 292 // instructions which can be remapped to a 16 bit instruction. 293 addPass(createMicroMipsSizeReducePass()); 294 295 // The delay slot filler pass can potientially create forbidden slot hazards 296 // for MIPSR6 and therefore it should go before MipsBranchExpansion pass. 297 addPass(createMipsDelaySlotFillerPass()); 298 299 // This pass expands branches and takes care about the forbidden slot hazards. 300 // Expanding branches may potentially create forbidden slot hazards for 301 // MIPSR6, and fixing such hazard may potentially break a branch by extending 302 // its offset out of range. That's why this pass combine these two tasks, and 303 // runs them alternately until one of them finishes without any changes. Only 304 // then we can be sure that all branches are expanded properly and no hazards 305 // exists. 306 // Any new pass should go before this pass. 307 addPass(createMipsBranchExpansion()); 308 309 addPass(createMipsConstantIslandPass()); 310 } 311 312 bool MipsPassConfig::addIRTranslator() { 313 addPass(new IRTranslator(getOptLevel())); 314 return false; 315 } 316 317 void MipsPassConfig::addPreLegalizeMachineIR() { 318 addPass(createMipsPreLegalizeCombiner()); 319 } 320 321 bool MipsPassConfig::addLegalizeMachineIR() { 322 addPass(new Legalizer()); 323 return false; 324 } 325 326 bool MipsPassConfig::addRegBankSelect() { 327 addPass(new RegBankSelect()); 328 return false; 329 } 330 331 bool MipsPassConfig::addGlobalInstructionSelect() { 332 addPass(new InstructionSelect(getOptLevel())); 333 return false; 334 } 335