1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // Implements the info about Mips target spec. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MipsTargetMachine.h" 14 #include "MCTargetDesc/MipsABIInfo.h" 15 #include "MCTargetDesc/MipsMCTargetDesc.h" 16 #include "Mips.h" 17 #include "Mips16ISelDAGToDAG.h" 18 #include "MipsSEISelDAGToDAG.h" 19 #include "MipsSubtarget.h" 20 #include "MipsTargetObjectFile.h" 21 #include "TargetInfo/MipsTargetInfo.h" 22 #include "llvm/ADT/Optional.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringRef.h" 25 #include "llvm/Analysis/TargetTransformInfo.h" 26 #include "llvm/CodeGen/BasicTTIImpl.h" 27 #include "llvm/CodeGen/GlobalISel/IRTranslator.h" 28 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h" 29 #include "llvm/CodeGen/GlobalISel/Legalizer.h" 30 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h" 31 #include "llvm/CodeGen/MachineFunction.h" 32 #include "llvm/CodeGen/Passes.h" 33 #include "llvm/CodeGen/TargetPassConfig.h" 34 #include "llvm/IR/Attributes.h" 35 #include "llvm/IR/Function.h" 36 #include "llvm/InitializePasses.h" 37 #include "llvm/Support/CodeGen.h" 38 #include "llvm/Support/Debug.h" 39 #include "llvm/Support/TargetRegistry.h" 40 #include "llvm/Support/raw_ostream.h" 41 #include "llvm/Target/TargetOptions.h" 42 #include <string> 43 44 using namespace llvm; 45 46 #define DEBUG_TYPE "mips" 47 48 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTarget() { 49 // Register the target. 50 RegisterTargetMachine<MipsebTargetMachine> X(getTheMipsTarget()); 51 RegisterTargetMachine<MipselTargetMachine> Y(getTheMipselTarget()); 52 RegisterTargetMachine<MipsebTargetMachine> A(getTheMips64Target()); 53 RegisterTargetMachine<MipselTargetMachine> B(getTheMips64elTarget()); 54 55 PassRegistry *PR = PassRegistry::getPassRegistry(); 56 initializeGlobalISel(*PR); 57 initializeMipsDelaySlotFillerPass(*PR); 58 initializeMipsBranchExpansionPass(*PR); 59 initializeMicroMipsSizeReducePass(*PR); 60 initializeMipsPreLegalizerCombinerPass(*PR); 61 } 62 63 static std::string computeDataLayout(const Triple &TT, StringRef CPU, 64 const TargetOptions &Options, 65 bool isLittle) { 66 std::string Ret; 67 MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions); 68 69 // There are both little and big endian mips. 70 if (isLittle) 71 Ret += "e"; 72 else 73 Ret += "E"; 74 75 if (ABI.IsO32()) 76 Ret += "-m:m"; 77 else 78 Ret += "-m:e"; 79 80 // Pointers are 32 bit on some ABIs. 81 if (!ABI.IsN64()) 82 Ret += "-p:32:32"; 83 84 // 8 and 16 bit integers only need to have natural alignment, but try to 85 // align them to 32 bits. 64 bit integers have natural alignment. 86 Ret += "-i8:8:32-i16:16:32-i64:64"; 87 88 // 32 bit registers are always available and the stack is at least 64 bit 89 // aligned. On N64 64 bit registers are also available and the stack is 90 // 128 bit aligned. 91 if (ABI.IsN64() || ABI.IsN32()) 92 Ret += "-n32:64-S128"; 93 else 94 Ret += "-n32-S64"; 95 96 return Ret; 97 } 98 99 static Reloc::Model getEffectiveRelocModel(bool JIT, 100 Optional<Reloc::Model> RM) { 101 if (!RM.hasValue() || JIT) 102 return Reloc::Static; 103 return *RM; 104 } 105 106 // On function prologue, the stack is created by decrementing 107 // its pointer. Once decremented, all references are done with positive 108 // offset from the stack/frame pointer, using StackGrowsUp enables 109 // an easier handling. 110 // Using CodeModel::Large enables different CALL behavior. 111 MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT, 112 StringRef CPU, StringRef FS, 113 const TargetOptions &Options, 114 Optional<Reloc::Model> RM, 115 Optional<CodeModel::Model> CM, 116 CodeGenOpt::Level OL, bool JIT, 117 bool isLittle) 118 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, 119 CPU, FS, Options, getEffectiveRelocModel(JIT, RM), 120 getEffectiveCodeModel(CM, CodeModel::Small), OL), 121 isLittle(isLittle), TLOF(std::make_unique<MipsTargetObjectFile>()), 122 ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)), 123 Subtarget(nullptr), 124 DefaultSubtarget(TT, CPU, FS, isLittle, *this, 125 MaybeAlign(Options.StackAlignmentOverride)), 126 NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16", 127 isLittle, *this, 128 MaybeAlign(Options.StackAlignmentOverride)), 129 Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16", 130 isLittle, *this, 131 MaybeAlign(Options.StackAlignmentOverride)) { 132 Subtarget = &DefaultSubtarget; 133 initAsmInfo(); 134 135 // Mips supports the debug entry values. 136 setSupportsDebugEntryValues(true); 137 } 138 139 MipsTargetMachine::~MipsTargetMachine() = default; 140 141 void MipsebTargetMachine::anchor() {} 142 143 MipsebTargetMachine::MipsebTargetMachine(const Target &T, const Triple &TT, 144 StringRef CPU, StringRef FS, 145 const TargetOptions &Options, 146 Optional<Reloc::Model> RM, 147 Optional<CodeModel::Model> CM, 148 CodeGenOpt::Level OL, bool JIT) 149 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {} 150 151 void MipselTargetMachine::anchor() {} 152 153 MipselTargetMachine::MipselTargetMachine(const Target &T, const Triple &TT, 154 StringRef CPU, StringRef FS, 155 const TargetOptions &Options, 156 Optional<Reloc::Model> RM, 157 Optional<CodeModel::Model> CM, 158 CodeGenOpt::Level OL, bool JIT) 159 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {} 160 161 const MipsSubtarget * 162 MipsTargetMachine::getSubtargetImpl(const Function &F) const { 163 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 164 Attribute FSAttr = F.getFnAttribute("target-features"); 165 166 std::string CPU = 167 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU; 168 std::string FS = 169 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS; 170 bool hasMips16Attr = F.getFnAttribute("mips16").isValid(); 171 bool hasNoMips16Attr = F.getFnAttribute("nomips16").isValid(); 172 173 bool HasMicroMipsAttr = F.getFnAttribute("micromips").isValid(); 174 bool HasNoMicroMipsAttr = F.getFnAttribute("nomicromips").isValid(); 175 176 // FIXME: This is related to the code below to reset the target options, 177 // we need to know whether or not the soft float flag is set on the 178 // function, so we can enable it as a subtarget feature. 179 bool softFloat = 180 F.hasFnAttribute("use-soft-float") && 181 F.getFnAttribute("use-soft-float").getValueAsString() == "true"; 182 183 if (hasMips16Attr) 184 FS += FS.empty() ? "+mips16" : ",+mips16"; 185 else if (hasNoMips16Attr) 186 FS += FS.empty() ? "-mips16" : ",-mips16"; 187 if (HasMicroMipsAttr) 188 FS += FS.empty() ? "+micromips" : ",+micromips"; 189 else if (HasNoMicroMipsAttr) 190 FS += FS.empty() ? "-micromips" : ",-micromips"; 191 if (softFloat) 192 FS += FS.empty() ? "+soft-float" : ",+soft-float"; 193 194 auto &I = SubtargetMap[CPU + FS]; 195 if (!I) { 196 // This needs to be done before we create a new subtarget since any 197 // creation will depend on the TM and the code generation flags on the 198 // function that reside in TargetOptions. 199 resetTargetOptions(F); 200 I = std::make_unique<MipsSubtarget>( 201 TargetTriple, CPU, FS, isLittle, *this, 202 MaybeAlign(Options.StackAlignmentOverride)); 203 } 204 return I.get(); 205 } 206 207 void MipsTargetMachine::resetSubtarget(MachineFunction *MF) { 208 LLVM_DEBUG(dbgs() << "resetSubtarget\n"); 209 210 Subtarget = &MF->getSubtarget<MipsSubtarget>(); 211 } 212 213 namespace { 214 215 /// Mips Code Generator Pass Configuration Options. 216 class MipsPassConfig : public TargetPassConfig { 217 public: 218 MipsPassConfig(MipsTargetMachine &TM, PassManagerBase &PM) 219 : TargetPassConfig(TM, PM) { 220 // The current implementation of long branch pass requires a scratch 221 // register ($at) to be available before branch instructions. Tail merging 222 // can break this requirement, so disable it when long branch pass is 223 // enabled. 224 EnableTailMerge = !getMipsSubtarget().enableLongBranchPass(); 225 } 226 227 MipsTargetMachine &getMipsTargetMachine() const { 228 return getTM<MipsTargetMachine>(); 229 } 230 231 const MipsSubtarget &getMipsSubtarget() const { 232 return *getMipsTargetMachine().getSubtargetImpl(); 233 } 234 235 void addIRPasses() override; 236 bool addInstSelector() override; 237 void addPreEmitPass() override; 238 void addPreRegAlloc() override; 239 bool addIRTranslator() override; 240 void addPreLegalizeMachineIR() override; 241 bool addLegalizeMachineIR() override; 242 bool addRegBankSelect() override; 243 bool addGlobalInstructionSelect() override; 244 245 std::unique_ptr<CSEConfigBase> getCSEConfig() const override; 246 }; 247 248 } // end anonymous namespace 249 250 TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) { 251 return new MipsPassConfig(*this, PM); 252 } 253 254 std::unique_ptr<CSEConfigBase> MipsPassConfig::getCSEConfig() const { 255 return getStandardCSEConfigForOpt(TM->getOptLevel()); 256 } 257 258 void MipsPassConfig::addIRPasses() { 259 TargetPassConfig::addIRPasses(); 260 addPass(createAtomicExpandPass()); 261 if (getMipsSubtarget().os16()) 262 addPass(createMipsOs16Pass()); 263 if (getMipsSubtarget().inMips16HardFloat()) 264 addPass(createMips16HardFloatPass()); 265 } 266 // Install an instruction selector pass using 267 // the ISelDag to gen Mips code. 268 bool MipsPassConfig::addInstSelector() { 269 addPass(createMipsModuleISelDagPass()); 270 addPass(createMips16ISelDag(getMipsTargetMachine(), getOptLevel())); 271 addPass(createMipsSEISelDag(getMipsTargetMachine(), getOptLevel())); 272 return false; 273 } 274 275 void MipsPassConfig::addPreRegAlloc() { 276 addPass(createMipsOptimizePICCallPass()); 277 } 278 279 TargetTransformInfo 280 MipsTargetMachine::getTargetTransformInfo(const Function &F) { 281 if (Subtarget->allowMixed16_32()) { 282 LLVM_DEBUG(errs() << "No Target Transform Info Pass Added\n"); 283 // FIXME: This is no longer necessary as the TTI returned is per-function. 284 return TargetTransformInfo(F.getParent()->getDataLayout()); 285 } 286 287 LLVM_DEBUG(errs() << "Target Transform Info Pass Added\n"); 288 return TargetTransformInfo(BasicTTIImpl(this, F)); 289 } 290 291 // Implemented by targets that want to run passes immediately before 292 // machine code is emitted. 293 void MipsPassConfig::addPreEmitPass() { 294 // Expand pseudo instructions that are sensitive to register allocation. 295 addPass(createMipsExpandPseudoPass()); 296 297 // The microMIPS size reduction pass performs instruction reselection for 298 // instructions which can be remapped to a 16 bit instruction. 299 addPass(createMicroMipsSizeReducePass()); 300 301 // The delay slot filler pass can potientially create forbidden slot hazards 302 // for MIPSR6 and therefore it should go before MipsBranchExpansion pass. 303 addPass(createMipsDelaySlotFillerPass()); 304 305 // This pass expands branches and takes care about the forbidden slot hazards. 306 // Expanding branches may potentially create forbidden slot hazards for 307 // MIPSR6, and fixing such hazard may potentially break a branch by extending 308 // its offset out of range. That's why this pass combine these two tasks, and 309 // runs them alternately until one of them finishes without any changes. Only 310 // then we can be sure that all branches are expanded properly and no hazards 311 // exists. 312 // Any new pass should go before this pass. 313 addPass(createMipsBranchExpansion()); 314 315 addPass(createMipsConstantIslandPass()); 316 } 317 318 bool MipsPassConfig::addIRTranslator() { 319 addPass(new IRTranslator(getOptLevel())); 320 return false; 321 } 322 323 void MipsPassConfig::addPreLegalizeMachineIR() { 324 addPass(createMipsPreLegalizeCombiner()); 325 } 326 327 bool MipsPassConfig::addLegalizeMachineIR() { 328 addPass(new Legalizer()); 329 return false; 330 } 331 332 bool MipsPassConfig::addRegBankSelect() { 333 addPass(new RegBankSelect()); 334 return false; 335 } 336 337 bool MipsPassConfig::addGlobalInstructionSelect() { 338 addPass(new InstructionSelect()); 339 return false; 340 } 341